CN105225972B - 一种半导体封装结构的制作方法 - Google Patents

一种半导体封装结构的制作方法 Download PDF

Info

Publication number
CN105225972B
CN105225972B CN201510686880.7A CN201510686880A CN105225972B CN 105225972 B CN105225972 B CN 105225972B CN 201510686880 A CN201510686880 A CN 201510686880A CN 105225972 B CN105225972 B CN 105225972B
Authority
CN
China
Prior art keywords
sheet metal
transparent panel
layer
pin
plastic packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510686880.7A
Other languages
English (en)
Other versions
CN105225972A (zh
Inventor
吴奇斌
吴靖宇
耿丛正
吴莹莹
吴涛
吕磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changjiang Electronics Technology Chuzhou Co Ltd
Original Assignee
Changjiang Electronics Technology Chuzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changjiang Electronics Technology Chuzhou Co Ltd filed Critical Changjiang Electronics Technology Chuzhou Co Ltd
Priority to CN201510686880.7A priority Critical patent/CN105225972B/zh
Publication of CN105225972A publication Critical patent/CN105225972A/zh
Application granted granted Critical
Publication of CN105225972B publication Critical patent/CN105225972B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

本发明涉及一种半导体封装结构的制作方法,该方法主要包括以下步骤:步骤一、取透明板;步骤二、透明板表面涂覆粘性材料;步骤三、贴金属板材;步骤四、金属板材贴膜、曝光显影蚀刻形成管脚;步骤五、电镀金属线路层;步骤六、装片;步骤七、塑封;步骤八、去除透明板;步骤九、金属板材背面电镀金属线路层;步骤十、切割成品。本发明提供的工艺方法简单,且不浪费材料,有效降低封装体厚度的同时还可以提高生产良率。

Description

一种半导体封装结构的制作方法
技术领域
本发明涉及一种半导体封装结构的制作方法。属于集成电路封装领域。
背景技术
随着电子产品的功能越来越齐全,对于半导体封装的尺寸要求越来越小,越来越薄,为了制作超薄的封装结构,一般的制作方式是首先提供基板,在基板的正面设置通过电镀或者蚀刻的方式形成所需的引脚图形,进行装片打线包封流程,然后对基板的背面进行整体蚀刻或者研磨,最后分割成单品,完成整个超薄封装。
现有的技术存在多个缺陷:
1、不能使用薄型的基板,因为薄型基板在封装过程中容易出现翘曲变形的情况,影响正常轨道传输与产品质量,所以必须使用具有一定厚度的基板,最后通过蚀刻或研磨的方式减薄基板得到尺寸较薄的封装结构;
2、现有技术中基板的作用仅仅在于增加强度或者利用部分基板作为线路层,多余的基板厚度都是需要蚀刻或者研磨掉的,不仅材料浪费,也增加了不必要的工艺;
3、如果利用研磨进行基板部分的去除,用力不匀的话可能会导致封装体的破裂,影响产品的良率。
发明内容
本发明的目的在于克服上述不足,提供一种半导体封装结构的制作方法,首先在一块透明板上刷一层粘性材料,该材料经过一种工艺处理即可消失,在粘性材料上面贴薄型金属板材,对薄型金属板材进行蚀刻形成线路,进行正常封装流程,再通过工艺处理,将透明板与产品脱离,最后进行电镀、切割,形成超薄封装产品。该制作方法,工艺简单,且不浪费材料,有效降低封装体厚度的同时还可以提高生产良率。
本发明的目的是这样实现的:一种半导体封装结构的制作方法,该方法主要包括以下步骤:
步骤一、取透明板
取一片厚度合适的透明板;
步骤二、透明板表面涂覆粘性材料
在步骤一的透明板表面刷一层粘性材料;
步骤三、贴金属板材
在步骤二的透明板涂敷粘性材料一面贴一块薄型的金属板材;
步骤四、金属板材贴膜、曝光显影蚀刻形成管脚
在步骤三的金属板材正面贴上可进行曝光显影的光阻膜,利用曝光显影设备将贴光阻膜作业的金属板材正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属板材正面后续需要进行蚀刻的区域图形,对金属板材正面完成曝光显影的区域进行化学蚀刻以形成管脚;
步骤五、电镀金属线路层
在步骤四形成的管脚表面电镀一层金属线路层,形成相应的基岛和引脚;
步骤六、装片
在步骤五形成的金属线路层正面植入芯片与电性焊接;
步骤七、塑封
在步骤六中的金属板材正面采用塑封料进行塑封;
步骤八、去除透明板
在透明板的背面进行曝光显影将粘性材料去除,使得透明板与金属板材脱离;
步骤九、金属板材背面电镀金属层
在步骤五形成的基岛和引脚背面电镀一层金属层;
步骤十、切割成品
对步骤九的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得半导体封装结构。
与现有技术相比,本发明的有益效果是:
1、可以使用薄型的金属板材,直接制作超薄封装结构,且工艺简单,制程稳定。
2、避免了材料的浪费,透明板可以重复使用,节省了成本。
3、针对不同厚度的产品,只需要用相同的包封模具,通过修改透明板的厚度,即可以生产出不同厚度的封装产品,节省了更换包封模具的时间以及成本。
附图说明
图1—图10为本发明一种半导体封装结构的制作方法的流程示意图。
具体实施方式
本发明提供一种半导体封装结构的制作方法,该方法主要包括以下步骤:
步骤一、取透明板
参见图1,取一片厚度合适的透明板,此板材使用的目的只是为降低金属板材厚度同时确保后续线路制作支撑强度的过渡性材料,此透明板可以选用钢化玻璃等强度较高且透明的板材。
步骤二、透明板表面涂覆粘性材料
参见图2,在步骤一的透明板表面刷一层粘性材料,该材料可以通过曝光显影去除,如曝光显影膜,涂覆粘性材料一方面为了后续贴上金属板材,另一方面便于透明板的脱离。
步骤三、贴金属板材
参见图3,取一块薄型的金属板材,将金属板材通过步骤二的粘性材料贴于透明板上,此板材的材质主要是以金属材料为主,而金属材料的材质可以是铜材﹑铁材﹑镀锌材﹑不锈钢材﹑铝材或可以达到导电功能的金属物质等。
步骤四、金属板材贴膜、曝光显影蚀刻形成管脚
参见图4,在步骤三的金属板材正面贴上可进行曝光显影的光阻膜,以保护后续的电镀金属层工艺作业,光阻膜可以是干式光阻膜也可以是湿式光阻膜,利用曝光显影设备将贴光阻膜作业的金属板材正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属板材正面后续需要进行蚀刻的区域图形,对金属板材正面完成曝光显影的区域进行化学蚀刻以形成管脚,化学蚀刻直至粘性材料为止,蚀刻药水可以采用氯化铜或是氯化铁或是可以进行化学蚀刻的药水。
步骤五、电镀金属线路层
参见图5,在步骤四形成的管脚表面电镀一层金属线路层,形成相应的基岛和引脚,金属线路层材料可以是铜、铝、镍、银、金、铜银、镍金、镍钯金(通常5~20微米,可以根据不同特性变换电镀的厚度)等材料,当然其它可以导电的金属物质都可以使用,并不局限铜、铝、镍、银、金、铜银、镍金、镍钯金等金属材料,电镀方式可以是化学沉积或是电解电镀方式。
步骤六、装片
参见图6,在步骤五形成的金属线路层正面植入芯片,植入方式可以采用正装或倒装,采用正装时在基岛正面涂覆导电或是不导电的粘结物质后将芯片与基岛接合,在芯片正面与引脚正面之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或是合金的材料,金属丝的形状可以是丝状也可以是带状;采用倒装时可以将底部填充胶涂覆在基岛和引脚上再倒装上芯片或是将底部充胶涂覆在芯片正面后倒装于基岛和引脚正面。
步骤七、塑封
参见图6,在步骤六中的金属板材正面采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、喷涂设备喷涂方式或是用贴膜方式。所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。
步骤八、去除透明板
参见图8,在透明板的背面进行曝光显影将粘性材料去除,使得透明板与金属板材脱离,由于选用了透明板,同时粘性材料为曝光显影膜,可直接在透明板的背面进行曝光显影将粘性材料去除,从而实现透明板与上方产品的脱离。
步骤九、金属板材背面电镀金属层
参见图9,在步骤五形成的基岛和引脚背面电镀一层金属层,金属线路层材料可以是锡。
步骤十、切割成品
参见图10,对步骤九的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得半导体封装结构,可采用常规的钻石刀片及常规的切割设备即可。

Claims (1)

1.一种半导体封装结构的制作方法,其特征在于:该方法主要包括以下步骤:
步骤一、取透明板
取一片透明板;
步骤二、透明板表面涂覆粘性材料
在步骤一的透明板表面刷一层粘性材料;
步骤三、贴金属板材
取一块薄型的金属板材,将金属板通过粘性材料贴于透明板上方;
步骤四、金属板材贴膜、曝光显影蚀刻形成管脚
在步骤三的金属板材正面贴上可进行曝光显影的光阻膜,利用曝光显影设备将贴光阻膜作业的金属板材正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属板材正面后续需要进行蚀刻的区域图形,对金属板材正面完成曝光显影的区域进行化学蚀刻以形成管脚;
步骤五、电镀金属线路层
在步骤四形成的管脚表面电镀一层金属线路层,形成相应的基岛和引脚;
步骤六、装片
在步骤五形成的金属线路层正面植入芯片与电性焊接;
步骤七、塑封
在步骤六中的金属板材正面采用塑封料进行塑封;
步骤八、去除透明板
在透明板的背面进行曝光显影将粘性材料去除,使得透明板与金属板材脱离;
步骤九、金属板材背面电镀金属层
在步骤五形成的基岛和引脚背面电镀一层金属层;
步骤十、切割成品
对步骤九的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得半导体封装结构。
CN201510686880.7A 2015-10-22 2015-10-22 一种半导体封装结构的制作方法 Active CN105225972B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510686880.7A CN105225972B (zh) 2015-10-22 2015-10-22 一种半导体封装结构的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510686880.7A CN105225972B (zh) 2015-10-22 2015-10-22 一种半导体封装结构的制作方法

Publications (2)

Publication Number Publication Date
CN105225972A CN105225972A (zh) 2016-01-06
CN105225972B true CN105225972B (zh) 2017-09-26

Family

ID=54994845

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510686880.7A Active CN105225972B (zh) 2015-10-22 2015-10-22 一种半导体封装结构的制作方法

Country Status (1)

Country Link
CN (1) CN105225972B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109626319A (zh) * 2019-01-11 2019-04-16 清华大学 一种植入式器件及其封装方法
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
CN114407455B (zh) * 2021-12-29 2023-08-18 沈阳和研科技股份有限公司 小颗粒电子封装材料加工用复合夹层结构及其加工方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG142321A1 (en) * 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
DE102008047964A1 (de) * 2008-09-18 2010-03-25 Tesa Se Verfahren zur Kapselung einer elektronischen Anordnung
KR20120084194A (ko) * 2011-01-19 2012-07-27 삼성전자주식회사 반도체 패키지 제조방법 및 반도체 패키지용 다이
US20140131897A1 (en) * 2012-11-15 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control for Flexible Substrates
US9412702B2 (en) * 2013-03-14 2016-08-09 Intel Corporation Laser die backside film removal for integrated circuit (IC) packaging

Also Published As

Publication number Publication date
CN105225972A (zh) 2016-01-06

Similar Documents

Publication Publication Date Title
CN102005432B (zh) 四面无引脚封装结构及其封装方法
US8375577B2 (en) Method of making foil based semiconductor package
TW201232673A (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN105225972B (zh) 一种半导体封装结构的制作方法
CN110473853A (zh) 一种dfn器件的封装结构、无引线框架载体及dfn器件的封装方法
CN105428325B (zh) 一种带金属屏蔽层的单层超薄基板封装结构的制备工艺及其制品
CN103730442B (zh) 带焊球面阵列四边无引脚封装体堆叠封装件及制备方法
CN106783790A (zh) 一种具有低电阻损耗三维封装结构及其工艺方法
CN101996889A (zh) 超薄封装工艺
CN103400775B (zh) 先封后蚀三维系统级芯片倒装凸点封装结构及工艺方法
CN102263077A (zh) 一种双扁平无载体无引脚的ic芯片封装件
CN104347542A (zh) 五面包封的csp结构及制造工艺
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN108648999A (zh) 半导体的封装方法
CN201838581U (zh) 四面无引脚封装结构
CN107910288A (zh) 基于太鼓晶圆的晶圆级封装结构及方法
CN101853832B (zh) 基岛露出型及埋入型基岛引线框结构及其先刻后镀方法
CN112582358A (zh) 一种具有电磁干扰防护的fowlp封装结构的制备方法
CN103441078B (zh) 先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法
CN202196776U (zh) 一种扁平无载体无引线引脚外露封装件
US6940183B1 (en) Compound filled in lead IC packaging product
CN104538378A (zh) 一种圆片级封装结构及其工艺方法
CN104465586B (zh) 一种圆片级封装结构及其工艺方法
CN104600056B (zh) 一种多芯片三维混合封装结构及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant