CN106601882B - A kind of epitaxial wafer and its manufacturing method of light emitting diode - Google Patents
A kind of epitaxial wafer and its manufacturing method of light emitting diode Download PDFInfo
- Publication number
- CN106601882B CN106601882B CN201611039598.0A CN201611039598A CN106601882B CN 106601882 B CN106601882 B CN 106601882B CN 201611039598 A CN201611039598 A CN 201611039598A CN 106601882 B CN106601882 B CN 106601882B
- Authority
- CN
- China
- Prior art keywords
- layer
- sublayer
- improvement
- improves
- sin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a kind of epitaxial wafer of light emitting diode and its manufacturing methods, belong to technical field of semiconductors.The epitaxial wafer includes Sapphire Substrate and stacks gradually buffer layer, nucleating layer, layer of undoped gan, N-type layer, active layer, P-type layer on a sapphire substrate, epitaxial wafer further includes improving layer, improving layer includes alternately stacked SiN layer and GaN layer, improves layer and is arranged between layer of undoped gan and N-type layer or is arranged between N-type layer and active layer.The present invention improves layer by being arranged between layer of undoped gan and N-type layer or between N-type layer and active layer, improving layer includes alternately stacked SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, stress can effectively be discharged, to reduce the defect of active layer, crystal quality is improved, and then improves the Performance And Reliability of epitaxial wafer, improves the backward voltage of chip manufactured by epitaxial wafer.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the epitaxial wafer and its manufacturing method of a kind of light emitting diode.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent is widely used in the technical fields such as indicator light, display screen, illumination.
Epitaxial wafer is the raw material of the chip growth inside LED, generally includes Sapphire Substrate and is sequentially laminated on indigo plant
Buffer layer, layer of undoped gan, N-type GaN layer on jewel substrate, active layer, p-type GaN layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
There are lattice mismatches between GaN and sapphire, and the stress of generation is excessive to lead to defect, stacking of the defect along epitaxial wafer
Direction extends to active layer, even p-type GaN layer, influences the function and reliability of device.
Summary of the invention
In order to solve problems in the prior art, the embodiment of the invention provides a kind of epitaxial wafer of light emitting diode and its systems
Make method.The technical solution is as follows:
In a first aspect, the epitaxial wafer includes blue precious the embodiment of the invention provides a kind of epitaxial wafer of light emitting diode
It is stone lining bottom and the buffer layer being sequentially laminated in the Sapphire Substrate, nucleating layer, layer of undoped gan, N-type layer, active
Layer, P-type layer, the epitaxial wafer further include improving layer, and the improvement layer includes alternately stacked SiN layer and GaN layer, the improvement
Layer is arranged between the layer of undoped gan and the N-type layer or is arranged between the N-type layer and the active layer.
Optionally, the layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement
Layer, it is described first improvement sublayer, it is described second improvement sublayer, the third improve sublayer include alternately stacked SiN layer and
GaN layer, it is described first improve sublayer in SiN layer in Si constituent content be higher than it is described second improve sublayer in SiN layer in Si
Constituent content, it is described second improve sublayer in SiN layer in Si constituent content lower than the third improve sublayer in SiN layer in
Si constituent content.
Preferably, described first improves the SiN in sublayer, in the second improvement sublayer, in third improvement sublayer
The number of plies of layer is three layers or more, and described first improves in sublayer, in the second improvement sublayer, in third improvement sublayer
The number of plies of GaN layer be three layers or more.
Optionally, it is described improve layer with a thickness of 200 angstroms or more.
Second aspect, the embodiment of the invention provides a kind of manufacturing method of the epitaxial wafer of light emitting diode, the manufacture
Method includes:
One Sapphire Substrate is provided；
In the Sapphire Substrate successively grown buffer layer, nucleating layer, layer of undoped gan, improve layer, be N-type layer, active
Layer, P-type layer；
Wherein, the improvement layer includes alternately stacked SiN layer and GaN layer.
Optionally, the layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement
Layer, it is described first improvement sublayer, it is described second improvement sublayer, the third improve sublayer include alternately stacked SiN layer and
GaN layer, it is described first improve sublayer in SiN layer in Si constituent content be higher than it is described second improve sublayer in SiN layer in Si
Constituent content, it is described second improve sublayer in SiN layer in Si constituent content lower than the third improve sublayer in SiN layer in
Si constituent content.
Optionally, the growth temperature for improving layer is 1000 DEG C or more.
The third aspect, the embodiment of the invention provides a kind of manufacturing method of the epitaxial wafer of light emitting diode, the manufacture
Method includes:
One Sapphire Substrate is provided；
In the Sapphire Substrate successively grown buffer layer, nucleating layer, layer of undoped gan, N-type layer, improve layer, active
Layer, P-type layer；
Wherein, the improvement layer includes alternately stacked SiN layer and GaN layer.
Optionally, the layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement
Layer, it is described first improvement sublayer, it is described second improvement sublayer, the third improve sublayer include alternately stacked SiN layer and
GaN layer, it is described first improve sublayer in SiN layer in Si constituent content be higher than it is described second improve sublayer in SiN layer in Si
Constituent content, it is described second improve sublayer in SiN layer in Si constituent content lower than the third improve sublayer in SiN layer in
Si constituent content.
Optionally, the growth temperature for improving layer is 1000 DEG C or more.
Technical solution provided in an embodiment of the present invention has the benefit that
Improve layer by being arranged between layer of undoped gan and N-type layer or between N-type layer and active layer, improves layer
Including alternately stacked SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, can effectively be discharged
Stress improves crystal quality, and then improve the Performance And Reliability of epitaxial wafer, improves extension to reduce the defect of active layer
The backward voltage of chip manufactured by piece.Be formed simultaneously superlattice structure wherein one layer be the pure GaN not adulterated, with extension
The lattice match of this body structure of piece is good, and the setting for improving layer not will cause additional lattice mismatch.And form superlattices knot
Other one layer of structure is SiN layer, and Si constituent content is lower than the SiN positioned at top and bottom in the SiN layer improved among layer
Si constituent content in layer is conducive to current expansion, improves the electron amount of injection active layer, promotes the luminous efficiency of LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of the epitaxial wafer for light emitting diode that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram for the improvement layer that the embodiment of the present invention one provides；
Fig. 3 is a kind of process signal of the manufacturing method of the epitaxial wafer of light emitting diode provided by Embodiment 2 of the present invention
Figure；
Fig. 4 is the structural schematic diagram of the epitaxial wafer for another light emitting diode that the embodiment of the present invention three provides；
Fig. 5 is the process signal of the manufacturing method of the epitaxial wafer for another light emitting diode that the embodiment of the present invention four provides
Figure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
The embodiment of the invention provides a kind of epitaxial wafers of light emitting diode, and referring to Fig. 1, which includes sapphire lining
Bottom 1 and stack gradually buffer layer 2 on a sapphire substrate, nucleating layer 3, layer of undoped gan 4, improve layer 10, N-type layer 5,
Active layer 6, P-type layer 7.
In the present embodiment, referring to fig. 2, improving layer 10 may include alternately stacked SiN layer 10a and GaN layer 10b.
Optionally, improving layer may include that first stacked gradually improves sublayer, the second improvement sublayer, third improvement
Layer, it includes alternately stacked SiN layer and GaN layer that the first improvement sublayer, the second improvement sublayer, third, which improve sublayer, and first changes
Si constituent content is higher than Si constituent content in the SiN layer in the second improvement sublayer in SiN layer in kind sublayer, and second improves sublayer
In SiN layer in Si constituent content lower than third improve sublayer in SiN layer in Si constituent content.
Preferably, first improve in sublayer, second improve in sublayer, third improves the number of plies of the SiN layer in sublayer can be with
It is three layers or more, first number of plies for improving the GaN layer in sublayer, in the second improvement sublayer, in third improvement sublayer can be equal
It is three layers or more.
Optionally, the thickness for improving layer can be 200 angstroms or more, the excessively thin effect that release stress can be not achieved.
Preferably, the thickness for improving layer can be 20~50nm.
Specifically, buffer layer can be the GaN layer of two-dimensional growth, with a thickness of 15~30nm；Nucleating layer can be three-dimensional raw
Long GaN layer, with a thickness of 200~500nm；Layer of undoped gan is the GaN layer of two-dimensional growth, with a thickness of 50~500nm；N-type layer
For the GaN layer of n-type doping, with a thickness of 3~4 μm；Active layer includes alternately stacked InGaN quantum well layer and GaN quantum barrier layer,
With a thickness of 400~500nm；P-type layer is the GaN layer of p-type doping, with a thickness of 50~800nm.
The embodiment of the present invention improves layer by being arranged between layer of undoped gan and N-type layer, and it includes alternately laminated for improving layer
SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, stress can be effectively discharged, to reduce
The defect of active layer improves crystal quality, and then improves the Performance And Reliability of epitaxial wafer, improves chip manufactured by epitaxial wafer
Backward voltage.Be formed simultaneously superlattice structure wherein one layer be the pure GaN not adulterated, the crystalline substance with epitaxial wafer this body structure
Lattice matching degree is good, and the setting for improving layer not will cause additional lattice mismatch.And other one layer for forming superlattice structure is
SiN layer is lower than the Si constituent content in the SiN layer of top and bottom positioned at Si constituent content in the SiN layer improved among layer,
Be conducive to current expansion, improve the electron amount of injection active layer, promote the luminous efficiency of LED.
Embodiment two
The embodiment of the invention provides a kind of manufacturing methods of the epitaxial wafer of light emitting diode, are suitable for manufacture embodiment one
The epitaxial wafer of offer.Using trimethyl gallium or trimethyl second as gallium source when realization, high-purity N H3 is as nitrogen source, trimethyl indium conduct
Indium source, for trimethyl aluminium as silicon source, N type dopant selects silane, and P-type dopant selects two luxuriant magnesium.
Specifically, referring to Fig. 3, which includes:
Step 201: a Sapphire Substrate is provided.
In the concrete realization, can first by Sapphire Substrate metallo-organic compound chemical gaseous phase deposition (English:
Meta1Organic Chemical Vapor Deposition, referred to as: MOCVD) 1060 DEG C are heated in reaction chamber, then in hydrogen
Sapphire Substrate is made annealing treatment in gas atmosphere, is finally carried out nitrogen treatment 10 minutes, to clean substrate surface.
Step 202: grown buffer layer on a sapphire substrate.
Specifically, buffer layer can be the GaN layer of two-dimensional growth, and with a thickness of 15~30nm, growth temperature is 500~650
DEG C, growth pressure is 300~760torr, and V/III ratio is 500~3000.
Wherein, V/III ratio is the molar ratio of V valence atom and III valence atom.
Step 203: growing nucleating layer on the buffer layer.
Specifically, nucleating layer can be the GaN layer of three dimensional growth, with a thickness of 200~500nm, growth temperature is 1000~
1100 DEG C, growth pressure is 400~600torr, and V/III ratio is 300~1000.
Step 204: layer of undoped gan is grown on nucleating layer.
Specifically, layer of undoped gan is the GaN layer of two-dimensional growth, with a thickness of 50~500nm, growth temperature is 1000~
1200 DEG C, growth pressure is 30~500torr, and V/III ratio is 300~3000.
Step 205: growth improves layer in layer of undoped gan.
In the present embodiment, improving layer includes alternately stacked SiN layer and GaN layer.
Optionally, improving layer may include that first stacked gradually improves sublayer, the second improvement sublayer, third improvement
Layer, it includes alternately stacked SiN layer and GaN layer that the first improvement sublayer, the second improvement sublayer, third, which improve sublayer, and first changes
Si constituent content is higher than Si constituent content in the SiN layer in the second improvement sublayer in SiN layer in kind sublayer, and second improves sublayer
In SiN layer in Si constituent content lower than third improve sublayer in SiN layer in Si constituent content.
Preferably, first improve in sublayer, second improve in sublayer, third improves the number of plies of the SiN layer in sublayer can be with
It is three layers or more, first number of plies for improving the GaN layer in sublayer, in the second improvement sublayer, in third improvement sublayer can be equal
It is three layers or more.
Optionally, the thickness for improving layer can be 200 angstroms or more, the excessively thin effect that release stress can be not achieved.
Preferably, the thickness for improving layer can be 20~50nm.
Optionally, the growth temperature for improving layer can be 1000 DEG C or more.Using high growth temperature, improve the crystal quality of layer
It is higher.
Preferably, growth temperature can be 1000~1200 DEG C.
Optionally, growth pressure can be 50~760torr.
Optionally, V/III ratio can be 300~3000.
Step 206: growing N-type layer on improving layer.
Specifically, N-type layer is the GaN layer of n-type doping, and with a thickness of 3~4 μm, growth temperature is 1000~1200 DEG C, growth
Pressure is 50~760torr, and V/III ratio is 300~3000.
Step 207: active layer is grown in N-type layer.
Specifically, active layer includes alternately stacked InGaN quantum well layer and GaN quantum barrier layer, with a thickness of 400~
500nm, growth temperature are 720~820 DEG C, and growth pressure is 200~400torr, and V/III ratio is 300~5000.
Step 208: the growing P-type layer on active layer.
Specifically, P-type layer is the GaN layer of p-type doping, and with a thickness of 50~800nm, growth temperature is 850~1050 DEG C, raw
Long pressure is 100~760torr, and V/III ratio is 1000~20000.
In practical applications, after P-type layer growth is completed, the temperature of reaction chamber is first down to 650~850 DEG C, pure
It is made annealing treatment 5~15 minutes in nitrogen atmosphere；The temperature of reaction chamber is down to room temperature again, terminates the growth of epitaxial wafer；It is finally right
The semiconducter process such as the epitaxial wafer of growth cleaned, deposited, lithography and etching, it is 10* that single size, which is made,
The LED chip of 16mi1.
The embodiment of the present invention improves layer by being arranged between layer of undoped gan and N-type layer, and it includes alternately laminated for improving layer
SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, stress can be effectively discharged, to reduce
The defect of active layer improves crystal quality, and then improves the Performance And Reliability of epitaxial wafer, improves chip manufactured by epitaxial wafer
Backward voltage.Be formed simultaneously superlattice structure wherein one layer be the pure GaN not adulterated, the crystalline substance with epitaxial wafer this body structure
Lattice matching degree is good, and the setting for improving layer not will cause additional lattice mismatch.And other one layer for forming superlattice structure is
SiN layer is lower than the Si constituent content in the SiN layer of top and bottom positioned at Si constituent content in the SiN layer improved among layer,
Be conducive to current expansion, improve the electron amount of injection active layer, promote the luminous efficiency of LED.
Embodiment three
The embodiment of the invention provides a kind of epitaxial wafers of light emitting diode, and referring to fig. 4, which includes sapphire lining
Bottom 1 and stack gradually buffer layer 2 on a sapphire substrate, nucleating layer 3, layer of undoped gan 4, N-type layer 5, improve layer 10,
Active layer 6, P-type layer 7.
In the present embodiment, improving layer can be identical as the improvement layer that embodiment one provides, and this will not be detailed here.
Specifically, Sapphire Substrate can be identical as the Sapphire Substrate that embodiment one provides, and buffer layer can be with implementation
The buffer layer that example one provides is identical, and nucleating layer can be identical as the nucleating layer that embodiment one provides, and layer of undoped gan can be with reality
The layer of undoped gan for applying the offer of example one is identical, and N-type layer can be identical as the N-type layer that embodiment one provides, and active layer can be with reality
The active layer for applying the offer of example one is identical, and P-type layer can be identical as the P-type layer that embodiment one provides, and this will not be detailed here.
The embodiment of the present invention is by the way that in the setting improvement layer between N-type layer and active layer, it includes alternately stacked for improving layer
SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, can effectively discharge stress, so that reducing has
The defect of active layer improves crystal quality, and then improves the Performance And Reliability of epitaxial wafer, improves the anti-of chip manufactured by epitaxial wafer
To voltage.Be formed simultaneously superlattice structure wherein one layer be the pure GaN not adulterated, the lattice with epitaxial wafer this body structure
Matching degree is good, and the setting for improving layer not will cause additional lattice mismatch.And other one layer for forming superlattice structure is SiN
Layer is lower than the Si constituent content in the SiN layer of top and bottom positioned at Si constituent content in the SiN layer improved among layer, has
Conducive to current expansion, the electron amount of injection active layer is improved, the luminous efficiency of LED is promoted.
Example IV
The embodiment of the invention provides a kind of manufacturing methods of the epitaxial wafer of light emitting diode, are suitable for manufacture embodiment three
The epitaxial wafer of offer.Using trimethyl gallium or trimethyl second as gallium source when realization, high-purity N H3 is as nitrogen source, trimethyl indium conduct
Indium source, for trimethyl aluminium as silicon source, N type dopant selects silane, and P-type dopant selects two luxuriant magnesium.
Specifically, referring to Fig. 5, which includes:
Step 401: a Sapphire Substrate is provided.
Optionally, which can be identical as the step 201 that embodiment two provides, and this will not be detailed here.
Step 402: grown buffer layer on a sapphire substrate.
Optionally, which can be identical as the step 202 that embodiment two provides, and this will not be detailed here.
Step 403: growing nucleating layer on the buffer layer.
Optionally, which can be identical as the step 203 that embodiment two provides, and this will not be detailed here.
Step 404: layer of undoped gan is grown on nucleating layer.
Optionally, which can be identical as the step 204 that embodiment two provides, and this will not be detailed here.
Step 405: N-type layer is grown in layer of undoped gan.
Optionally, which can be identical as the step 206 that embodiment two provides, and this will not be detailed here.
Step 406: growth improves layer in N-type layer.
Optionally, which can be identical as the step 205 that embodiment two provides, and this will not be detailed here.
Step 407: growing active layer on improving layer.
Optionally, which can be identical as the step 207 that embodiment two provides, and this will not be detailed here.
Step 408: the growing P-type layer on active layer.
Optionally, which can be identical as the step 208 that embodiment two provides, and this will not be detailed here.
The embodiment of the present invention is by the way that in the setting improvement layer between N-type layer and active layer, it includes alternately stacked for improving layer
SiN layer and GaN layer, alternately stacked SiN layer and GaN layer are superlattice structure, can effectively discharge stress, so that reducing has
The defect of active layer improves crystal quality, and then improves the Performance And Reliability of epitaxial wafer, improves the anti-of chip manufactured by epitaxial wafer
To voltage.Be formed simultaneously superlattice structure wherein one layer be the pure GaN not adulterated, the lattice with epitaxial wafer this body structure
Matching degree is good, and the setting for improving layer not will cause additional lattice mismatch.And other one layer for forming superlattice structure is SiN
Layer is lower than the Si constituent content in the SiN layer of top and bottom positioned at Si constituent content in the SiN layer improved among layer, has
Conducive to current expansion, the electron amount of injection active layer is improved, the luminous efficiency of LED is promoted.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of epitaxial wafer of light emitting diode, the epitaxial wafer includes Sapphire Substrate and is sequentially laminated on described blue precious
Buffer layer, nucleating layer on stone lining bottom, layer of undoped gan, N-type layer, active layer, P-type layer, which is characterized in that the epitaxial wafer
It further include improving layer, the improvement layer includes alternately stacked SiN layer and GaN layer, and the improvement layer is arranged described undoped
Between GaN layer and the N-type layer or it is arranged between the N-type layer and the active layer；
The layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement sublayer, and described first changes
It includes alternately stacked SiN layer and GaN layer that kind sublayer, the second improvement sublayer, the third, which improve sublayer, and described first
Improving Si constituent content in the SiN layer in sublayer and being higher than described second improves Si constituent content in SiN layer in sublayer, and described the
Si constituent content improves Si constituent content in the SiN layer in sublayer lower than the third in SiN layer in two improvement sublayers.
2. epitaxial wafer according to claim 1, which is characterized in that described first improves in sublayer, second improvement is sub
In layer, the number of plies of SiN layer that the third improves in sublayer be three layers or more, described first improve in sublayer, described second
The number of plies for improving the GaN layer in sublayer, in third improvement sublayer is three layers or more.
3. epitaxial wafer according to claim 1 or 2, which is characterized in that it is described improve layer with a thickness of 200 angstroms or more.
4. a kind of manufacturing method of the epitaxial wafer of light emitting diode, which is characterized in that the manufacturing method includes:
One Sapphire Substrate is provided；
In the Sapphire Substrate successively grown buffer layer, nucleating layer, layer of undoped gan, improve layer, N-type layer, active layer, P
Type layer；
Wherein, the improvement layer includes alternately stacked SiN layer and GaN layer；
The layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement sublayer, and described first changes
It includes alternately stacked SiN layer and GaN layer that kind sublayer, the second improvement sublayer, the third, which improve sublayer, and described first
Improving Si constituent content in the SiN layer in sublayer and being higher than described second improves Si constituent content in SiN layer in sublayer, and described the
Si constituent content improves Si constituent content in the SiN layer in sublayer lower than the third in SiN layer in two improvement sublayers.
5. manufacturing method according to claim 4, which is characterized in that it is described improve layer growth temperature be 1000 DEG C with
On.
6. a kind of manufacturing method of the epitaxial wafer of light emitting diode, which is characterized in that the manufacturing method includes:
One Sapphire Substrate is provided；
In the Sapphire Substrate successively grown buffer layer, nucleating layer, layer of undoped gan, N-type layer, improve layer, active layer, P
Type layer；
Wherein, the improvement layer includes alternately stacked SiN layer and GaN layer；
The layer that improves includes that first stacked gradually improves sublayer, the second improvement sublayer, third improvement sublayer, and described first changes
It includes alternately stacked SiN layer and GaN layer that kind sublayer, the second improvement sublayer, the third, which improve sublayer, and described first
Improving Si constituent content in the SiN layer in sublayer and being higher than described second improves Si constituent content in SiN layer in sublayer, and described the
Si constituent content improves Si constituent content in the SiN layer in sublayer lower than the third in SiN layer in two improvement sublayers.
7. manufacturing method according to claim 6, which is characterized in that it is described improve layer growth temperature be 1000 DEG C with
On.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611039598.0A CN106601882B (en) | 2016-11-21 | 2016-11-21 | A kind of epitaxial wafer and its manufacturing method of light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611039598.0A CN106601882B (en) | 2016-11-21 | 2016-11-21 | A kind of epitaxial wafer and its manufacturing method of light emitting diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106601882A CN106601882A (en) | 2017-04-26 |
| CN106601882B true CN106601882B (en) | 2019-02-12 |
Family
ID=58591755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611039598.0A Active CN106601882B (en) | 2016-11-21 | 2016-11-21 | A kind of epitaxial wafer and its manufacturing method of light emitting diode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106601882B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653971B (en) * | 2016-11-26 | 2018-10-12 | 华灿光电（浙江）有限公司 | A kind of epitaxial wafer and its growing method of GaN base light emitting |
| CN106784216B (en) * | 2016-11-26 | 2019-04-12 | 华灿光电（浙江）有限公司 | A kind of epitaxial wafer and its growing method of GaN base light emitting |
| CN107359229A (en) * | 2017-06-30 | 2017-11-17 | 华灿光电(苏州）有限公司 | A kind of LED epitaxial slice and its manufacture method |
| CN109545918B (en) * | 2018-09-27 | 2020-11-27 | 华灿光电（浙江）有限公司 | Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof |
| CN109638114B (en) * | 2018-10-16 | 2020-10-09 | 华灿光电(苏州）有限公司 | Light emitting diode epitaxial wafer and preparation method thereof |
| CN109545926A (en) * | 2018-11-30 | 2019-03-29 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its manufacturing method |
| CN112687773B (en) * | 2020-12-16 | 2022-04-12 | 华灿光电(苏州）有限公司 | Epitaxial wafer of ultraviolet light-emitting diode and preparation method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552186B (en) * | 2014-10-29 | 2019-03-08 | 南通同方半导体有限公司 | One kind, which has, inhibits polarity effect barrier layer blue-ray LED epitaxial structure |
| CN105350074A (en) * | 2015-11-03 | 2016-02-24 | 湘能华磊光电股份有限公司 | Epitaxial growth method for improving LED epitaxial crystal quality |
| CN106252480B (en) * | 2016-08-05 | 2019-08-23 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its growing method |
-
2016
- 2016-11-21 CN CN201611039598.0A patent/CN106601882B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106601882A (en) | 2017-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106601882B (en) | A kind of epitaxial wafer and its manufacturing method of light emitting diode | |
| CN106410005B (en) | A kind of GaN-based LED epitaxial wafer and its growing method | |
| CN106057988B (en) | A kind of preparation method of the epitaxial wafer of GaN base light emitting | |
| CN106653970B (en) | A kind of epitaxial wafer and its growing method of light emitting diode | |
| CN107195737B (en) | A kind of LED epitaxial slice and its manufacturing method | |
| CN102760808B (en) | A kind of epitaxial wafer of light-emitting diode and manufacture method thereof | |
| CN103904177B (en) | LED epitaxial slice and its manufacture method | |
| CN109786529A (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN109860359A (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN109346576A (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN109860358A (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN109216514A (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN105552178B (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN109346583A (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN109192831A (en) | A kind of gallium nitride based LED epitaxial slice and preparation method thereof | |
| CN109103303A (en) | A kind of preparation method and LED epitaxial slice of LED epitaxial slice | |
| CN108717954A (en) | A kind of LED epitaxial slice and its growing method | |
| CN109103312B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109671817A (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN109346568A (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN109192829A (en) | A kind of gallium nitride based LED epitaxial slice and its growing method | |
| CN105870278B (en) | A kind of gallium nitride based light emitting diode and preparation method thereof | |
| CN109192826B (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN106711296B (en) | A kind of epitaxial wafer and its growing method of green light LED | |
| CN107887480B (en) | A kind of preparation method and LED epitaxial slice of LED epitaxial slice |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |