CN106505067A - 互补金属氧化物半导体装置及制造方法 - Google Patents

互补金属氧化物半导体装置及制造方法 Download PDF

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CN106505067A
CN106505067A CN201510564982.1A CN201510564982A CN106505067A CN 106505067 A CN106505067 A CN 106505067A CN 201510564982 A CN201510564982 A CN 201510564982A CN 106505067 A CN106505067 A CN 106505067A
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semiconductor layer
cmos
metal oxide
doping concentration
photoresistance
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CN106505067B (zh
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安生健二
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Abstract

一种互补金属氧化物半导体(CMOS)装置，包括：P型晶体管与N型晶体管，该P型晶体管与N型半导体分别包括源极、漏极及设置于源、漏极之间的半导体层；至少一用于控制该P型晶体管与N型晶体管的栅极。该P型晶体管的半导体层包括具有第一离子掺杂浓度的第一倾角部与具有第二离子掺杂浓度的第一平坦部；该N型晶体管的导体层包括具有第三离子掺杂浓度的第二倾角部、第四离子掺杂浓度的第二平坦部及位于第二倾角部与第二平坦部之间具有第五离子掺杂浓度的第三平坦部；且第一、第二、第四、第三、第五离子掺杂浓度依次增大。

Description

互补金属氧化物半导体装置及制造方法
技术领域
本发明涉及一种互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)装置及一种CMOS装置的制造方法，特别是减少漏电流及改善驼峰现象(Hupnomenon)的CMOS装置及制造方法。
背景技术
CMOS广泛应用于集成电路行业。CMOS装置具有高抗干扰性及低功耗。但由于驼峰现象，为控制CMOS装置栅极电压(Vg)的阈值电压(Vth)，而使半导体层的倾角区域与平坦区域的掺杂离子浓度不同。该半导体层可以是CMOS装置的多晶硅(poly-Si)层。该CMOS装置多晶硅层不同区域的阈值电压不同引起CMOS装置有较高的漏电流从而降低CMOS装置的质量。当CMOS装置越来越小时漏电流问题越严重。
为克服驼峰现象引起的高漏电流问题，在NMOS多晶硅层的倾斜区域需要增加离子掺杂浓度，而在PMOS多晶硅层的倾斜区域的离子掺杂浓度保持不变。为达到此效果需要在CMOS装置的制程中增加一道额外的光罩，而增加的CMOS装置的制造成本。
发明内容
有鉴于此，有必要提供一种可提升削角幅度的显示驱动芯片及显示设备。
一种互补金属氧化物半导体(CMOS)装置，包括：
一P型金属氧化物半导体晶体管，包括：第一源极、第一漏极、及设置于第一源极与第一漏极之间的第一半导体层；
一N型金属氧化物半导体晶体管，包括：第二源极、第二漏极、及设置于第二源极与第二漏极之间的第二半导体层；
至少一用于控制该P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管的栅极；
其中，第一半导体层包括具有第一离子掺杂浓度的第一倾角部与具有第二离子掺杂浓度的第一平坦部；
第二半导体层包括具有第三离子掺杂浓度的第二倾角部、第四离子掺杂浓度的第二平坦部及位于第二倾角部与第二平坦部之间具有第五离子掺杂浓度的第三平坦部；
且第一离子掺杂浓度小于第二离子掺杂浓度，第二离子掺杂浓度小于第四离子掺杂浓度，第四离子掺杂浓度小于第三离子掺杂浓度，第三离子掺杂浓度小于第五离子掺杂浓度。
一种互补金属氧化物半导体(PMOS)的制造方法，包括：
提供一基板，并于基板上形成半导体层，及在半导体层上形成光阻层；
通过一半透光罩照射该光阻层，显影该照射后之光阻层得到第一光阻与第二光阻，且该第二光阻的高度小于该第一光阻的高度；
第一离子植入制程，向该半导体层植入第一离子；
灰化第一、第二光阻消除第一光阻以暴露出该半导体层的第一区域及部份第二光阻以暴露出该半导体层的第二区域；
第二离子植入制程，向该半导体层植入第二离子；
移除剩余第二光阻层暴露出半导体层的被第二区域围绕之第三区域；
通过光刻在半导体层上形成第三光阻与第四光阻，其中该第三光阻在该第三区域的中间部，该第四光阻位于该第二区域与及围绕该第二区域的第四区域；
蚀刻该半导体层以移除未被该第三、第四光阻覆盖之半导体层；
移除第三、第四光阻；
第三离子植入制程形成第一半导体层及与该第一半导体层分离的第二半导体层；
在第一半导体层两侧形成第一源极与第一漏极以形成P型金属氧化物半导体晶体管；及在第二半导体层两侧形成第二源极与第二漏极以形成N型金属氧化物半导体晶体管；及
在该第一、第二半导体层上形成至少一用于控制该P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管之栅极。
相较于现有技术，因为第一、第二、第四、第三、第五离子掺杂浓度依次增大，本发明的互补金属氧化物半导体(CMOS)的P型金属氧化物晶体管单元与N型金属氧化物晶体管单元的驼峰现象可以消除。该N型金属氧化物晶体管单元的半导体层倾角区域的阈值电压增加且该P型金属氧化物晶体管单元的半导体层倾角区域的阈值电压不减小的情况下有效减少漏电流。
附图说明
图1是本发明的CMOS装置一实施方式平面结构示意图。
图2是图1的CMOS装置沿线II-II的剖视图。
图3是图2中部份III的放大示意图。
图4是本发明CMOS装置另一实施方式的剖视图。
图5是本发明CMOS装置制造方法一实施方式流程示意图。
图6是图5所示的制造方法中光刻制程的剖面示意图。
图7是图6所示的光刻制程得到的结构剖面示意图。
图8是图5所示的制造方法中第一离子植入制程的剖面示意图。
图9是图5所示的制造方法中灰化制程剖面示意图。
图10是图5所示的制造方法中第二离子植入制程的剖面示意图。
图11是图5所示的制造方法中光阻移除制程的剖面示意图。
图12是图5所示的制造方法中多晶硅层光刻制程的剖面示意图。
图13是图5所示的制造方法中多晶硅层干蚀刻制程的剖面示意图。
图14是图5所示的制造方法中第三离子植入制程剖面示意图。
主要元件符号说明
互补金属氧化物半导体(CMOS)装置 10
基板 20
P型金属氧化物晶体管单元 100
N型金属氧化物晶体管单元 200
源极 102、202
漏极 104、204
半导体层 106、206
栅极 108、109、110
栅极绝缘层 112
区域 114、116、118、120、122
制造方法 300
多晶硅层 22
光阻层 23
半透光罩 24
不透明区域 241
半透明区域 242
第一透明区域 243
第二透明区域 244
第三透明区域 245
第一光阻 25
第二光阻 26
第三光阻 31
第四光阻 32
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参阅图1，互补金属氧化物半导体(CMOS)装置10包括基板20、P型金属氧化物(P-Channel Metal Oxide Semiconductor, PMOS)晶体管单元100与N型金属氧化物(N-Channel Metal Oxide Semiconductor, NMOS)晶体管单元200。该PMOS晶体管单元100与该NMOS晶体管单元200形成于该基板20上。在本实施方式中，该基板20可以是玻璃基板。该PMOS晶体管单元100包括源极102、漏极104、位于源极102与漏极104之间的半导体层106与门极108。该半导体层106可由多晶硅(poly-Si)植入硼离子形成。该NMOS晶体管单元200包括源极202、漏极204、位于源极202与漏极204之间的半导体层206与门极108。该半导体层206可由多晶硅植入硼离子形成。在本实施方式中，该栅极108为条状形成于源极102、202与漏极104、204之间且垂直于半导体层106、206。通过对该栅极108施加偏置电压控制该PMOS与NMOS晶体管单元100、200。
请参阅图2，该CMOS装置10进一步包括形成于基板20上的栅极绝缘层112，该栅极绝缘层112覆盖该半导体层106、206以使该半导体层112与栅极108相互绝缘。
请求一并参阅图3，在本实施方式中，该半导体层106、206可分为五个区域114、116、118、120与122，其中该半导体层106包括区域114与区域116，该半导体层206包括区域118、区域120与区域122。该区域114为该半导体层106的倾角区域。该区域116为该半导体层106的平坦区域。在本实施例中，该区域116与该区域114相连，且该区域114位于该区域116的边缘。该区域118为该半导体层206的倾角区域。该区域120为该半导体层206平坦区域的周边部。该区域122为该半导体层层206平坦区域的主体部。该些区域114、116、118、120与122的离子掺杂浓度不同。该区域120位于该区域118与该区域122之间，且连通该二区域118与122。在本实施例中，该区域120亦大致呈一平面，为该区域122的周边部分。可变更地，该区域120亦可包括一部分倾斜面。CP/e表示区域114的离子掺杂浓度，CP/f表示区域116的离子掺杂浓度，CN/e表示区域118的离子掺杂浓度，CN/f-1表示区域120的离子掺杂浓度及CN/f-2表示区域122的离子掺杂浓度。该些区域114、116、118、120与122的离子掺杂浓度具有以下关系：CP/e < CP/f < CN/f-2 < CN/e < CN/f-1。在此种设计下，该PMOS晶体管单元100与该NMOS晶体管单元200的驼峰现象可以消除。该NMOS晶体管单元200的半导体层206倾角区域的阈值电压增加且该PMOS晶体管单元100的半导体层106倾角区域的阈值电压不减小的情况下。因此，CMOS装置10可有效减少漏电流。
请参阅图4，图4是本发明CMOS装置的另一实施方式结构示意图，该CMOS装置与图1所示的CMOS装置基本相同，除了两个分离的栅极109、110用于分别控制该PMOS晶体管单元110与NMOS晶体管单元200。
请参阅图5，图5是本发明CMOS装置的制造方法流程图。图5所示的制造方法300仅作为一实施例，有多种方法实施该方法300。该制造方法300可藉助于图1-4及6-13描述，图标中的各组件在该制造方法300进行解释。图5中每一模块代表一个或多个制程步骤。该制造方法300自步骤302开始。
步骤302，请一并参阅图6，提供一包括多晶硅层22的基板20。光阻层23形成于该多晶硅层22上。一半透光罩(half-tone mask)24形成于该光阻层23上。该半透光罩24包括不透明区域241、半透明区域242、第一、第二及第三透明区域243、244、245。该第一、第二及第三透明区域243、244、245与该不透明区域241、该半透明区域242间隔设置。光照通过该半透光罩24施加于该光阻层23，其中与该不透明区域241对应的光阻层23几乎不受光照影响。与半透明区域242对应的的光阻层23接收一半光照水平的光线。与该第一、第二及第三透明区域243、244、245对应的光阻层接收全部光照。
光阻层23显影。请参阅图7，在显影后，光阻层23对应该第一、第二及第三透明区域243、244及245的区域全部被移除。该光阻层23对应不透明区域241的部份形成第一光阻25。该光阻层23对应该透明区域242的部份形成第二光阻26。该第一光阻24比该第二光阻26大。该第一光阻25的高度基本为该第二光阻26的两倍。
步骤304，请参阅图8，在多晶硅层22未被第一光阻25与第二光阻26覆盖的区域27植入硼离子B+执行第一离子植入制程。该硼离子B+以第一浓度植入。
步骤306，请参阅图9，利用氧气(O2)灰化该第一光阻25、第二光阻26及多晶硅层22。通过灰化制程，该第二光阻26基本被移除暴露出该多晶硅层22的一个区域28。该第一光阻25部份被移除暴露出该多晶硅层22的区域28。
步骤308，请参阅图10，在多晶硅层22植入硼离子B+执行第二离子植入制程。其中，该区域27的离子浓度由第一离子浓度增加到第二离子浓度。该多晶硅层22新暴露区域28的离子浓度为比第二离子浓度小的第三离子浓度。
步骤310，请参阅图11，移除剩余的第一光阻层暴露出该多晶硅层22的区域29。该区域29不包括硼离子。
步骤312，请参阅图12，执行光刻制程，在该区域29上形成第三光阻31，在该区域29上形成第四光阻32。该第三、第四光阻31、32通过在该多晶硅层22上涂布一光阻层然后通过一全透光罩照射最后显影形成。该第三光阻31未全部覆盖该区域29以暴露该区域29的周边区域。该第四光阻32全部覆盖该区域28及该区域27中与该区域28相邻的部份。
步骤314，请参阅图13，干蚀刻该多晶硅层22以移除该第三、第四光阻31、32未覆盖的区域。
步骤316，移除第三、第四光阻31、32暴露出该多晶硅层22。
步骤318，请参阅图14，在移除该第三、第四光阻31、32后进行第三离子植入制程。硼离子B+被植入剩余多晶硅层22的区域29、28及27中。在第三离子植入后，请再次参阅图2，该区域29形成该PMOS晶体管单元100的第一半导体层106，该区域28及相邻区域27共同形成该NMOS晶体管单元200的第二半导体层206。在第三离子植入制程中，该区域29、27的平坦部及区域28的离子浓度大于该区域29、27的倾角部。因此，该CMOS装置的第一、第二半导体层106、206的该些区域114、116、118、120、122离子浓度具有以下关系：CP/e < CP/f < CN/f-2 < CN/e < CN/f-1.
请再次参阅图1，在步骤318后，该源极102、漏极202、该栅极绝缘层112及该栅极108(或图4中的栅极109、110)以形成具有PMOS晶体管单元100与NMOS晶体管单元200的该CMOS装置10。
以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。

Claims (10)

1.一种互补金属氧化物半导体(CMOS)装置，包括：
一P型金属氧化物半导体晶体管，包括：第一源极、第一漏极、及设置于第一源极与第一漏极之间的第一半导体层；
一N型金属氧化物半导体晶体管，包括：第二源极、第二漏极、及设置于第二源极与第二漏极之间的第二半导体层；
至少一用于控制该P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管的栅极；
其特征在于，第一半导体层包括具有第一离子掺杂浓度的第一倾角部与具有第二离子掺杂浓度的第一平坦部；
第二半导体层包括具有第三离子掺杂浓度的第二倾角部、第四离子掺杂浓度的第二平坦部及位于第二倾角部与第二平坦部之间具有第五离子掺杂浓度的第三平坦部；
且第一离子掺杂浓度小于第二离子掺杂浓度，第二离子掺杂浓度小于第四离子掺杂浓度，第四离子掺杂浓度小于第三离子掺杂浓度，第三离子掺杂浓度小于第五离子掺杂浓度。
2.如权利要求1所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该至少一栅极位于该第一、第二源极与第一、第二漏极之间，且沿与该第一、第二半导体层垂直延伸。
3.如权利要求2所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该至少一栅极仅为单栅极，该单栅极为沿第一、第二半导体层延伸的条状。
4.如权利要求3所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该第一、第二半导体层由多晶硅掺杂硼离子制成。
5.如权利要求4所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该互补金属氧化物半导体进一步包括设置于第一、第二半导体层与该单栅极之间的栅极绝缘层。
6.如权利要求2所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该至少一栅极包括二栅极，一栅极用于控制P型金属氧化物半导体晶体管，另一栅极用于控制N型金属氧化物半导体晶体管。
7.如权利要求6所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该第一、第二半导体层由多晶硅掺杂硼离子制成。
8.如权利要求7所述的互补金属氧化物半导体(CMOS)装置，其特征在于，该互补金属氧化物半导体进一步包括设置于第一、第二半导体层与该二栅极之间的栅极绝缘层。
9.一种互补金属氧化物半导体(CMOS)的制造方法，包括：
提供一基板，并于基板上形成半导体层，及在半导体层上形成光阻层；
通过一半透光罩照射该光阻层，显影该照射后之光阻层得到第一光阻与第二光阻，且该第二光阻的高度小于该第一光阻的高度；
第一离子植入制程，向该半导体层植入第一离子；
灰化第一、第二光阻消除第一光阻以暴露出该半导体层的第一区域及部份第二光阻以暴露出该半导体层的第二区域；
第二离子植入制程，向该半导体层植入第二离子；
移除剩余第二光阻层暴露出半导体层的被第二区域围绕之第三区域；
通过光刻在半导体层上形成第三光阻与第四光阻，其特征在于该第三光阻在该第三区域的中间部，该第四光阻位于该第二区域与及围绕该第二区域的第四区域；
蚀刻该半导体层以移除未被该第三、第四光阻覆盖之半导体层；
移除第三、第四光阻；
第三离子植入制程形成第一半导体层及与该第一半导体层分离的第二半导体层；
在第一半导体层两侧形成第一源极与第一漏极以形成P型金属氧化物半导体晶体管；及在第二半导体层两侧形成第二源极与第二漏极以形成N型金属氧化物半导体晶体管；及
在该第一、第二半导体层上形成至少一用于控制该P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管之栅极。
10.如权利要求9所述的互补金属氧化物半导体(CMOS)的制造方法，其特征在于，该互补金属氧化物半导体(CMOS)的制造方法还包括在该至少一栅极与第一、第二半导体层之间形成栅极绝缘层。
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