CN106489202A - 具有高效率散热路径的堆叠式半导体裸片组合件及相关联系统 - Google Patents
具有高效率散热路径的堆叠式半导体裸片组合件及相关联系统 Download PDFInfo
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- CN106489202A CN106489202A CN201580037672.2A CN201580037672A CN106489202A CN 106489202 A CN106489202 A CN 106489202A CN 201580037672 A CN201580037672 A CN 201580037672A CN 106489202 A CN106489202 A CN 106489202A
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Abstract
本发明涉及具有高效率散热路径的半导体裸片组合件。在一个实施例中,半导体裸片组合件包括封装支撑衬底、电安装到所述封装支撑衬底的第一半导体裸片,及多个第二半导体裸片。所述第一裸片具有堆叠位区及从所述堆叠位区横向延伸的外围区域,且底部第二半导体裸片附接到所述第一裸片的所述堆叠位区。所述组合件进一步包含(a)附接到所述第一裸片的所述外围区域的热传递结构,所述热传递结构具有其中定位有所述第二裸片的腔,及入口,及(b)所述腔中的底部填充材料。所述底部填充材料具有在所述第二半导体裸片之间通过将所述底部填充材料通过壳体的入口端口注入到所述腔中造成的填角料。
Description
技术领域
所揭示实施例涉及半导体裸片组合件。特定地说,本技术涉及具有高效率散热路径的堆叠式半导体裸片组合件及相关联的系统及方法。
背景技术
包含存储器芯片、微处理器芯片及成像器芯片的封装式半导体裸片通常包含安装在衬底上且被包纳在塑料保护罩中的半导体裸片。裸片包含功能特征,例如存储器单元、处理器电路及成像器装置,以及电连接到功能特征的接合垫。接合垫可电连接到保护罩外部的端子以允许裸片连接到较高层级电路。
市场压力不断驱使半导体制造商减小裸片封装的大小以装配在电子装置的空间约束内,同时还施压于其以增加每一封装的功能容量以满足操作参数。用于增加半导体封装的处理能力而不基本上增加由封装覆盖的表面积(即,封装的“占据面积”)的一种方法是在单个封装中将多个半导体裸片垂直堆叠在彼此的顶部上。此类垂直堆叠式封装中的裸片可通过使用穿硅通孔(TSV)电耦合个别裸片的接合垫与相邻裸片的接合垫而互连。
与垂直堆叠式裸片封装相关联的挑战在于来自个别裸片的热量是加成性的且难以耗散由堆叠式裸片产生的汇总热量。总之,此增加个别裸片、裸片之间的结及封装的操作温度,这可造成堆叠式裸片达到高于其最大操作温度(Tmax)的温度。问题还由于封装中的裸片的密度增加而恶化。此外,当装置在裸片堆叠中具有不同类型的裸片时,装置的最大操作温度被限制于具有最低的最大操作温度的裸片。
附图说明
图1是说明根据本技术的实施例的半导体裸片组合件的横截面图。
图2A是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图,且图2B是说明所述方法的俯视平面图。
图2C是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图,且图2D是说明所述方法的俯视平面图。
图2E及2F是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图。
图3是说明根据本技术的实施例的半导体裸片组合件的横截面图。
图4A是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图,且图4B是说明所述方法的俯视平面图。
图4C是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图。
图4D是说明根据本技术的实施例的制造半导体裸片组合件的方法的横截面图,且图4E是说明所述方法的俯视平面图。
图5A是根据本技术的实施例的半导体裸片组合件的横截面图且图5B是所述半导体裸片组合件的俯视平面图。
图6是根据本技术的实施例的半导体裸片组合件的横截面图。
图7是根据本技术的实施例的半导体裸片组合件的横截面图。
图8是根据本技术的实施例的半导体裸片组合件的横截面图。
图9是根据本技术的实施例的半导体裸片组合件的横截面图。
图10是包含根据本技术的实施例配置的半导体裸片组合件的系统的示意图。
具体实施方式
下文描述具有高效率散热路径的堆叠式半导体裸片组合件及相关联的系统及方法的若干实施例的具体细节。术语“半导体裸片”通常是指具有集成电路或组件、数据存储元件、处理组件及/或制造在半导体衬底上的其它特征的裸片。例如,半导体裸片可包含集成电路存储器及/或逻辑电路。半导体裸片及/或半导体裸片封装中的其它特征可被视为彼此“热接触”,前提是所述两种结构可经由例如传导、对流及/或辐射通过热量交换能量。所属领域技术人员还将了解,本技术可具有额外实施例,且本技术可在无下文参考图1到10描述的实施例的若干细节的情况下实践。
如本文中使用,鉴于图中所示的定向,术语“垂直”、“横向”、“上部”及“下部”可指代半导体裸片组合件中的特征的相对方向或位置。例如,“上部”或“最上面”可指代经定位成比另一特征更接近页面的顶部的特征。然而,这些术语应被广义地解释为包含具有其它定向(例如颠倒或倾斜定向,其中顶部/底部、上方/下方、以上/以下、上/下及左/右取决于定向可互换)的半导体装置。
图1是说明根据本技术的实施例的半导体裸片组合件100(“组合件100”)的横截面图。组合件100可包含封装支撑衬底102、安装到封装支撑衬底102的第一半导体裸片110,及在堆叠区域(例如第一裸片110的中心区域或偏心区域)处布置在堆叠122中的多个第二半导体裸片120。第一裸片110可进一步包含在第二裸片120的外侧横向的外围区域112及热传递结构(TTS)130,热传递结构130具有由粘合剂133附接到第一裸片110的外围区域112的第一部分131及覆盖、围封或以其它方式在第二裸片120的堆叠122上方的第二部分132。例如,粘合剂133可为散热界面材料(“TIM”)或另一适当粘合剂。例如,TIM及其它粘合剂可包含硅酮基油脂、凝胶或掺杂有导电材料(例如,碳纳米管、焊锡材料、类金刚石碳(DLC)等等)的粘合剂,以及相变材料。在图1中说明的实施例中,第一部分131是至少从第一裸片110的外围区域112延伸到第二裸片120的堆叠122的中间高度处的高度的底座,例如屏障部件。第二部分132是由粘合剂133附接到第一部分131及最上面第二裸片120的罩。第一部分131及第二部分132可一起界定由金属(例如,铜或铝)或其它高热传导材料制成的壳体,且第一部分131及第二部分132可一起界定其中定位有第二裸片120的堆叠122的腔138。
组合件100进一步包含第二裸片120中的每一者之间及第一裸片110与底部第二裸片120之间的底部填充材料160。底部填充材料160可在靠近第一裸片110的区域中形成从第二裸片120的堆叠122向外延伸的填角料162。组合件100预期提供来自第一裸片110及第二裸片120的堆叠122的热量的增强热耗散。例如,TTS 130可由具有高热传导率的材料制成以沿直接从第一裸片110的外围区域112的大部分的第一路径且沿穿过第二裸片120的第二路径有效地传递热量。TTS 130的第一部分131附接到第一裸片110的外围区域112的可用区域的大的百分比,因为第一部分131提供屏障,所述屏障防止底部填充材料160的填角料162覆盖外围区域112的相当大的百分比。这增强了第一热路径的效率,因为与其中在第一部分131附接到第一裸片110的外围区域112之前沉积底部填充材料的装置相比,TTS 130的第一部分131可覆盖外围区域112的更多表面区域。
图1中所示的组合件100的若干实施例可因此提供增强的散热性质,其降低组合件100中的个别裸片110、120的操作温度使得所述裸片保持在其指定最大温度(Tmax)以下。当组合件100被布置为混合存储器立方体(HMC)时此可极为有用,因为第一裸片110通常是较大衬底逻辑裸片,且第二裸片120通常是存储器裸片,且逻辑裸片通常是以远高于存储器裸片的功率等级操作(例如,与0.628W相比的5.24W)。逻辑裸片HMC配置通常将大量热量集中在第一裸片110的外围区域112处。逻辑裸片还可在外围区域处具有较大功率密度,从而造成外围区域处进一步集中热量且温度较高。因而,通过将第一裸片110的外围区域112的较大百分比耦合到TTS 130的高度传导第一部分131,热量可被有效地从第一裸片的外围区域112消除。
图2A到2F说明根据本技术的实施例的制造组合件100的方法的方面。图2A是制造组合件100的阶段的横截面图且图2B是所述阶段的俯视平面图。参考图2A,封装支撑衬底102经配置以将第一裸片110及第二裸片120连接到较高层级封装(未展示)的外部电组件。例如,封装支撑衬底102可为插入物或印刷电路板,其包含半导体组件(例如,经掺杂硅晶片或砷化镓晶片)、不导电组件(例如,各种陶瓷衬底,例如氧化铝(Al2O3)、氮化铝(AlN)等等),及/或导电部分(例如,互连电路、TSV等等)。在图2A中说明的实施例中,封装支撑衬底102在封装支撑衬底102的第一侧103a处经由第一多个电连接器104a电耦合到第一裸片110,且在封装支撑衬底102的第二侧103b处经由第二多个电连接器104b电耦合到外部电路(未展示)(电连接器104a及电连接器104b统称为“电连接器104”)。电连接器104可为焊球、导电凸块及支柱、导电环氧树脂,及/或其它适当的导电元件。在各个实施例中,封装支撑衬底102可由具有相对较高热传导率的材料制成以增强第一半导体裸片110的背侧处的热耗散。
如图2A及2B中所示,第一裸片110可具有大于堆叠式第二裸片120的占据面积。第一裸片110因此包含安装区域111(图2A)或堆叠区域,在堆叠区域中,第二裸片120附接到第一裸片110且外围区域112向外横向延伸超出安装区域111的至少一侧。外围区域112因此是在第二裸片120外侧(例如,超出第二裸片120的长度及/或宽度)。
第一裸片110及第二裸片120可包含各种类型的半导体组件及功能特征,例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件,及/或其它半导体特征。在各个实施例中,例如,组合件100可被配置为HMC,其中堆叠式第二裸片120是DRAM裸片或提供数据存储的其它存储器裸片,且第一裸片110是提供HMC内的存储器控制(例如DRAM控制)的高速逻辑裸片。在其它实施例中,第一裸片110及第二裸片120可包含其它半导体组件,及/或堆叠122中的个别第二裸片120的半导体组件可不同。
第一裸片110及第二裸片120可为矩形、圆形及/或其它适当形状,且可具有各种不同尺寸。例如,个别第二裸片120可各自具有大约10mm到11mm(例如,10.7mm)的长度L1及大约8mm到9mm(例如,8.6mm、8.7mm)的宽度。第一裸片110可具有大约12mm到13mm(例如,12.67mm)的长度L2及大约8mm到9mm(例如,8.5mm、8.6mm等等)的宽度。在其它实施例中,第一裸片110及第二裸片120可具有其它适当尺寸,及/或个别第二裸片120可具有彼此不同的尺寸。
第一裸片110的外围区域112(被所属领域技术人员称为“门廊”或“搁板”)可由第一裸片110及第二裸片120的相对尺寸及第一裸片110的前向表面114上的堆叠122的位置来界定。在图2A及2B中说明的实施例中,堆叠122相对于第一裸片110的长度L2居中,使得外围区域112横向地延伸超出堆叠122的两个相对侧。例如,如果第一裸片110的长度L2比第二裸片120的长度L1大大约1.0mm,那么外围区域112将延伸超出居中第二裸片120的任一侧大约0.5mm。堆叠122还可相对于第一裸片110的宽度居中,且在其中第一裸片110的宽度及长度两者均大于居中堆叠122的实施例中,外围区域112可围绕第二裸片120的整个周长延伸。在其它实施例中,堆叠122可相对于第一裸片110的前向表面114(图2A)偏移,及/或第一裸片110的外围区域112可围绕堆叠122的全周长的一部分延伸。在进一步实施例中,第一裸片110及第二裸片120可为圆形,且因此第一裸片110及第二裸片120的相对直径界定外围区域112。
如图2A中所示,第二裸片120可在堆叠122中彼此电耦合,且由定位在相邻裸片110、120之间的多个导电元件124电耦合到下伏第一裸片110。虽然图1中所示的堆叠122包含电耦合在一起的8个第二裸片120,但是在其它实施例中,堆叠122可包含多于或少于8个的裸片(例如,2到4个裸片,或至少9个裸片等等)。导电元件124可具有各种适当结构,例如支柱、柱、支杆、凸块,且可由铜、镍、焊锡(例如,基于SnAg的焊锡)、填充导体的环氧树脂及/或其它导电材料制成。在选定实施例中,例如,导电元件124可为铜柱,而在其它实施例中,导电元件124可包含更复杂的结构,例如氮化物上凸块(bump-on-nitride)结构。
如图2A中进一步所示,个别第二裸片120可各自包含多个TSV 126,其在一或两侧上与对应导电元件124对准以在第二裸片120的相对侧处提供电连接。每一TSV 126可包含完全行进穿过个别第二裸片120的导电材料(例如,铜)及电绝缘材料,所述电绝缘材料包围导电材料以电隔离TSV 126与第二裸片120的剩余部分。虽然图1中未展示,但是第一裸片110还可包含将第一裸片110电耦合到较高层级电路的多个TSV 126。在电通信之外,TSV126及导电元件124提供散热导管,热量可通过散热导管被传递远离第一裸片110及第二裸片120(例如,通过第一散热路径)。在一些实施例中,导电元件124及/或TSV 126的尺寸可增加以增强垂直通过堆叠122的热传递。例如,个别导电元件124可各自具有大约15μm到30μm的直径或其它适当尺寸以增强穿过裸片110、120的散热通路。在其它实施例中,第二裸片120可彼此电耦合且使用还可提供穿过堆叠122的散热通路的其它类型的电连接器(例如导线接合)电耦合到第一裸片110。
在各个实施例中,组合件100还可包含填隙地定位在导电元件124之间的多个热传导元件128(以虚线展示)。个别热传导元件128在结构及成分方面可至少通常类似于导电元件124(例如铜柱)。然而,热传导元件128并未电耦合到TSV 126或裸片110及120的其它电活性组件,且因此不提供第二裸片120之间的电连接。相反地,热传导元件128是电隔离“哑元件”,其增加通过堆叠122的整体热传导率以增强沿第一散热路径的热传递。例如,在其中组合件100被布置为HMC的实施例中,导电元件124之间添加热传导元件128已被示为将HMC的操作温度降低若干度(例如大约6℃到7℃)。
图2C是说明用于制造组合件100的方法在将TTS 130(图1)的第一部分131附接到第一裸片110及封装支撑衬底102之后的后续阶段的横截面图,且图2D是说明所述后续阶段的俯视平面图。参考图2C,第一部分131的此实施例具有经配置以围绕第一裸片110的至少一部分延伸的基座142(例如,基脚)及经配置以定位在第一裸片110的外围区域112上方的凸肩144。第一部分131可进一步包含延伸到相对于第二裸片120的堆叠122的高度(H1)的侧壁146。侧壁146还通过间隙(G)与第二裸片120的堆叠122分隔开,使得凸肩144覆盖外围区域112的相当大的百分比(例如,覆盖面积(C))。基座142可由粘合剂148附接到封装支撑衬底102,且凸肩144可由热传导粘合剂133附接到第一裸片110的外围区域112。粘合剂133及148可为相同粘合剂,或其可彼此不同。粘合剂133例如可为TIM。如图2D中所示,第一部分131可为包围第一裸片110及第二裸片120的环。
图2E是说明制造组合件100的方法在第二裸片120之间及第一裸片110与底部第二裸片120之间沉积底部填充材料160之后的另一阶段的横截面图。底部填充材料160通常是可流动材料,其填充第二裸片120、导电元件124及热传导元件128之间的填隙空间。TTS130的第一部分131提供屏障部件,其抑制填角料162覆盖第一裸片110的外围区域112的程度。例如,填角料162沿侧壁146的部分向上延伸,而非如同在沉积底部填充材料160之后将热传导部件附接到外围区域112的其它装置中一样,填角料162在外围区域112上方横向地展开。底部填充材料160可为不导电环氧树脂糊状物(例如由日本新泻市的纳美仕公司(NamicsCorporation)制造的XS8448-171)、毛细管底部填充物、不导电膜、模制底部填充物及/或包含其它适当的电绝缘材料。底部填充材料160可替代地为电介质底部填充物,例如由德国杜塞尔多夫的汉高公司(Henkel)制造的FP4585。在一些实施例中,底部填充材料160可基于其热传导率选择以增强通过堆叠122的热耗散。底部填充材料160的量经选择以充分填充填隙空间使得底部填充材料160的过量部分进入第一部分131的侧壁146与第二裸片120的堆叠122之间之间隙(G)中而形成填角料162。高度(H1)、间隙(G)及覆盖面积(C)经选择以提供外围区域112的大的覆盖面积(C),同时还提供侧壁146与第二裸片120的堆叠122之间的足够空间以容纳底部填充材料160的填角料162。
图2F是说明TTS 130的第二部分132已附接到第一部分131以完成TTS 130之后图1的组合件100的横截面图。第二部分132可具有由粘合剂133附接到最上面第二裸片120的顶部152、由粘合剂133附接到第一部分131的底部154,及从顶部152下垂的侧壁156。第一部分131及第二部分132一起界定包纳第二裸片120的堆叠122的腔138。图2F中说明的实施例的TTS 130因此是热传导壳体,其提供增强的热传递以消除由第一裸片110及第二裸片120产生的热量。TTS 130的第一部分131及第二部分132中的每一者可由金属(例如铜或铝)制成,使得TTS 130具有金属底座部分及金属罩。
图3是根据本技术的组合件100的另一实施例的横截面图。在此实施例中,TTS 130的第一部分131具有具备延伸到至少与最上面第二裸片120的顶部近似相同的高度的高度(H2)的侧壁146,且TTS 130的第二部分132具有附接到侧壁146的顶部的底部154。第二部分132因此不具有从顶部152下垂的单独侧壁。第二部分132可由粘合剂133附接到第一部分131。
图4A是在根据本技术的制造过程的一个阶段处的半导体裸片组合件400的侧视横截面图,且图4B是所述半导体裸片组合件400的俯视平面图。组合件400的若干特征类似于上文关于组合件100描述的特征,且因此相似参考数字是指图1到4B中的相似组件。图4A展示内部壳体430附接到第一裸片110之后的组合件400。内部壳体430可包含具有第一内表面433的第一支撑件431、具有第二内表面434的第二支撑件432,及在第一支撑件431与第二支撑件432之间延伸的顶部435。内部壳体430具有腔436,其用第一支撑件431及第二支撑件432封闭在侧边上,但是在另外两侧上敞开。第一支撑件431及第二支撑件432可用粘合剂133附接到第一裸片110的外围区域112。内部壳体430的顶部435还可由粘合剂133附接到第二裸片120的顶部。如图4B中所示,内部壳体430可具有类似于第一裸片110的占据面积的占据面积。
图4C是在底部填充材料160已沉积在第二裸片120之间及第一裸片110与底部第二裸片120之间之后的后续制造阶段处的组合件400的侧视横截面图。返回参考图4B,底部填充材料可通过如箭头F所示那样将底部填充材料流过内部壳体430的敞开侧而分布在填隙空间内。为增强底部填充材料的流动,组合件400可倾斜成某个角度使得重力将底部填充材料160拖曳通过腔436内的填隙空间。
图4D是后续制造阶段处的组合件400的侧视横截面图,且图4E是所述组合件400的俯视平面图。参考图4D,组合件400进一步包含外部壳体440,其具有具备内表面444的侧壁442及与所述侧壁442一起界定腔448的顶部446。如图4E中所示,侧壁442的内表面444具有四个侧面,使得腔448围封第一裸片110、第二裸片120的堆叠及内部壳体430。如图4D中所示,外部壳体440可由粘合剂148附接到封装支撑衬底102且由粘合剂133附接到内部壳体430的顶部435。此实施例提供与如上文解释的第一裸片110的外围区域112且与第二裸片120的侧的良好的散热界面,因为底部填充材料160可具有高于壳体内的空隙的热传导率。
图5A是根据本技术的另一实施例的半导体装置组合件500(“组合件500”)的横截面图,且图5B是所述半导体装置组合件500的俯视平面图。相似参考数字是指遍及1到5B的相似组件。组合件500包含TTS 530,其具有顶部532、与顶部532一体式形成的侧壁534,及由顶部532及侧壁534界定的腔538。TTS 530是由具有高热传导率的材料(例如铜或铝)形成的单件式壳体。侧壁534可具有内表面535。在如图5B中所示的一个实施例中,内表面535可具有四个侧面,其经配置以与第二裸片120的堆叠122分隔开使得第二裸片120与侧壁534的内表面535之间存在小间隙。返回参考图5A,侧壁534可进一步包含由粘合剂148附接到封装支撑衬底102的基座536及由粘合剂133附接到第一裸片110的外围区域112的凸肩537。基座536可为具有从第一裸片110的外围区域112向外横向地分开的内表面539的基脚。TTS 530可进一步包含入口540a及出口540b。入口540a可为延伸穿过侧壁534的下部部分的第一通道,且出口540b可为延伸穿过侧壁534的上部部分的第二通道。参考图5B,入口540a及出口540b可彼此横向地偏移,或在其它实施例中其可跨腔538彼此对准。在其它实施例中,入口540a及出口540b可以近似相同高度延伸穿过侧壁。在又其它实施例中,入口540a沿侧壁534定位的高度可相对大于出口540b沿侧壁534定位的高度。
底部填充材料160经由入口540a注入(I)到腔538中,使得底部填充材料160填充第二裸片120之间及第一裸片与底部第二裸片120之间的填隙空间。在一个实施例中,底部填充材料160可被注入到腔538中直到底部填充材料160流出出口540b为止(O)。入口540a及出口540b可通过用底部填充材料160填充这些通道来密封,或在其它实施例中,入口540a及出口540b的外部开口可用另一材料加盖以将腔538密封在TTS 530内。因此,TTS 530提供屏障部件,其有效地含有底部填充材料160,同时还由侧壁534的凸肩537提供第一裸片110的外围区域112的大的表面积的覆盖。此外,底部填充材料160还接触第二裸片120的侧,以还增强横向地远离第二裸片120的热传递。
图6是根据本技术的另一实施例的半导体裸片组合件600(“组合件600”)的横截面图。相似参考数字是指图1到6中的相似组件。组合件600可包含TTS 630,其具有顶部632及具有内表面636的侧壁634。顶部632及侧壁634界定经配置以接纳第一裸片110及第二裸片120的堆叠122的腔638。顶部632可由粘合剂133附接到上部第二裸片120,且侧壁634可由粘合剂148附接到封装支撑衬底102。图6中所示的侧壁634的实施例不接触第一裸片110的外围区域112。在其它实施例中,侧壁634可具有粘附到第一裸片110的外围区域112的凸肩,及粘附到封装支撑衬底102的基座,如由图5A中所示的侧壁534的凸肩537及基座536所示。TTS630可进一步包括入口640a及出口640b。在经说明的实施例中,入口640a及出口640b是延伸穿过TTS 630的顶部632的通道。在其它实施例中,入口640a及/或出口640b可为穿过侧壁634的通道。此外,图6中说明的TTS 630的实施例是其中顶部632与侧壁634一体式形成的单件式壳体。在其它实施例中,顶部632可为由粘合剂附接到侧壁634的单独组件,例如上文关于图3展示并描述。
组合件600进一步包含腔638中的热传导电介质液体670。电介质液体670可经由入口640a注入到腔638中(I)。出口640b可因此提供通风孔,空气或其它物质随着注入电介质液体670而可通过所述通风孔从腔638逸出(O)。电介质液体670可作为液体注入且在腔638内保留为液体状态,或其可作为液体注入且部分固化为凝胶状物质或完全固化为固体。适当的热传导电介质液体670包含例如石蜡流体及由陶氏化学公司(Dow Chemical Company)制造的DowthermTM。适当的DowthermTM热传递流体包含Dowtherm ATM、Dowtherm GTM、Dowtherm QTM及Dowtherm TTM,其全部是由陶氏化学公司制造。电介质液体670应具有大于组合件600的最大操作温度的沸点以避免在腔中产生气体。在一些实施例中,电介质液体670可经选择以在周围温度下固化为固态或半固态材料,但是在最大操作温度下或附近经历到液体状态的相变以潜在地增强热传递并当达到最大操作温度时提供稳定状态操作温度。
电介质液体670可填充第二裸片120之间及第一裸片110与底部第二裸片120之间的填隙空间,使得不一定需要单独底部填充材料。在其它实施例中,在用电介质液体670填充腔638之前,底部填充材料可沉积在第二裸片120之间及第一裸片110与底部第二裸片120之间。当电介质液体670保持为液体状态时底部填充材料通常是需要的,以提供对裸片110、120的结构支撑。然而,当电介质液体670固化为充分固态时,可消除底部填充材料。
在操作中,电介质液体670不仅接触第一裸片110的外围区域112,而且接触第二裸片120以有效地传递热量到TTS 630。与使用底部填充材料及/或在壳体与裸片110及120之间具有空隙的装置相比,此在具有高热传导率的材料与裸片110及120之间提供显著更多表面接触。在一些实施例中,腔638经完全填充以防止TTS 630出现空隙,且入口640a及出口640b经加盖以密封腔638。组合件600的实施例预期提供从第一裸片110及第二裸片120的高效率的热量传递。
图7是根据本技术的组合件600的另一实施例的横截面图。在此实施例中,入口640a是延伸穿过侧壁634的下部部分的通道,且出口640b是延伸穿过顶部632的通道。此实施例提供腔638的从下而上的填充,这预期可减少腔638内气穴的可能形成。
图8是根据本技术的组合件600的另一实施例的横截面图。在此实施例中,TTS 630是具有由粘合剂133彼此附接的顶部组件632及单独侧壁634的多件式壳体。侧壁634可由粘合剂148附接到封装支撑衬底102,且接着可用电介质液体670填充侧壁634的内表面636与裸片110及120之间的空间。顶部632接着由粘合剂133附接到侧壁634及上部第二裸片120。在许多实施例中,腔638将具有由粘合剂133的厚度引起的小的空隙。为避免腔638内具有可膨胀气体,TTS 630的顶部632可在真空中附接到侧壁634。
图9是根据本技术的另一实施例的半导体裸片组合件900(“组合件900”)的横截面图。图9中说明的实施例类似于图2F中说明的组合件100的实施例,且因此相似参考数字是指图1到9中的相似组件。在组合件900中,TTS 130可进一步包含TTS 130的第二部分132中的入口910a及出口910b。入口910a及出口910b是暴露于TTS 130内的腔138的通道。组合件900进一步包含腔138中的底部填充材料160及电介质液体670两者。底部填充材料160可如上文参考图2E描述那样沉积。电介质液体670可经由入口910a注入到腔中,且空气或过量的电介质液体670可经由出口910b从腔138中传出。在腔138已用电介质液体670填充之后,入口910a及出口910b可经加盖或以其它方式密封以密封腔138使其与外部环境隔离。
上文参考图1到9描述的堆叠式半导体裸片组合件中的任一者可并入到大量较大系统及/或更复杂系统中的任一者中,所述系统的代表性实例是图10中示意地展示的系统1000。系统1000可包含半导体裸片组合件1010、电源1020、驱动器1030、处理器1040及/或其它子系统或组件1050。半导体裸片组合件1010可包含通常类似于上文描述的堆叠式半导体裸片组合件的特征的特征,且可因此包含具有可良好覆盖第一裸片110的外围区域112且增强热耗散的多个散热路径。所得系统1000可执行多种功能中的任一者,例如存储器存储、数据处理及/或其它适当功能。因此,代表性系统1000可包含但不限于手持式装置(例如,移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及电器。系统1000的组件可容置在单个单元中或分布在多个互连单元(例如,通过通信网络)内。系统1000的组件还可包含远程装置及多种计算机可读媒体中的任一者。
从前述将明白,本文中已出于说明目的描述本技术的特定实施例,但是可在不脱离本发明的情况下作出各种修改。例如,虽然关于HMC描述半导体裸片组合件的许多实施例,但是在其它实施例中,半导体裸片组合件可被配置为其它存储器装置或其它类型的堆叠式裸片组合件。此外,图1到9中说明的半导体裸片组合件包含在第二半导体裸片上布置成堆叠的多个第一半导体裸片。然而,在其它实施例中,半导体裸片组合件可包含堆叠在第二半导体裸片中的一或多者上的一个第一半导体裸片。特定实施例的背景中描述的新技术的某些方面还可在其它实施例中组合或消除。此外,虽然已在所述实施例的背景中描述与新技术的某些实施例相关联的优点,但是其它实施例也可展现出此类优点且并非所有实施例一定展现出此类优点以落在本技术的范围内。因此,本发明及相关联的技术可涵盖本文中未明确展示或描述的其它实施例。
Claims (28)
1.一种半导体裸片组合件,其包括:
封装支撑衬底;
电安装到所述封装支撑衬底的第一半导体裸片,所述第一裸片具有堆叠位区及从所述堆叠位区横向延伸的外围区域;
多个第二半导体裸片,其彼此上下堆叠,其中底部第二半导体裸片附接到所述第一裸片的所述堆叠位区;
附接到所述第一裸片的所述外围区域的热传递结构,所述热传递结构具有其中定位有所述第二裸片的腔,及入口;及
所述腔中的底部填充材料,其中所述底部填充材料具有在所述第二半导体裸片与所述热传递结构之间通过将所述底部填充材料通过所述入口注入到所述腔中造成的填角料,使得所述填角料的至少一部分沿所述热传递结构向上延伸。
2.根据权利要求1所述的半导体裸片组合件,其中所述热传递结构包括附接到所述第一裸片的所述外围区域的侧壁及在所述侧壁上方且附接到最上面第二裸片的顶部,且其中所述侧壁及所述顶部彼此一体式形成。
3.根据权利要求2所述的半导体裸片组合件,其中所述热传递结构包括附接到所述第一裸片的所述外围区域的侧壁及在所述侧壁上方且附接到最上面第二裸片的顶部,且其中所述侧壁及所述顶部是用粘合剂彼此附接的分离组件。
4.根据权利要求1所述的半导体裸片组合件,其中:
所述热传递结构包括侧壁及所述侧壁上方的顶部;
所述入口包括第一通道;
所述第二裸片包含所述底部第二裸片上的最上面第二裸片;
所述底部填充材料沿所述热传递结构向上延伸到至少靠近所述最上面第二裸片的层级;及
所述半导体裸片组合件进一步包括出口,所述出口包括第二通道。
5.根据权利要求4所述的半导体裸片组合件,其中所述第一通道延伸穿过所述侧壁的下部部分,且所述第二通道延伸穿过所述侧壁的上部部分。
6.根据权利要求4所述的半导体裸片组合件,其中所述第一通道及所述第二通道以近似相同高度延伸穿过所述侧壁。
7.根据权利要求4所述的半导体裸片组合件,其中所述第一通道延伸穿过所述侧壁且所述第二通道延伸穿过所述顶部。
8.根据权利要求7所述的半导体裸片组合件,其中所述第一通道延伸穿过所述侧壁的下部部分。
9.根据权利要求4所述的半导体裸片组合件,其中所述第一通道延伸穿过所述顶部且所述第二通道延伸穿过所述顶部。
10.根据权利要求1所述的半导体裸片组合件,其进一步包括经由所述入口注入到所述腔中的电介质液体,且其中所述电介质液体具有高于所述底部填充材料的热传导率。
11.一种半导体裸片组合件,其包括:
封装支撑衬底;
安装到所述封装支撑衬底的第一半导体裸片,所述第一裸片具有外围区域及堆叠区域;
多个第二半导体裸片,其包含附接到所述第一裸片的所述堆叠区域的底部第二裸片及堆叠在所述下部裸片上的上部第二裸片;
热传导壳体,其具有附接到所述第一裸片的所述外围区域的底座部分、附接到所述上部第二裸片的顶部,及入口;及
所述壳体中的介于所述底座部分与至少所述下部第二裸片之间的底部填充材料,其中所述底部填充材料是经由所述入口注入到所述腔中。
12.根据权利要求11所述的半导体裸片组合件,其中所述底座及所述顶部彼此一体式形成。
13.根据权利要求11所述的半导体裸片组合件,其中所述底座及所述顶部是分离组件,且所述顶部是由粘合剂附接到所述底座。
14.根据权利要求11所述的半导体裸片组合件,其中所述入口是第一通道,且所述装置进一步包括由第二通道界定的出口。
15.根据权利要求14所述的半导体裸片组合件,其中所述底座包括侧壁的部分,且所述第一通道延伸穿过所述侧壁的下部区域且所述第二通道延伸穿过所述侧壁的上部区域。
16.根据权利要求14所述的半导体裸片组合件,其中所述第一通道及所述第二通道延伸穿过所述顶部。
17.根据权利要求11所述的半导体裸片组合件,其进一步包括所述腔中的电介质液体。
18.根据权利要求11所述的半导体裸片组合件,其中所述底部填充材料至少部分隐藏所述入口的至少一部分。
19.一种半导体裸片组合件,其包括:
具有第一功能的第一裸片,所述第一裸片具有外围区域及堆叠位区;
多个第二裸片,其布置成堆叠且安装到所述第一裸片的所述堆叠位区;
附接到所述第一裸片的至少所述外围区域的热传递结构,所述热传递结构具有其中定位有所述第二裸片的腔,及入口;及
所述腔中介于所述第二裸片之间的底部填充材料,其中所述底部填充材料沿所述热传递结构向上延伸一定距离。
20.根据权利要求19所述的半导体裸片组合件,其中所述热传递结构具有第一部分,所述第一部分包含经配置以围绕所述第一裸片的至少一部分延伸的基座及经配置以定位在所述第一裸片的所述外围区域上方的凸肩,且其中所述凸肩粘附到所述第一裸片的所述外围区域。
21.根据权利要求19所述的半导体裸片组合件,其中所述热传递结构包括:
第一部分,所述第一部分包含经配置以围绕所述第一裸片的至少一部分延伸的基座及经配置以定位在所述第一裸片的所述外围区域上方的凸肩,且其中所述凸肩粘附到所述第一裸片的所述外围区域;及
附接到所述第一部分的第二部分,且所述第二部分具有附接到最上面第二裸片的顶部。
22.根据权利要求19所述的半导体裸片组合件,其中所述热传递结构包括侧壁及顶部,所述入口包括第一通道,且所述半导体裸片组合件包括由第二通道界定的出口。
23.根据权利要求22所述的半导体裸片组合件,其中所述侧壁具有经配置以附接到封装支撑衬底的基座及粘附到所述第一裸片的所述外围区域的凸肩。
24.根据权利要求22所述的半导体裸片组合件,其中所述第一通道延伸穿过所述侧壁的下部部分,且所述第二通道延伸穿过所述侧壁的上部部分。
25.根据权利要求22所述的半导体裸片组合件,其中所述第一通道延伸穿过所述侧壁且所述第二通道延伸穿过所述顶部。
26.根据权利要求22所述的半导体裸片组合件,其中所述第一通道及所述第二通道延伸穿过所述顶部。
27.根据权利要求19所述的半导体裸片组合件,其进一步包括所述热传递结构的所述腔中的电介质液体,且其中所述电介质液体具有高于所述底部填充材料的热传导率。
28.根据权利要求19所述的半导体裸片组合件,其中所述多个第二裸片包含安装到所述第一裸片的所述堆叠位区的底部第二裸片及最上面第二裸片,且其中所述底部填充材料沿所述热传递结构向上延伸到至少靠近所述最上面第二裸片的高度。
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PCT/US2015/037630 WO2016010703A1 (en) | 2014-07-14 | 2015-06-25 | Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111033733A (zh) * | 2017-08-22 | 2020-04-17 | 美光科技公司 | 集成半导体组合件及其制造方法 |
CN113809024A (zh) * | 2020-06-16 | 2021-12-17 | 美光科技公司 | 带盖微电子器件封装以及相关系统、装置和制造方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9691746B2 (en) | 2014-07-14 | 2017-06-27 | Micron Technology, Inc. | Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths |
US9397078B1 (en) * | 2015-03-02 | 2016-07-19 | Micron Technology, Inc. | Semiconductor device assembly with underfill containment cavity |
TWM512730U (zh) * | 2015-08-20 | 2015-11-21 | Cooler Master Co Ltd | 水冷式散熱裝置 |
KR102579876B1 (ko) * | 2016-02-22 | 2023-09-18 | 삼성전자주식회사 | 반도체 패키지 |
US10008395B2 (en) | 2016-10-19 | 2018-06-26 | Micron Technology, Inc. | Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill |
US10074633B2 (en) * | 2016-11-08 | 2018-09-11 | Micron Technology, Inc. | Semiconductor die assemblies having molded underfill structures and related technology |
US10170392B2 (en) * | 2017-04-05 | 2019-01-01 | International Business Machines Corporation | Wafer level integration for embedded cooling |
WO2019146039A1 (ja) * | 2018-01-25 | 2019-08-01 | ソフトバンク株式会社 | 三次元積層集積回路の冷媒による冷却方式と、それを用いた三次元積層集積回路 |
US10548239B1 (en) * | 2018-10-23 | 2020-01-28 | Google Llc | Cooling electronic devices in a data center |
US11011449B1 (en) * | 2020-02-27 | 2021-05-18 | Micron Technology, Inc. | Apparatus and method for dissipating heat in multiple semiconductor device modules |
KR20220075507A (ko) | 2020-11-30 | 2022-06-08 | 삼성전자주식회사 | 고 전도 층을 갖는 반도체 패키지 |
US11887908B2 (en) * | 2021-12-21 | 2024-01-30 | International Business Machines Corporation | Electronic package structure with offset stacked chips and top and bottom side cooling lid |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050224953A1 (en) * | 2004-03-19 | 2005-10-13 | Lee Michael K L | Heat spreader lid cavity filled with cured molding compound |
US20070126103A1 (en) * | 2005-12-01 | 2007-06-07 | Intel Corporation | Microelectronic 3-D package defining thermal through vias and method of making same |
US20130119528A1 (en) * | 2011-11-14 | 2013-05-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
WO2014069174A1 (ja) * | 2012-10-29 | 2014-05-08 | 富士電機株式会社 | 半導体装置 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4323914A (en) | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
US5001548A (en) | 1989-03-13 | 1991-03-19 | Coriolis Corporation | Multi-chip module cooling |
NO911774D0 (no) * | 1991-05-06 | 1991-05-06 | Sensonor As | Anordning ved innkapsling av et funksjonsorgan, samt fremgangsmaate for fremstilling av samme. |
US5405808A (en) | 1993-08-16 | 1995-04-11 | Lsi Logic Corporation | Fluid-filled and gas-filled semiconductor packages |
KR970005712B1 (ko) * | 1994-01-11 | 1997-04-19 | 삼성전자 주식회사 | 고 열방출용 반도체 패키지 |
JPH08116138A (ja) * | 1994-10-17 | 1996-05-07 | Mitsubishi Heavy Ind Ltd | 半導体レーザ素子の冷却装置 |
KR100236016B1 (ko) | 1996-12-16 | 1999-12-15 | 구자홍 | 적층형 반도체 패키지 및 그의 어셈블리 방법 |
US6153929A (en) * | 1998-08-21 | 2000-11-28 | Micron Technology, Inc. | Low profile multi-IC package connector |
US6686654B2 (en) | 2001-08-31 | 2004-02-03 | Micron Technology, Inc. | Multiple chip stack structure and cooling system |
SG104348A1 (en) * | 2002-11-21 | 2004-06-21 | Inst Of Microelectronics | Apparatus and method for fluid-based cooling of heat-generating devices |
US6724080B1 (en) | 2002-12-20 | 2004-04-20 | Altera Corporation | Heat sink with elevated heat spreader lid |
US7215018B2 (en) * | 2004-04-13 | 2007-05-08 | Vertical Circuits, Inc. | Stacked die BGA or LGA component assembly |
US20080042302A1 (en) | 2006-08-16 | 2008-02-21 | Crispell Robert B | Plastic overmolded packages with molded lid attachments |
US20100117209A1 (en) * | 2007-02-28 | 2010-05-13 | Bezama Raschid J | Multiple chips on a semiconductor chip with cooling means |
US7592697B2 (en) * | 2007-08-27 | 2009-09-22 | Intel Corporation | Microelectronic package and method of cooling same |
JP2010123881A (ja) * | 2008-11-21 | 2010-06-03 | Fujikura Ltd | コールドプレート |
US8299633B2 (en) * | 2009-12-21 | 2012-10-30 | Advanced Micro Devices, Inc. | Semiconductor chip device with solder diffusion protection |
JP2011216818A (ja) * | 2010-04-02 | 2011-10-27 | Elpida Memory Inc | 半導体装置の製造方法 |
US20120061059A1 (en) * | 2010-09-09 | 2012-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling mechanism for stacked die package and method of manufacturing the same |
JP2012253104A (ja) * | 2011-05-31 | 2012-12-20 | Zycube:Kk | インターポーザを用いた積層モジュールの実装構造 |
US8526186B2 (en) | 2011-07-11 | 2013-09-03 | Texas Instruments Incorporated | Electronic assembly including die on substrate with heat spreader having an open window on the die |
JP5867259B2 (ja) * | 2012-04-17 | 2016-02-24 | 住友ベークライト株式会社 | 積層体の製造方法 |
-
2014
- 2014-07-14 US US14/330,900 patent/US9337119B2/en active Active
-
2015
- 2015-06-25 JP JP2017501357A patent/JP6625599B2/ja active Active
- 2015-06-25 CN CN201580037672.2A patent/CN106489202B/zh active Active
- 2015-06-25 KR KR1020177003816A patent/KR101996154B1/ko active IP Right Grant
- 2015-06-25 EP EP15822508.6A patent/EP3170201B1/en active Active
- 2015-06-25 WO PCT/US2015/037630 patent/WO2016010703A1/en active Application Filing
- 2015-07-06 TW TW104121886A patent/TWI548056B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050224953A1 (en) * | 2004-03-19 | 2005-10-13 | Lee Michael K L | Heat spreader lid cavity filled with cured molding compound |
US20070126103A1 (en) * | 2005-12-01 | 2007-06-07 | Intel Corporation | Microelectronic 3-D package defining thermal through vias and method of making same |
US20130119528A1 (en) * | 2011-11-14 | 2013-05-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
WO2014069174A1 (ja) * | 2012-10-29 | 2014-05-08 | 富士電機株式会社 | 半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111033733A (zh) * | 2017-08-22 | 2020-04-17 | 美光科技公司 | 集成半导体组合件及其制造方法 |
CN111033733B (zh) * | 2017-08-22 | 2023-11-28 | 美光科技公司 | 集成半导体组合件及其制造方法 |
CN113809024A (zh) * | 2020-06-16 | 2021-12-17 | 美光科技公司 | 带盖微电子器件封装以及相关系统、装置和制造方法 |
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