CN106486482B - 集成电路和制造集成电路的方法 - Google Patents

集成电路和制造集成电路的方法 Download PDF

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CN106486482B
CN106486482B CN201510834395.XA CN201510834395A CN106486482B CN 106486482 B CN106486482 B CN 106486482B CN 201510834395 A CN201510834395 A CN 201510834395A CN 106486482 B CN106486482 B CN 106486482B
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N·卢贝
P·莫林
Y·米尼奥
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STMicroelectronics lnc USA
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Abstract

本公开的实施方式涉及拉伸性硅和压缩性硅锗的共整合。在此披露了其中的邻近的pFET和nFET的应变特性是独立可调的集成电路。这些pFET包括在硅衬底上的压缩性应变SiGe，而这些nFET包括在应变弛豫的SiGe衬底上的拉伸性应变硅。通过镶嵌工艺形成的多个电绝缘区将邻近的n型鳍式FET和p型鳍式FET分离。在这些绝缘区形成过程中，允许支撑这些n型器件的该SiGe衬底弹性地弛豫，由此限制在该SiGe衬底的晶格中形成缺陷。

Description

集成电路和制造集成电路的方法
技术领域
本披露总体上涉及用于制造高性能鳍式场效晶体管(FinFET)的技术，并且具体地讲，涉及用于减少应变硅晶体管中的缺陷的技术。
背景技术
先进的集成电路的特征经常在于应变沟道晶体管、绝缘体上硅(SOI)衬底、鳍式FET结构或其组合，以便继续按比例决定低于20nm的晶体管栅极长度。这类技术允许使晶体管的沟道长度更小同时最小化有害结果如电流泄漏和其他短沟道效应。
鳍式FET是特征在于从衬底表面向外延伸的半导体鳍形式的导电沟道的电子切换器件。在这种器件中，控制鳍中的电流流动的栅极环绕该鳍的三侧以影响来自三个表面而不是一个表面的电流流动。与常规平面型器件相比，用鳍式FET设计实现的改进控制带来“接通”状态下的更快的切换性能和“关断”状态下的更少电流泄漏。在美国专利8,759,874和美国专利申请公开US2014/0175554中进一步详细地描述了鳍式FET。
应变硅晶体管已经被开发以增加穿过半导体晶格的载流子(即，电子或空穴)的迁移率。将应变结合到半导体器件的沟道中拉伸了晶体晶格，由此增加了沟道中的载流子迁移率，由此使得该器件变为更具有响应性的开关。将压缩性应变引入到pFET晶体管中倾向于增加沟道中的空穴迁移率，导致了对施加到晶体管栅极的电压的变化的更快的切换响应。类似地，将拉伸性应变引入到nFET中倾向于增加沟道中的电子迁移率，也导致了更快的切换响应。
针对平面型器件和鳍式FET两者，存在多种方式来将拉伸性应变或压缩性应变引入到晶体管中。通常，此类技术需要将一种或多种材料的多个外延层结合到器件中，这些材料具有稍微不同于硅衬底的晶体晶格尺寸或几何形状。通过控制晶体的元素组成来调整外延生长晶体内的应变和迁移率效果。此类外延层可以被结合到源极区和栅极区中、被结合到被用于调制沟道中的电流流动的晶体管栅极中、或者被结合到作为鳍的一部分的沟道自身中。例如，引入应变的一种方式为用硅化合物(如硅锗(SiGe))来替换来自源极区和漏极区或者来自沟道的体硅。因为Si-Ge键合比Si-Si键合更长，在SiGe晶格中存在更多的开放空间。存在具有更长键合的锗原子拉伸性晶格，导致内部应变。相比于穿过包含较短的Si-Si键合的晶格，穿过包含狭长的Si-Ge键合和Ge-Ge键合的晶格的电子可以移动得更加自由。在外延晶体生长的受控过程中，其中，新的SiGe晶体层从体硅晶体的表面中生长，可以完成用SiGe原子替换硅原子同时维持下面的体硅晶体的相同的晶体结构。已经确定，与较低浓度的SiGe膜相比，含有高浓度的锗(例如，在25％-40％的范围中)的外延SiGe膜提供增强的电子迁移率。因此，从设备性能的角度来看，增加鳍式FET中的鳍中的锗原子的百分比浓度通常是有利的。
替代性地，通过使用各种类型的绝缘体上硅(SOI)衬底，可以在从器件下方的鳍中引起应变。SOI衬底的特征在于掩埋绝缘体，通常为在有源区下面的掩埋氧化物层(BOX)。已在转让给本受让人的专利申请中披露了SOI鳍式FET器件，例如，题为“具有应变性沟道的SOI鳍式FET晶体管(SOI FinFET Transistor with Strained Channel)”的美国专利申请No.14/231,466、题为“硅锗绝缘体上鳍式FET(Silicon Germanium-on-insulatorFinFET)”的美国专利申请No.14/588,116以及题为“无缺陷的应变弛豫的缓冲层(Defect-Free Strain-Relaxed Buffer Layer)”的美国专利申请No.14/588,221。
虽然应变硅晶格是有益的，通过使用现有方法结合锗原子来创造应变倾向于损坏晶体晶格。结果，富锗膜的晶格结构倾向于为机械上不稳定的，尤其如果其包含高数量的结构缺陷，如故障或错位。此外，机械上不稳定的SiGe鳍可以是关于其纵横比或高宽比在结构上受限制的。此限制是不令人期望的，因为鳍式FET的一个优点是竖直结构的鳍具有小的占用面积。
发明内容
通过创造弛豫的富锗层作为应变膜的替代方案可以避免导致鳍式FET中的机械不稳定性的错位缺陷。本披露的自对准SiGe鳍式FET器件的特征在于应变弛豫的具有高锗浓度的衬底。披露了其中构成pFET和nFET的应变特性是独立可调的集成电路。pFET包括在硅衬底上的压缩性应变SiGe，而nFET包括在应变弛豫的SiGe衬底上的拉伸性应变硅。通过使用镶嵌工艺形成的绝缘区将邻近的n型鳍式FET和p型鳍式FET分离。在绝缘区的形成过程中，允许支撑n型器件的SiGe衬底弹性地弛豫，由此限制SiGe衬底的晶格中的缺陷形成。
附图说明
在附图中，完全相同的参考号标识类似的元件或操作。附图中元件的大小和相对位置不一定成比例地绘制。
图1是示出根据如本文所述的一个实施例的制造集成电路的第一方法中的步骤的流程图，该集成电路包括压缩性应变SiGe pFET以及拉伸性硅nFET。
图2A是根据如本文所述的一个实施例的在硅衬底上的SiGe有源层的俯视平面图。
图2B是对应于图2A的横截面图。
图3A是根据如本文所述的一个实施例的在硅衬底的nFET区中形成的大沟槽的俯视平面图。
图3B是图3A中所示的大沟槽的横截面图。
图4A是根据如本文所述的一个实施例的指示在氧化物表面下方形成的鳍的定向的硅的有源层的俯视平面图。
图4B是根据如本文所述的一个实施例的如图4A中所示的硅的有源层沿着基本上平行于鳍的切割线4B-4B的横截面图。
图4C是根据如本文所述的一个实施例的硅的有源层沿着横跨鳍的切割线4C-4C的横截面图。
图5A是根据如本文所述的一个实施例的在nFET区与pFET区之间形成隔离沟槽之后硅的有源层的俯视平面图。
图5B、图5C是对应于图5A的横截面图。
图6A是根据如本文所述的一个实施例的在用氧化物填充隔离沟槽和鳍间区之后硅的有源层的俯视平面图。
图6B、图6C是对应于图6A的横截面图。
图7A是根据如本文所述的一个实施例的在形成多晶硅栅极之后nFET和pFET的俯视平面图。
图7B、图7C是对应于图7A的横截面图。
图8是示出根据如本文所述的替代实施例的制造集成电路的第二方法中的步骤的流程图，该集成电路包括压缩性应变SiGe pFET以及拉伸性硅nFET。
图9是示出根据图8中所示的第二制造方法在鳍形成之前nFET器件和pFET器件之间的隔离区的横截面图。
图10是示出根据如本文所述的一个实施例的比居间应变弛豫的SiGe衬底浅的nFET器件和pFET器件之间的隔离区的横截面图。
具体实施方式
在以下说明中，陈述了某些具体细节以便提供对所披露的主题的不同方面的全面理解。然而，所披露的主题可以在没有这些具体细节的情况下实施。在一些实例中，尚未具体描述公知的结构和半导体加工方法以免模糊本披露的其他方面的描述。
除非上下文另有要求，否则贯穿说明书和所附权利要求书，“包括(comprise)”一词及其多种变体(诸如，“包括(comprises)”和“包括(comprising)”)将以一种开放式的和包含性的意义来进行解释，也就是作为“包括，但不限于(including,but not limitedto)”。
贯穿本说明书对“一个实施例”或“一种实施例”的引用意味着关于实施例所描述的特定的特征、结构、或特性是包括在至少一个实施例中的。因此，在贯穿本说明书的各种地方出现的短语“在一个实施例中”或“在一种实施例中”不一定都是指相同的方面。此外，可以将这些特定的特征、结构、或特性以任何适当的方式在本披露的一个或多个方面中进行组合。
贯穿本说明书对集成电路的引用一般旨在于包括在半导体衬底上构建的集成电路部件，无论部件是否被一起耦接到电路中或者能够被互连。贯穿本说明书，以最广泛的意义使用术语“层”以包括薄膜、帽盖等，并且一个层可以由多个子层组成。
贯穿说明书对用于沉积氮化硅、二氧化硅、金属或者相似材料的常规薄膜沉积技术的引用包括诸如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、金属有机化学气相沉积(MOCVD)、等离子体增强化学气相沉积(PECVD)、等离子体气相沉积(PVD)、原子层沉积(ALD)、分子束外延(MBE)、电镀、无电镀等这样的工艺。在此参考这类工艺的示例描述特定的实施例。然而，本披露和对某些沉积技术的引用不应当被限制于所描述的这些。例如，在一些境况中，可以替代性地使用PVD来完成引用CVD的描述，或者可以替代性地使用无电镀来实现指定电镀的描述。此外，对薄膜形成的常规技术的引用可以包括原位生长膜。例如，在一些实施例中，可以通过在受热室中使硅表面暴露于氧气或者潮气来实现控制氧化物生长至所期望的厚度。
贯穿本说明书对在半导体制造领域中已知的用于图案化各种薄膜的常规光刻技术的引用包括旋涂-曝光-显影工艺序列，通常接着是刻蚀工艺。替代性地或者附加地，光刻胶也可以用于图案化硬掩模(例如，氮化硅硬掩模)，其中，硬掩模又可以反过来用于图案化下面的膜。
贯穿本说明书对在半导体制造领域中已知的用于选择性去除多晶硅、氮化硅、二氧化硅、金属、光刻胶、聚酰亚胺或者类似材料的常规刻蚀技术的引用包括比如湿法化学刻蚀、反应离子(等离子体)刻蚀(RIE)、洗涤、湿法清洗、预清洗、喷洗、化学机械平坦化(CMP)等这样的工艺。在此参考这类工艺的示例描述特定的实施例。然而，本披露和对某些沉积技术的引用不应当被限制于所描述的这些。在一些实例中，两种这样的技术可以是可互换的。例如，剥离光刻胶可能需要在湿法化学浴器中浸渍样本或者替代性地向样本上直接喷射湿化学剂。
在此参考已经产生的共整合的拉伸性nFET和压缩性pFET来描述特定的实施例。然而，本披露和对某些材料、尺寸以及加工步骤的细节和次序的引用是示例性的，并且不应当被限制于所示的这些。
现在转到附图，图1示出了根据一个实施例的制造与具有拉伸性应变的n型鳍式FET或nFET共整合的具有压缩性应变的p型鳍式FET或pFET的方法200中的步骤。方法200中的步骤202至219由图2A至图7C展示并在以下被描述。在各图中，A是共整合的鳍式FET在制造过程中的本步骤中的俯视平面图，指示横截面图的切割线；B是沿平行于鳍式FET的鳍的切割线的横截面图；并且C是沿横向于鳍的切割线的横截面图。一个示例性的nFET和两个示例性的pFET示于每一个横截面图中。
在202处，在硅衬底220上生长具有压缩性应变的毯覆外延SiGe膜，以形成压缩性SiGe有源层222。压缩性SiGe有源层222(cSiGe)令人期望地在大约10nm厚至100nm厚的范围中，其中目标厚度是40nm，并且具有在大约15％至50％的范围中的Ge浓度，其中目标浓度是25％的锗。压缩性SiGe有源层222是完全压缩性应变的膜，它将包括p型鳍式FET的至少一个源极和一个漏极以及将该源极耦合到该漏极的鳍沟道。
在204处，根据如在图2A、图2B、图3A和图3B中示出的一个实施例，将压缩性SiGe有源层222和硅衬底220一起图案化，以开出nFET区并且覆盖pFET区。首先，在压缩性SiGe有源层222上沉积毯覆硬掩模224，并使用光刻胶226以及(任选地)光学平坦化层(OPL)以通常的方式将其图案化。硬掩模224以及如下所述的随后的硬掩模可以由SiN、SiO2或SiO2/SiN双层制成。可以根据任何常规方法(例如，等离子体增强CVD(PE-CVD)、低压CVD(LP-CVD)、快速热CD(RT-CVD)、原子层沉积(ALD)等)来沉积硬掩模224。然后，使用SiN硬掩模224来在下面的外延SiGe层中蚀刻开口228，该开口228进一步延伸到硅衬底220中，以形成具有宽度“a”和深度“d”的镶嵌沟槽。该宽度可以在在10nm至100um的范围中的任何地方。深度令人期望地在大约50nm至400nm的范围中。例如，尺寸a和d可以取决于是否是在制造逻辑或SRAM器件。
在206处，根据如在图4B、图4C中示出的一个实施例，形成厚SiGe层230以填充开口228。填充开口228完成在稍后将在彼处形成nFET的有源层下面在硅衬底220中形成应变SiGe层的镶嵌工艺。厚SiGe层230有效地用作取代硅衬底220的衬底。在一个实施例中，通过从下面的硅衬底220的选择性外延生长来形成厚SiGe层230。只在nFET区中，选择性外延工艺从底部进行到顶部，在硅衬底220的表面处停止。在选择性外延工艺过程中，硬掩模224保持在原位。例如，可以使用甲氯基化学或硅烷基化学来抑制从硅衬底220的侧壁的生长，由此实现定向沉积。这样的用于定向外延的技术是外延晶体生长领域的技术人员已知的。可以通过调整锗浓度在不形成晶体缺陷的情况下使厚SiGe层230的厚度最大化。使鳍沟道中的机械应力最大化的进一步的优化可能需要形成具有竖直锗浓度梯度的厚SiGe层230，该竖直锗浓度梯度可以通过在定向沉积步骤期间改变锗的量来实现。替代性地，也可以使用用于定向外延的其他技术来生长厚SiGe层230。nFET区中的所得的镶入的厚SiGe层230具有压缩性应变。
在208处，根据如在图4B和图4C中示出的一个实施例，形成外延硅有源层232。在一个实施例中，也从厚SiGe层230的表面向上定向生长外延硅有源层232，同时抑制从SiGe有源层222的侧壁的生长。外延硅有源层232具有大约等于周围的压缩性SiGe层222的厚度目标的厚度目标。外延硅有源层232由此在有源区中形成，该有源区将包括n型鳍式FET的源极和漏极以及将源极耦合到漏极的鳍沟道。可以在与厚SiGe层230相同的工艺中作为增加的步骤来生长外延硅有源层232，其中，在硅锗和硅之间的转变时断开锗气体的流动。可以使用定时的外延工艺，其中，针对每个步骤的时间是基于所期望的掩模开口a以及外延SiGe和外延硅中的每一者的已知生长速率。可以在外延生长期间对外延硅有源层232的源极区和漏极区进行原位掺杂。这样形成的外延硅有源层232是具有类似于衬底220的晶体结构的晶体结构的弛豫层。
在210处，在定向外延步骤之后，例如通过任何合适的方法去除硬掩模224。
在212处，根据如在图4A和图4C中示出的一个实施例，在压缩性SiGe有源层222中并且在拉伸性硅有源层232中形成鳍240。图4A示出了在形成鳍240和鳍间氧化物244之后nFET和pFET的俯视图。虽然表面覆盖有衬垫氧化物242，但下面的鳍240由虚线表示，也描绘了厚SiGe层230的边界的外延硅有源层232也由虚线表示。
在鳍式FET器件中，鳍体现了导电沟道，该导电沟道将源极区与漏极区彼此耦合。为了形成鳍240，在图4C中所示，沉积第一衬垫氧化物242，并且在衬垫氧化物242的顶部，衬垫氮化物(SiN)层被用作鳍硬掩模(未示出)以通过常规光刻方法限定鳍240。替代性地，可以使用侧壁图像转印(SIT)方法来限定鳍240，该方法能够产生非常窄的特征，如本领域中已知。在一个实施例中，鳍240具有在大约5nm至20nm的范围中的鳍宽度。在pFET区中，鳍240竖直地延伸到压缩性SiGe有源层222下方的硅衬底220中。在nFET区中，鳍240竖直地延伸穿过拉伸性硅有源层232并进入厚SiGe层230。在鳍形成之后，去除各自带有鳍图案的衬垫氧化物242和鳍硬掩模。为下一个工艺步骤做准备，用鳍间氧化物244填充鳍240之间的空间。然后将鳍间氧化物244平坦化以重新建立垫氧化物242：略高于鳍240和鳍间氧化物244。
在214处，根据如在图5A至图5C中示出的一个实施例，在pFET有源区与nFET有源区之间制作基本上平行于鳍240的平行切口252和横向于鳍240的竖直切口254。首先，在衬垫氧化物242的顶部形成SiN切割硬掩模250。然后在SiN切割硬掩模250中将平行切口252图案化，如图5A、图5C中所示。然后通过蚀刻将图5A中所示的平行切口252的图案转移到衬底220，使得平行切口252在厚SiGe层230和硅衬底220之间向下延伸到切口深度245。在图5B、图5C中，切口深度245被示为略低于SiGe深度d。然而，通常，切口深度245可以小于、等于或大于厚SiGe层230的深度d，虽然切口深度245大于厚SiGe层230的深度d可以是有利的。
接着，在随后的光刻步骤中，在切割硬掩模250中将竖直切口254图案化，如图5A、图5B中所示。然后通过蚀刻将图5A中所示的竖直切口254的图案转移到衬底220，使得竖直切口254在厚SiGe层230和硅衬底220之间向下延伸到平行切口252大约相同的切口深度245，如图5B中所示。切口252、254中的每一个由此产生邻近厚SiGe层230的下部部分的三个自由表面253。竖直切口254的深度可以小于、等于或大于平行切口252的深度。
由于制作了平行切口252，厚SiGe层230在平行于有源层222和232的水平方向上部分或完全弹性地弛豫(rSiGe)。这样的弹性弛豫将厚SiGe层230从压缩性应变层变换成镶入在硅衬底220中的应变弛豫的SiGe区258。弹性弛豫发生时不会产生缺陷，这否则将在依赖于塑料弛豫的常规工艺中发生。同样地，由于制作了竖直切口254，应变弛豫的SiGe区258经受双轴弹性弛豫，其中，SiGe在所有方向上完全弹性地弛豫，也不会产生缺陷。在制作切口252、254的相同的时间，从压缩性SiGe有源层222分割上覆外延硅有源层232，并且将外延硅有源层232变换成双轴拉伸性应变膜。所得的拉伸性硅有源层243提供nFET鳍内的优异的电子迁移率。同时，拉伸性硅有源层243的任一侧的压缩性SiGe有源层222仍然完全压缩性应变，以提供pFET鳍内的优异的空穴迁移率。以这种方式，独立地调整pFET中的压缩性应变和nFET中的拉伸性应变。
在216处，根据如在图6A至图6C中示出的一个实施例，从切割硬掩模250剥离光刻胶并且以氧化物填充切口252、254，由此分别产生绝缘区262、264。绝缘区262、264将nFET和pFET彼此电绝缘。与通常的倾斜侧对比，绝缘区262、264具有基本上直的竖直侧。然后在去除切割硬掩模250之前，将绝缘区262、264内的氧化物平坦化，以在切割硬掩模250上停止。然后使氧化物进一步凹进，以便从鳍240去除衬垫氧化物242。绝缘区262、264可以延伸超出鳍240的顶部，如图6B、图6C中所示。
在218处，根据如在图7A至图7C中示出的一个实施例，横向于鳍240形成栅极结构255。鳍式FET器件的栅极结构255环绕每个鳍的三侧，以便比在常规的平面型器件中更精确地控制其中的电流流动。栅极结构255包括栅极电介质266和栅极268，例如，该栅极可以由多晶硅制成。替代性地，栅极268可以由金属制成，或者它最初可以由多晶硅制成并且以后使用如本领域中公知的替代金属栅极工艺由金属替代。首先，部分地去除绝缘区262、264内的氧化物，向下到衬底220的表面。接着，在鳍240之上形成栅极电介质266，例如SiO2、HfO2等的薄层。最后，在栅极电介质266的顶部形成厚多晶硅栅极268，并且以通常的方式以横向于鳍的特征将栅极电介质266和多晶硅栅极268图案化。
在219处，根据一个实施例，对源极区和漏极区进行掺杂。可以使用现有的栅极结构255作为掩模通过离子注入或等离子体注入或其组合来对p型压缩性SiGe有源层222和n型拉伸性硅有源层232的源极区和漏极区进行掺杂。替代性地，可以从源极区和漏极区外延生长升高的源极区和漏极区并且对其进行原位掺杂。使用任一技术，自对准掺杂步骤完成共整合的nFET器件和pFET器件的形成。
图8示出了根据替代实施例的制造与具有拉伸性应变的n型鳍式FET或nFET共整合的具有压缩性应变的p型鳍式FET或pFET的方法300中的一系列步骤。在该方法300中，一些步骤以不同的顺序发生，例如，在绝缘区262、264之后形成鳍240。
图9和图10示出了根据包括步骤302至320的方法300形成的结构320a、320b的示例性横截面图。结构320a、320b示出了步骤314之后的nFET和pFET，该步骤314是在绝缘区264的完成之后，但在316处的鳍240的形成之前。在图9中，绝缘区264a延伸到低于应变弛豫的SiGe区258的深度d的深度245a。在图10中，绝缘区264b延伸到高于应变弛豫的SiGe区258的深度d的深度245b。示例性方法300中的步骤的顺序在其他方面类似于方法200中的步骤的顺序。如在方法200中，通过方法300制作的绝缘区262和264可以延伸到小于、等于或大于限定了应变弛豫的SiGe区258的边界的沟槽的深度的深度，同时仍引起SiGe的弛豫以及硅有源层232中的拉伸性应变。
将理解的是，尽管出于说明的目的在此描述了本披露的多个特定的实施例，在不背离本披露的精神和范围的情况下可以进行各种修改。相应地，除所附权利要求书之外，本披露不受限制。
鉴于以上详细的描述，可以对这些实施例做出这些和其他改变。总之，在以下权利要求书中，所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例，而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。因此，权利要求并不局限于本披露的范围。
以上所描述的各个实施例可以被组合以提供进一步的实施例。在本说明书中所提及的和/或在申请资料表中所列出的所有美国专利、美国专利申请出版物、美国专利申请、国外专利、国外专利申请和非专利出版物都以其全文通过引用结合在此。如果有必要，可以对实施例的各方面进行修改，以采用各专利、申请和公开的概念来提供更进一步的实施例。

Claims (20)

1.一种集成电路，包括：
硅衬底；
在所述硅衬底上的压缩性SiGe有源层；
p型鳍式FET，所述p型鳍式FET在所述压缩性SiGe有源层中形成；
应变弛豫的SiGe区，所述应变弛豫的SiGe区镶入所述硅衬底中；
拉伸性硅有源层，所述拉伸性硅有源层在所述应变弛豫的SiGe区上并且邻近所述压缩性SiGe有源层；
n型鳍式FET，所述n型鳍式FET在所述拉伸性硅有源层中形成；以及
多个电绝缘区，所述多个电绝缘区定位在所述p型鳍式FET和所述n型鳍式FET之间并且定位在所述应变弛豫的SiGe区和所述硅衬底之间。
2.如权利要求1所述的集成电路，其中，所述拉伸性硅有源层由所述压缩性SiGe有源层包围。
3.如权利要求1所述的集成电路，其中，所述拉伸性硅有源层与所述应变弛豫的SiGe区竖直地对准。
4.如权利要求1所述的集成电路，其中，所述多个电绝缘区具有直的竖直侧和在50nm至100nm的范围中的宽度。
5.如权利要求1所述的集成电路，其中，所述多个电绝缘区在所述压缩性SiGe有源层以及所述拉伸性硅有源层的顶表面之上延伸。
6.如权利要求1所述的集成电路，其中，所述压缩性SiGe有源层和所述拉伸性硅有源层具有在10nm至100nm的范围中的厚度。
7.如权利要求1所述的集成电路，其中，所述压缩性SiGe有源层具有在15％和50％的范围中的锗浓度。
8.如权利要求1所述的集成电路，其中，所述压缩性SiGe有源层具有在40nm至1000nm的范围中的宽度。
9.如权利要求1所述的集成电路，其中，所述应变弛豫的SiGe区延伸到所述硅衬底中50nm至400nm的深度。
10.如权利要求1所述的集成电路，其中，所述拉伸性硅有源层与所述压缩性SiGe有源层具有类似的厚度。
11.一种制造集成电路的方法，包括：
在硅衬底上形成毯覆SiGe层，所述SiGe层具有压缩性应变；
掩蔽所述SiGe层的pFET区；
用SiGe衬底部分替换所述硅衬底在nFET区中的部分；
在所述nFET区中在所述SiGe衬底部分之上形成外延硅有源层；
沿着将所述SiGe衬底部分的至少一部分与所述硅衬底分离的所述nFET区的至少两侧形成多个沟槽，由此减轻所述SiGe衬底部分的应变并且在所述硅有源层中引起拉伸性应变；
在所述多个沟槽中形成电绝缘材料；
将在所述pFET区和所述nFET区中的多个鳍图案化；以及
形成环绕所述多个鳍的三侧的栅极结构。
12.如权利要求11所述的方法，其中，在形成所述多个沟槽之前将所述多个鳍图案化。
13.如权利要求11所述的方法，其中，在形成所述多个沟槽之后将所述多个鳍图案化。
14.如权利要求11所述的方法，其中，形成所述多个沟槽在所述SiGe衬底部分中产生弹性弛豫。
15.如权利要求11所述的方法，其中，沿着所述nFET区的四侧形成多个沟槽，以在所述SiGe衬底部分中产生双轴弹性弛豫和在所述硅有源层中产生双轴拉伸性应变。
16.一种n型器件，包括：
衬底；
应变弛豫的SiGe区，所述应变弛豫的SiGe区在所述衬底内形成，所述应变弛豫的SiGe区具有第一深度；
n型拉伸性硅层，所述n型拉伸性硅层在所述应变弛豫的SiGe区的顶部；
源极区，所述源极区在所述n型拉伸性硅层中形成；
漏极区，所述漏极区在所述n型拉伸性硅层中形成；
鳍，所述鳍将所述源极区耦合到所述漏极区；
多个电绝缘区，所述多个电绝缘区定位在所述应变弛豫的SiGe区和所述衬底之间，所述多个电绝缘区具有大于所述第一深度的第二深度；以及
栅极结构，所述栅极结构环绕所述鳍的三侧。
17.如权利要求16所述的n型器件，其中，所述栅极结构包括栅极电介质和多晶硅栅极。
18.如权利要求16所述的n型器件，其中，所述栅极结构包括栅极电介质和金属栅极。
19.如权利要求16所述的n型器件，其中，所述应变弛豫的SiGe区没有晶体缺陷。
20.如权利要求16所述的n型器件，其中，所述多个电绝缘区具有延伸进入所述衬底50nm至400nm的直的侧。
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