CN106469663A - 铝栅cmos双层金属布线的制作工艺及其版图结构 - Google Patents

铝栅cmos双层金属布线的制作工艺及其版图结构 Download PDF

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CN106469663A
CN106469663A CN201610125636.8A CN201610125636A CN106469663A CN 106469663 A CN106469663 A CN 106469663A CN 201610125636 A CN201610125636 A CN 201610125636A CN 106469663 A CN106469663 A CN 106469663A
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陈军建
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Abstract

本发明公开了一种铝栅CMOS双层金属布线的制作工艺和版图结构。其包括：叠加在MOS晶体管层之上，通过通孔实现电路连接的第一金属层；叠加在第一金属层之上，通过制作通孔进行电路连接的第二金属层以及设置在第一金属层和第二金属层之间的绝缘介质隔离层。所述第二金属层可以只用作压焊点设计。当需要时，所述第二金属层亦可通过制作通孔进行其它电路连接，完成集成电路内部电路设计。所述制作连接第一金属层和第二金属层的通孔(via)结构，具有工艺简单可靠的特点。使用该双层金属布线的制作工艺和结构方式，可有效的提高铝栅CMOS集成度，降低生产成本，使产品具有良好的市场竞争力。

Description

铝栅CMOS双层金属布线的制作工艺及其版图结构
技术领域
本发明涉及集成电路制造技术领域，尤其涉及铝栅CMOS双层金属布线的制作工艺和版图结构。
背景技术
单层金属布线的铝栅CMOS制作工艺和版图结构是最早采用的CMOS产品技术，已有几十年历史，至今还被广泛采用。但由于其受到制作工艺和版图结构
设计规则的制约，提高集成度受到限制，不利于产品技术的竞争。尤其现
有铝栅CMOS工艺技术采用单层金属布线，对集成电路的集成度明显不利。
随着工艺加工精度逐步提高、铝栅CMOS器件的尺寸逐步减小(例如：过去的特征尺寸为3.0微米，而现在的特征尺寸1.0微米)，设计规则不断进行相应改变。但目前正在采用传统的铝栅CMOS单层金属布线制作工艺和版图结构设计的产品，压焊点(输入和输出PAD、电源和地端PAD)及内部电路连接均设置在一层金属层(如图1所示的Metal)上完成，进一步提高集成电路的集成度受到制约。实践表明，诸多产品因集成度问题，使集成电路(芯片)面积小不下来而无法参与市场竞争而退出。实施例证表明改进单层金属布线传统工艺和版图结构可提高产品集成度、进一步小型化、降低产品成本是可行的。
目前正在采用的铝栅CMOS其制作工艺依次为：N型衬底材料片准备——初始氧化——P阱光刻——P阱腐蚀——P阱注入——P阱推进——基础氧化——N+光刻——N+注入——N+推进——P+光刻——P+注入——栅氧及扩散——VT注入——退火——接触孔光刻——金属化(溅射AL与光刻)——钝化(PECVD氮化硅+二氧化硅与光刻)——合金。
发明内容
鉴于现有单层金属布线的铝栅CMOS制作工艺和版图结构的不足之处，本发明的目的在于提供一种铝栅CMOS双层金属布线的版图结构及其制作工艺，旨在解决现有技术中单层金属的铝栅CMOS工艺设计的产品集成度低的问题。
为了达到上述目的，本发明采取了以下技术方案：
铝栅CMOS双层金属布线的制作工艺和版图结构。其中，所述制作工艺和版图结构包括：第一金属层、层叠在第一金属层上的第二金属层以及设置在第一金属层和第二金属层之间的绝缘介质隔离层；
所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其中，所述第一金属层为CMOS连接电路，所述第二金属层只设置为压焊点设计。
所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其中，所述第一金属层为CMOS电路连接设计，所述第二金属层设置有压焊点(输入和输出PAD、电源和地端PAD)，亦可作为CMOS电路连接使用。
所述介质隔离层是所述第一金属层与第二金属层之间的绝缘介质隔离层，所述第一金属层与第二金属层通过光刻绝缘介质隔离层制作的通孔、按电路功能要求进行电路连接。
所述的铝栅CMOS双层金属布线制作工艺和版图结构，其中，所述绝缘介质隔离层的材质为绝缘材质或氮化硅和二氧化硅组成的复合介质层
有益效果：本发明提供的铝栅CMOS双层金属布线的版图结构及其制作工艺，使用了双层金属布线的结构方式。与现有技术相比，可在不牺牲可靠性的前提下，有效的减少了芯片面积、提高铝栅CMOS集成度，降低了生产成本，具有良好的市场竞争力。
附图说明
图1为现有单层金属布线的铝栅CMOS版图结构和制作工艺示意图。
图2为本发明第一实施例的铝栅CMOS双层金属布线的版图结构和制作工艺示意图。
图3为本发明第二实施例的铝栅CMOS双层金属布线的版图结构和制作工艺示意图。
图4为应用现有单层金属布线的铝栅CMOS设计的集成电路平面图。
图5为应用本发明铝栅CMOS双层金属布线设计的集成电路平面图。
具体实施方式
本发明提供一种铝栅CMOS双层金属布线的版图结构及其制作工艺。为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
如图2所示，为本发明所述铝栅CMOS双层金属布线的制作工艺和版图结构的第一实施例。
所述制作工艺和版图结构包括：第一金属层M1，第二金属层M2，绝缘介质介质层100以及MOS晶体管层200，其他部分结构如图2所标示。其中，所述第一金属层M1用于电路内部连接，第二金属层M2用于压焊点(输入和输出PAD、电源和地端PAD)。第二金属层M2层叠在第一金属层M1上，通过绝缘介质隔离层隔离，第一金属层M1和第二金属层M2之间则通过光刻刻蚀通孔(VIA)进行电路连接。
上述第一实施例的具体制造工艺流程如下：
S1、准备N型衬底(N-SUB)的材料片。
S2、P-WELL制程(其包括：P井光刻、P井腐蚀、P井注入、P井去胶以及P井推进)。
S3、NPLUS制程(包括基础氧化、N+光刻、N+注入、N+去胶、N+推进)。
S4、PPLUS制程(包括：P+光刻、P+注入、P+去胶)。
S5、栅氧制程(包括：栅氧扩散、VT注入、栅氧化退火)。
S6、接触孔制程(包括：接触孔光刻、接触孔腐蚀、接触孔去胶)。
S7、metal1制程(即上述第一金属层M1)，其具体包括：metal1溅射、metal1光刻、metal1刻蚀、metal1去胶。
S8、PE钝化制程(氮化硅淀积、氮化硅光刻、氮化硅刻蚀、氮化硅去胶)。
S9、metal2制程(即上述第二金属层M2)，其具体包括：metal2溅射、metal2光刻、metal2刻蚀、metal2去胶。
如图3所示，为本发明所述铝栅CMOS双层金属布线的制作工艺和版图结构的第二实施例。
所述制作工艺和版图结构包括：第一金属层M1，第二金属层M2，介质层100以及半导体器件部分200，其他部分结构如图3所标示。
其中，所述第一金属层M1用于电路内部连接设计；第二金属层M2除用于压焊点(输入及输出PAD、电源和地端PAD)设计外，第二金属层还用于电路连接。第二金属层M2层叠在第一金属层M1上，通过绝缘介质隔离层隔离，第一金属层M1和第二金属层M2之间则通过光刻刻蚀通孔(VIA)进行电路连接。
上述第二实施例的具体制造工艺流程如下：
S1、准备N型衬底(N-SUB)的材料片，
S2、P-WELL制程(其包括：P井光刻、P井腐蚀、P井注入、P井去胶以及P井推进)。
S3、NPLUS制程(包括基础氧化、N+光刻、N+注入、N+去胶、N+推进)。
S4、PPLUS制程(包括：P+光刻、P+注入、P+去胶)。
S5、栅孔制程(包括：氧化、栅孔光刻、栅孔腐蚀、栅孔去胶)
S6、栅氧制程(包括：栅氧扩散、VT注入、栅氧化退火)。
S7、接触孔制程(包括：接触孔光刻、接触孔腐蚀、接触孔去胶)。
S8、metal1制程(即上述第一金属层M1)，其具体包括：metal1溅射、metal1光刻、metal1刻蚀、metal1去胶。
S9、PE teos。
S10、SOG。
S11、PE teos。
S12、metal2制程(即上述第二金属层M2)，其具体包括：metal2溅射、metal2光刻、metal2刻蚀、metal2去胶。
S13、PE钝化(包括：氮化硅淀积、氮化硅光刻、氮化硅刻蚀、氮化硅去胶。
应当说明的是，本发明所述版图结构和制作工艺，适用于任何铝栅CMOS双层金属布线集成电路的制造，如图2和图3所示的实施例或者其他改进
如图4所示
为应用现有单层金属布线的铝栅CMOS设计的集成电路平面图。
(包括正极10，负极20，输入PAD30以及输出PAD40)以及电路部分50。
其输入/输出PAD部分以及连接电路部分设置于同一金属层上，面积为375*250μm。
如图5所示
为应用本发明铝栅CMOS双层金属布线设计的集成电路平面图。
正极10，负极20，输入PAD30以及输出PAD40设置于另一金属层中，可以层叠在电路部分50上，同一功能的集成电路面积能够缩小至290*210μm。
与现有单层金属布线技术相比，将压焊点(输入和输出PAD、电源和地端PAD)与连接电路分别设置于两层不同的金属层上，从而减少了集成电路的面积，提高了集成度，降低成本。能够比传统工艺减少30％以上的面积，从而提高了产品技术的竞争力。
另外，第一金属层M1和第二金属层M2的连接通孔工艺要求不高，不需要开小尺寸通孔，因此，不会增加制造工艺的复杂度、不会引入不可靠因素。
综上所述，在传统的单层金属布线制作工艺和版图结构中，铝栅CMOS集成电路的集成度低，成本难以下降。而传统工艺为达成提高集成度，降低成本的目标时，往往会采用牺牲可靠性换取。
本发明所述的双层铝栅CMOS双层金属布线的制作工艺和版图结构。结合了多层金属布线的思路，在不牺牲可靠性的基础上，能够比传统制作工艺和版图结构减少30％以上面积，提高20％以上的竞争力，具有良好的应用前景。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及本发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (6)

1.铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述制作工艺和版图结构包括：第一金属层、层叠在第一金属层上的第二金属层以及设置在第一金属层和第二金属层之间的绝缘介质隔离层。
2.根据权利要求1所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述第一金属层设置为CMOS电路连接层，所述第二金属层设置为压焊点层。
3.根据权利要求1所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述第一金属层设置为CMOS电路连接层，所述第二金属层设置为压焊点和进行MOS电路连接。
4.根据权利要求1所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述压焊点为输入和输出PAD、电源和地端PAD。
5.根据权利要求1所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述介质层的材质为绝缘材质或氮化硅和二氧化硅复合介质层。
6.根据权利要求1所述的铝栅CMOS双层金属布线的制作工艺和版图结构，其特征在于，所述绝缘介质隔离层是所述第一金属层与第二金属层之间的绝缘介质层，所述第一金属层与第二金属层通过光刻刻蚀绝缘隔离介质层制作的通孔进行电路连接。
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