CN106469663A - The processing technology of alum gate CMOS two metal wired layers and its domain structure - Google Patents
The processing technology of alum gate CMOS two metal wired layers and its domain structure Download PDFInfo
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/3051—Function
- H01L2224/30515—Layer connectors having different functions
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- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
Abstract
The invention discloses a kind of processing technology of alum gate CMOS two metal wired layers and domain structure.It includes：It is superimposed upon on MOS transistor layer, realize the first metal layer of circuit connection by through hole；It is superimposed upon on the first metal layer, carry out the second metal layer of circuit connection and be arranged on the dielectric sealing coat between the first metal layer and second metal layer by making through hole.Described second metal layer can be only used as pressure welding point design.When needed, described second metal layer also can carry out other circuit connections by making through hole, completes lsi internal circuit design.Described through hole (via) structure making connection the first metal layer and second metal layer, has the characteristics that simple and reliable process.Using processing technology and the frame mode of this two metal wired layers, can effectively improve alum gate CMOS integrated level, reduce production cost, make product have the good market competitiveness.
Description
Technical field
The present invention relates to ic manufacturing technology field, the more particularly, to processing technology of alum gate CMOS two metal wired layers
And domain structure.
Background technology
The alum gate CMOS processing technology of single-layer metal wiring and domain structure are the earliest CMOS product technologies adopting, existing
Decades history, is also widely adopted so far.But because it is subject to processing technology and domain structure
The restriction of design rule, improves integrated level and is restricted, be unfavorable for the competition of product technology.Especially existing
Alum gate CMOS technology technology is had to adopt single-layer metal to connect up, the integrated level significant adverse to integrated circuit.
Step up with technique machining accuracy, the size of alum gate cmos device progressively reduces (for example：The feature chi in past
Very little is 3.0 microns, and 1.0 microns of present characteristic size), design rule is constantly accordingly changed.But currently adopt
Traditional alum gate CMOS single-layer metal connects up processing technology and the product of domain structure design, pressure welding point (input and output PAD,
Power supply and ground terminal PAD) and internal circuit connect be arranged at completing, further on layer of metal layer (Metal as shown in Figure 1)
The integrated level improving integrated circuit is restricted.Practice have shown that, all multi-products, because of integrated level problem, make integrated circuit (chip) face
Amass little not getting off and cannot participate in market competition and exit.Implement illustration to show to improve single-layer metal wiring traditional handicraft and domain
Structure can improve product integrated level, further miniaturization, reduce product cost be feasible.
Its processing technology of alum gate CMOS currently adopting is followed successively by：N-type substrate material piece prepares initial oxygen
Change p-well photoetching p-well corrosion p-well injection p-well propulsion base oxide N+ photoetching N+ note
Enter N+ propulsion P+ photoetching P+ injection grid oxygen and diffusing V T implantation annealing contact hole light
Carve metallization (sputtering AL and photoetching) passivation (PECVD silicon nitride+silicon dioxide and photoetching) alloy.
Content of the invention
In view of the weak point of the alum gate CMOS processing technology of existing single-layer metal wiring and domain structure, the mesh of the present invention
Be to provide a kind of domain structure of alum gate CMOS two metal wired layers and its processing technology it is intended to solve single in prior art
The low problem of product integrated level of the alum gate CMOS technology design of layer metal.
In order to achieve the above object, this invention takes technical scheme below：
The processing technology of alum gate CMOS two metal wired layers and domain structure.Wherein, described processing technology and domain structure
Including：The first metal layer, stacking second metal layer on the first metal layer and be arranged on the first metal layer and the second metal
Dielectric sealing coat between layer；
The described processing technology of alum gate CMOS two metal wired layers and domain structure, wherein, described the first metal layer is
CMOS connects circuit, and described second metal layer is only set to pressure welding point design.
The described processing technology of alum gate CMOS two metal wired layers and domain structure, wherein, described the first metal layer is
Cmos circuit connects design, and described second metal layer is provided with pressure welding point (input and output PAD, power supply and ground terminal PAD), also may be used
Connect as cmos circuit and use.
Described buffer layer is the dielectric sealing coat between described the first metal layer and second metal layer, described
Through hole that one metal level and second metal layer make by photoetching dielectric sealing coat, carry out circuit company by circuit function requirements
Connect.
Described alum gate CMOS two metal wired layers processing technology and domain structure, wherein, described dielectric sealing coat
Material be isolation material or silicon nitride and the compound medium layer of silicon dioxide composition
Beneficial effect：The domain structure of alum gate CMOS two metal wired layers and its processing technology that the present invention provides, use
The frame mode of two metal wired layers.Compared with prior art, can be effectively reduced on the premise of not sacrificing reliability
Chip area, raising alum gate CMOS integrated level, reduce production cost, have the good market competitiveness.
Brief description
Fig. 1 is alum gate CMOS domain structure and the processing technology schematic diagram of existing single-layer metal wiring.
Fig. 2 is the domain structure of alum gate CMOS two metal wired layers and the processing technology signal of first embodiment of the invention
Figure.
Fig. 3 is the domain structure of alum gate CMOS two metal wired layers and the processing technology signal of second embodiment of the invention
Figure.
Fig. 4 is the integrated circuit plane figure of the alum gate CMOS design of application existing single-layer metal wiring.
Fig. 5 is the integrated circuit plane figure of application alum gate CMOS two metal wired layers of the present invention design.
Specific embodiment
The present invention provides a kind of domain structure of alum gate CMOS two metal wired layers and its processing technology.For making the present invention's
Purpose, technical scheme and effect are clearer, clear and definite, and the embodiment that develops simultaneously referring to the drawings is to the present invention further specifically
Bright.It should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Fig. 2 for the processing technology of alum gate CMOS two metal wired layers of the present invention and domain structure first
Embodiment.
Described processing technology and domain structure include：The first metal layer M1, second metal layer M2, dielectric dielectric layer
100 and MOS transistor layer 200, other parts structure such as Fig. 2 are indicated.Wherein, described the first metal layer M1 is used in circuit
Portion connects, and second metal layer M2 is used for pressure welding point (input and output PAD, power supply and ground terminal PAD).Second metal layer M2 is layered in
On the first metal layer M1, isolated by dielectric sealing coat, between the first metal layer M1 and second metal layer M2, then pass through light
Carve etching through hole (VIA) and carry out circuit connection.
The concrete manufacturing process flow of above-mentioned first embodiment is as follows：
S1, the material piece of preparation N-type substrate (N-SUB).
(it includes S2, P-WELL processing procedure：P well photoetching, the injection of P well burn into P well, P well remove photoresist and the propulsion of P well).
S3, NPLUS processing procedure (includes base oxide, N+ photoetching, N+ injection, N+ removes photoresist, N+ advances).
S4, PPLUS processing procedure (includes：P+ photoetching, P+ injection, P+ remove photoresist).
S5, grid oxygen processing procedure (include：Grid oxygen diffusion, VT injection, grid oxygen annealing).
S6, contact hole processing procedure (include：Contact hole photoetching, contact hole burn into contact hole remove photoresist).
S7, metal1 processing procedure (i.e. above-mentioned the first metal layer M1), it specifically includes：Metal1 sputtering, metal1 photoetching,
Metal1 etching, metal1 remove photoresist.
S8, PE passivation processing procedure (silicon nitride deposition, silicon nitride photoetching, silicon nitride etch, silicon nitride remove photoresist).
S9, metal2 processing procedure (i.e. above-mentioned second metal layer M2), it specifically includes：Metal2 sputtering, metal2 photoetching,
Metal2 etching, metal2 remove photoresist.
As shown in figure 3, for the processing technology of alum gate CMOS two metal wired layers of the present invention and domain structure second
Embodiment.
Described processing technology and domain structure include：The first metal layer M1, second metal layer M2, dielectric layer 100 and half
Conductor device part 200, other parts structure such as Fig. 3 is indicated.
Wherein, described the first metal layer M1 is used for inside circuit connecting design；Second metal layer M2 is removed (defeated for pressure welding point
Enter and export PAD, power supply and ground terminal PAD) design outward, second metal layer is additionally operable to circuit and connects.Second metal layer M2 is layered in
On the first metal layer M1, isolated by dielectric sealing coat, between the first metal layer M1 and second metal layer M2, then pass through light
Carve etching through hole (VIA) and carry out circuit connection.
The concrete manufacturing process flow of above-mentioned second embodiment is as follows：
S1, the material piece of preparation N-type substrate (N-SUB),
(it includes S2, P-WELL processing procedure：P well photoetching, the injection of P well burn into P well, P well remove photoresist and the propulsion of P well).
S3, NPLUS processing procedure (includes base oxide, N+ photoetching, N+ injection, N+ removes photoresist, N+ advances).
S4, PPLUS processing procedure (includes：P+ photoetching, P+ injection, P+ remove photoresist).
S5, gate hole processing procedure (include：Oxidation, gate hole photoetching, gate hole burn into gate hole are removed photoresist)
S6, grid oxygen processing procedure (include：Grid oxygen diffusion, VT injection, grid oxygen annealing).
S7, contact hole processing procedure (include：Contact hole photoetching, contact hole burn into contact hole remove photoresist).
S8, metal1 processing procedure (i.e. above-mentioned the first metal layer M1), it specifically includes：Metal1 sputtering, metal1 photoetching,
Metal1 etching, metal1 remove photoresist.
S9、PE teos.
S10、SOG.
S11、PE teos.
S12, metal2 processing procedure (i.e. above-mentioned second metal layer M2), it specifically includes：Metal2 sputtering, metal2 photoetching,
Metal2 etching, metal2 remove photoresist.
S13, PE passivation (includes：Silicon nitride deposition, silicon nitride photoetching, silicon nitride etch, silicon nitride remove photoresist.
It should be noted that domain structure of the present invention and processing technology are it is adaptable to any alum gate CMOS double-level-metal
The manufacture of wired integrated circuit, as with the embodiments shown in figures 2 and 3 or other improvement
As shown in Figure 4
For applying the integrated circuit plane figure of the alum gate CMOS design of existing single-layer metal wiring.
(including positive pole 10, negative pole 20, input PAD30 and output PAD40) and circuit part 50.
Its input/output PAD part and connection circuit part are arranged on same metal level, and area is 375*250 μm.
As shown in Figure 5
For applying the integrated circuit plane figure of alum gate CMOS two metal wired layers design of the present invention.
Positive pole 10, negative pole 20, input PAD30 and output PAD40 are arranged in another metal level, can be layered in circuit
In part 50, the integrated circuit area of same function can be contracted to 290*210 μm.
Compared with existing single-layer metal wiring technique, by pressure welding point (input and output PAD, power supply and ground terminal PAD) and even
Connecing circuit to be respectively arranged on the different metal level of two-layer, thus decreasing the area of integrated circuit, improve integrated level, reduce
Cost.Can reduce by more than 30% area than traditional handicraft, thus improve the competitiveness of product technology.
In addition, the connection via process of the first metal layer M1 and second metal layer M2 less demanding it is not necessary to open small size
Through hole, therefore, will not increase the complexity of manufacturing process, will not introduce unreliable factor.
In sum, in traditional single-layer metal wiring processing technology and domain structure, alum gate CMOS integrated circuit
Integrated level is low, and cost is difficult to decline.And traditional handicraft is to reach raising integrated level, during the target of reduces cost, often adopt
Sacrifice reliability to exchange for.
The processing technology of bilayer alum gate CMOS two metal wired layers of the present invention and domain structure.Combine multilamellar gold
Belong to the thinking of wiring, on the basis of not sacrificing reliability, more than 30% can be reduced than traditional manufacturing technique and domain structure
Area, improves more than 20% competitiveness, has a good application prospect.
It is understood that for those of ordinary skills, can with technology according to the present invention scheme and this
Bright design in addition equivalent or change, and all these change or replace the guarantor that all should belong to appended claims of the invention
Shield scope.
Claims (6)
1. the processing technology of alum gate CMOS two metal wired layers and domain structure are it is characterised in that described processing technology and domain
Structure includes：The first metal layer, stacking second metal layer on the first metal layer and be arranged on the first metal layer and second
Dielectric sealing coat between metal level.
2. the processing technology of alum gate CMOS two metal wired layers according to claim 1 and domain structure it is characterised in that
Described the first metal layer is set to cmos circuit articulamentum, and described second metal layer is set to pressure welding point layer.
3. the processing technology of alum gate CMOS two metal wired layers according to claim 1 and domain structure it is characterised in that
Described the first metal layer is set to cmos circuit articulamentum, and described second metal layer is set to pressure welding point and carries out MOS circuit even
Connect.
4. the processing technology of alum gate CMOS two metal wired layers according to claim 1 and domain structure it is characterised in that
Described pressure welding point is input and output PAD, power supply and ground terminal PAD.
5. the processing technology of alum gate CMOS two metal wired layers according to claim 1 and domain structure it is characterised in that
The material of described dielectric layer is isolation material or silicon nitride and silicon dioxide compound medium layer.
6. the processing technology of alum gate CMOS two metal wired layers according to claim 1 and domain structure it is characterised in that
Described dielectric sealing coat is the insulating medium layer between described the first metal layer and second metal layer, described the first metal layer
Carry out circuit with second metal layer by the through hole that chemical wet etching is dielectrically separated from dielectric layer making to be connected.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080087966A1 (en) * | 2006-10-16 | 2008-04-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102044539A (en) * | 2009-10-07 | 2011-05-04 | 富晶电子股份有限公司 | Semiconductor chip, seal ring structure and manufacturing method thereof |
| CN102832172A (en) * | 2011-06-17 | 2012-12-19 | 北大方正集团有限公司 | Low-voltage metal gate complementary metal oxide semiconductor and manufacturing method thereof |
| CN103003940A (en) * | 2009-10-12 | 2013-03-27 | 莫诺利特斯3D<sup>TM</sup>有限公司 | System comprising a semiconductor device and structure |
| CN205752106U (en) * | 2016-03-07 | 2016-11-30 | 陈军建 | The domain structure of alum gate CMOS two metal wired layers |
-
2016
- 2016-03-07 CN CN201610125636.8A patent/CN106469663A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080087966A1 (en) * | 2006-10-16 | 2008-04-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102044539A (en) * | 2009-10-07 | 2011-05-04 | 富晶电子股份有限公司 | Semiconductor chip, seal ring structure and manufacturing method thereof |
| CN103003940A (en) * | 2009-10-12 | 2013-03-27 | 莫诺利特斯3D<sup>TM</sup>有限公司 | System comprising a semiconductor device and structure |
| CN102832172A (en) * | 2011-06-17 | 2012-12-19 | 北大方正集团有限公司 | Low-voltage metal gate complementary metal oxide semiconductor and manufacturing method thereof |
| CN205752106U (en) * | 2016-03-07 | 2016-11-30 | 陈军建 | The domain structure of alum gate CMOS two metal wired layers |
Non-Patent Citations (1)
| Title |
|---|
| 郑养鉥 等: "双层金属布线硅栅CMOS门阵列电路制造工艺技术研究", 《半导体学报》 * |
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