TW201349485A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TW201349485A
TW201349485A TW102116617A TW102116617A TW201349485A TW 201349485 A TW201349485 A TW 201349485A TW 102116617 A TW102116617 A TW 102116617A TW 102116617 A TW102116617 A TW 102116617A TW 201349485 A TW201349485 A TW 201349485A
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Taiwan
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layer
columnar
eleventh
insulating film
gate
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TW102116617A
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Chinese (zh)
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Fujio Masuoka
Nozomu Harada
Hiroki Nakamura
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Unisantis Elect Singapore Pte
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A semiconductor device includes: a planar silicon layer, a first and a second pillar-shaped silicon layer formed on the planar silicon layer, a first and a second gate insulating films formed around the first and the second pillar-shaped silicon layers respectively, a first and a second gate electrodes formed around the first and the second gate insulating films respectively, a first gate wire connected to the first and second gate electrodes, a n-type diffusion layer formed on an upper portion of the first pillar-shaped silicon layer, a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a p-type diffusion layer formed on an upper portion of the second pillar-shaped silicon layer, a lower portion of the second pillar-shaped silicon layer and an upper portion of the planar silicon layer. A central line extending along the first gate wire shifts by a first predetermined value relative to a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer.

Description

半導體裝置 Semiconductor device

本發明是有關於一種半導體裝置。 The present invention relates to a semiconductor device.

半導體積體電路、其中使用金屬氧化物半導體(Metal Oxide Semiconductor，MOS)電晶體(transistor)的積體電路正趨於高積體化的方向。隨著該高積體化，MOS電晶體已微細化至奈米級(nano level)。當此種MOS電晶體的微細化發展時，漏(leak)電流的抑制變得困難，從而會因確保必要電流量的要求而難以使電路的佔有面積減少。為了解決此種問題，提出有環繞閘極電晶體(Surrounding Gate Transistor，以下稱作「SGT」)，其採用下述結構，即：相對於基板而沿垂直方向配置源極(source)、閘極(gate)、汲極(drain)，且閘極電極圍繞柱狀半導體層(例如參照專利文獻1、專利文獻2、專利文獻3)。 A semiconductor integrated circuit in which an integrated circuit using a metal oxide semiconductor (MOS) transistor is tending to be highly integrated. With this high integration, the MOS transistor has been miniaturized to the nano level. When the miniaturization of such a MOS transistor progresses, the suppression of the leakage current becomes difficult, and it is difficult to reduce the occupied area of the circuit by securing the required amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as "SGT") has been proposed which has a structure in which a source and a gate are arranged in a vertical direction with respect to a substrate. (gate), drain, and the gate electrode surrounds the columnar semiconductor layer (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

而且，提出有下述結構：使用上述SGT來構成互補金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，CMOS)反相器(inverter)，將n型SGT與p型SGT配置於直線上，使用位於矽(silicon)柱底部的擴散層來作為反相器的輸出端(例如參照專利文獻4)。於該結構中揭示出：於元件形成區域的表 面，形成有與包含雜質的p、n區域歐姆(ohmic)接合的連接區域，該連接區域是於n型SGT與p型SGT的外側，與輸出信號用通孔(via)電性連接。 Further, a configuration has been proposed in which a complementary metal-oxide-semiconductor (CMOS) inverter is formed using the SGT described above, and an n-type SGT and a p-type SGT are arranged on a straight line, and the use is located. A diffusion layer at the bottom of the silicon column is used as an output terminal of the inverter (for example, see Patent Document 4). Revealed in the structure: a table of element formation regions The surface is formed with a connection region ohmicly bonded to the p and n regions including the impurity, and the connection region is external to the n-type SGT and the p-type SGT, and is electrically connected to the output signal through via.

根據該技術，閘極配線的寬度長於元件形成區域的寬度，因此無法確定連接區域的形成方法。 According to this technique, the width of the gate wiring is longer than the width of the element formation region, and thus the method of forming the connection region cannot be determined.

於該技術中，當連接區域由矽化物(silicide)形成時，必須於進行矽化物化時使用保護膜，並且於閘極配線的周圍形成側牆(side wall)以防止短路。 In this technique, when the connection region is formed of silicide, it is necessary to use a protective film at the time of performing the mash formation, and a side wall is formed around the gate wiring to prevent a short circuit.

因此，若欲在位於閘極配線的相向的兩邊周圍的元件形成區域形成矽化物，則必須使元件形成區域的寬度寬於閘極配線的寬度與側牆寬度的2倍長度之和。此時，元件形成區域所佔的面積變大。 Therefore, if a germanide is to be formed in the element formation region around the opposite sides of the gate wiring, the width of the element formation region must be made wider than the sum of the width of the gate wiring and the width of the side wall. At this time, the area occupied by the element formation region becomes large.

而且，提出有使用6個SGT的靜態隨機存取記憶體(Static Random Access Memory，SRAM)(例如參照專利文獻5)。此處，於元件形成區域形成有矽化物，上述元件形成區域使元件形成區域的寬度長於閘極配線的寬度與側牆寬度的2倍長度之和，且該元件形成區域存在於閘極配線的相向的兩邊的周圍。此時，元件形成區域所佔的面積變大。 Further, a static random access memory (SRAM) using six SGTs has been proposed (for example, see Patent Document 5). Here, a germanide is formed in the element formation region, and the element formation region has a width of the element formation region longer than a sum of a width of the gate wiring and a width of the sidewall spacer, and the element formation region exists in the gate wiring. Around the opposite sides. At this time, the area occupied by the element formation region becomes large.

現有技術文獻 Prior art literature 專利文獻 Patent literature

專利文獻1：日本專利特開平2-71556號公報 Patent Document 1: Japanese Patent Laid-Open No. 2-71556

專利文獻2：日本專利特開平2-188966號公報 Patent Document 2: Japanese Patent Laid-Open No. Hei 2-188966

專利文獻3：日本專利特開平3-145761號公報 Patent Document 3: Japanese Patent Laid-Open No. Hei 3-145761

專利文獻4：日本專利特開2008-205168號公報 Patent Document 4: Japanese Patent Laid-Open Publication No. 2008-205168

專利文獻5：國際公開第2009/095998號 Patent Document 5: International Publication No. 2009/095998

本發明的目的在於提供一種半導體裝置，其元件形成區域所佔的面積小，且使用CMOS SGT。 An object of the present invention is to provide a semiconductor device in which an area occupied by an element formation region is small and a CMOS SGT is used.

本發明的第1觀點的半導體裝置的特徵在於包括：第1平面狀矽層，形成於基板上；第1以及第2柱狀矽層，形成於上述第1平面狀矽層上；第1閘極絕緣膜，形成於上述第1柱狀矽層的周圍；第1閘極電極，形成於上述第1閘極絕緣膜的周圍；第2閘極絕緣膜，形成於上述第2柱狀矽層的周圍；第2閘極電極，形成於上述第2閘極絕緣膜的周圍；第1閘極配線，連接於上述第1以及上述第2閘極電極；第1第二導電型擴散層，形成於上述第1柱狀矽層的上部；第2第二導電型擴散層，遍及上述第1柱狀矽層的下部與上述平面狀矽層的上部而形成；第1第一導電型擴散層，形成於上述第2柱狀矽層的上部；以及第2第一導電型擴散層，遍及上述第2柱狀矽層的下部與上述平面狀矽層的上部而形成，沿著上述第1閘極配線延伸的中心線相對於連結上述第1柱 狀矽層的中心與上述第2柱狀矽層的中心的線而偏移第1規定量。 A semiconductor device according to a first aspect of the present invention includes: a first planar germanium layer formed on a substrate; and first and second columnar germanium layers formed on the first planar germanium layer; the first gate a pole insulating film is formed around the first columnar layer; a first gate electrode is formed around the first gate insulating film; and a second gate insulating film is formed on the second columnar layer The second gate electrode is formed around the second gate insulating film; the first gate wiring is connected to the first and second gate electrodes; and the first second conductivity type diffusion layer is formed. The second conductive diffusion layer is formed over the lower portion of the first columnar layer and the upper portion of the planar layer; the first first conductivity type diffusion layer is formed on the upper portion of the first columnar layer; Formed on an upper portion of the second columnar layer; and a second first conductivity type diffusion layer formed over a lower portion of the second columnar layer and an upper portion of the planar layer, along the first gate The center line of the wiring extension is connected to the first column The center of the layer and the line of the center of the second columnar layer are shifted by the first predetermined amount.

較佳的是，上述半導體裝置包括：第1絕緣膜側牆，形成於上述第1閘極配線的側壁；以及矽化物，遍及上述第2第二導電型擴散層上與上述第2第一導電型擴散層上而形成，上述第1規定量大於下述值，該值是自第1絕緣膜側牆的寬度與上述第1閘極配線的寬度的一半長度之和，減去上述第1平面狀矽層的寬度的一半長度所得的值。 Preferably, the semiconductor device includes: a first insulating film spacer formed on a sidewall of the first gate wiring; and a telluride over the second second conductive diffusion layer and the second first conductive The first diffusion amount is formed by the first predetermined amount being greater than a sum of a width from a side wall of the first insulating film and a half of a width of the first gate wiring, and subtracting the first plane The value obtained by half the length of the layer of the layer.

較佳的是，上述第1規定量大於下述值，該值是自上述第1平面狀矽層的寬度，減去第1絕緣膜側牆的寬度與上述第1閘極配線的寬度的一半長度之和所得的值。 Preferably, the first predetermined amount is larger than a value obtained by subtracting a width of the first insulating film sidewall and a width of the first gate wiring from a width of the first planar germanium layer. The resulting value of the sum of the lengths.

較佳的是，上述半導體裝置包括：第2絕緣膜側牆，遍及上述第1柱狀矽層的上部側壁與上述第1閘極電極上部而形成；第3絕緣膜側牆，遍及上述第2柱狀矽層的上部側壁與上述第2閘極電極上部而形成；第1絕緣膜側牆，遍及上述第2以及上述第3絕緣膜側牆、上述第1以及上述第2閘極電極與上述第1閘極配線的側壁而形成；以及矽化物，遍及上述第1第二導電型擴散層上與上述第1第一導電型擴散層上而形成。 Preferably, the semiconductor device includes a second insulating film spacer formed over the upper sidewall of the first columnar layer and the first gate electrode, and a third insulating film sidewall extending over the second layer The upper sidewall of the columnar layer is formed on the upper portion of the second gate electrode; the first insulating film spacer extends over the second and third insulating film spacers, the first and second gate electrodes, and The sidewall of the first gate wiring is formed; and the germanide is formed over the first second conductivity type diffusion layer and the first first conductivity type diffusion layer.

而且，本發明的第2觀點的半導體裝置的特徵在於包括： 第11平面狀矽層，在包含於基板上設定的行及列的座標的第一行，以沿該行方向延伸的方式而形成；第11柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第一列；第11閘極絕緣膜，形成於上述第11柱狀矽層的周圍；第11閘極電極，形成於上述第11閘極絕緣膜的周圍；第11第二導電型擴散層，形成於上述第11柱狀矽層的上部；第12第二導電型擴散層，遍及上述第11柱狀矽層的下部與上述第11平面狀矽層的上部而形成；第12柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第二列；第12閘極絕緣膜，形成於上述第12柱狀矽層的周圍；第12閘極電極，形成於上述第12閘極絕緣膜的周圍；第11第一導電型擴散層，形成於上述第12柱狀矽層的上部；第12第一導電型擴散層，遍及上述第12柱狀矽層的下部與上述第11平面狀矽層的上部而形成；第13柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第三列；第13閘極絕緣膜，形成於上述第13柱狀矽層的周圍；第13閘極電極，形成於上述第13閘極絕緣膜的周圍；第13第二導電型擴散層，形成於上述第13柱狀矽層的上部；第14第二導電型擴散層，遍及上述第13柱狀矽層的下部與 上述第11平面狀矽層的上部而形成；第11閘極配線，連接於上述第11以及上述第12閘極電極；第21平面狀矽層，形成於在上述基板上設定的座標的第二行；第21柱狀矽層，於上述第21平面狀矽層上，形成於上述座標的第二行第一列；第21閘極絕緣膜，形成於上述第21柱狀矽層的周圍；第21閘極電極，形成於上述第21閘極絕緣膜的周圍；第21第二導電型擴散層，形成於上述第21柱狀矽層的上部；第22第二導電型擴散層，遍及上述第21柱狀矽層的下部與上述第21平面狀矽層的上部而形成；第22柱狀矽層，在上述第21平面狀矽層上，形成於上述座標的第二行第二列；第22閘極絕緣膜，形成於上述第22柱狀矽層的周圍；第22閘極電極，形成於上述第22閘極絕緣膜的周圍；第21第一導電型擴散層，形成於上述第22柱狀矽層的上部；第22第一導電型擴散層，遍及上述第22柱狀矽層的下部與上述第21平面狀矽層的上部而形成；第23柱狀矽層，在上述第21平面狀矽層上，形成於上述座標的第二行第三列；第23閘極絕緣膜，形成於上述第23柱狀矽層的周圍；第23閘極電極，形成於上述第23閘極絕緣膜的周圍；第23第二導電型擴散層，形成於上述第23柱狀矽層的上部； 第24第二導電型擴散層，遍及上述第23柱狀矽層的下部與上述第21平面狀矽層的上部而形成；以及第21閘極配線，連接於上述第22以及上述第23閘極電極，沿著上述第11閘極配線延伸的中心線相對於連結上述第11柱狀矽層的中心與上述第12柱狀矽層的中心的線而在上述座標的第二行中，沿該行方向偏移第11規定量，沿著上述第21閘極配線延伸的中心線相對於連結上述第22柱狀矽層的中心與上述第23柱狀矽層的中心的線而在上述座標的第一行中，沿該行方向偏移第11規定量。 Further, a semiconductor device according to a second aspect of the present invention is characterized by comprising: The eleventh planar crucible layer is formed to extend in the row direction in the first row of the coordinates of the rows and columns set on the substrate, and the eleventh columnar crucible layer in the eleventh planar crucible layer The first gate row and the first column are formed; the eleventh gate insulating film is formed around the eleventh columnar layer; and the eleventh gate electrode is formed around the eleventh gate insulating film a 11th second conductivity type diffusion layer formed on an upper portion of the eleventh columnar layer; and a twelfth second conductivity type diffusion layer over the lower portion of the eleventh columnar layer and the eleventh planar layer Formed on the upper portion; the twelfth columnar layer is formed on the eleventh planar layer of the first row and the second column of the coordinates; and the twelfth gate insulating film is formed on the twelfth columnar layer a 12th gate electrode formed around the 12th gate insulating film; a 11th first conductivity type diffusion layer formed on an upper portion of the 12th columnar layer; and a 12th first conductivity type diffusion layer; Formed over the lower portion of the twelfth columnar layer and the upper portion of the eleventh planar layer; the thirteenth column The enamel layer is formed on the eleventh planar ruthenium layer in the first row and the third column of the coordinates; the thirteenth gate insulating film is formed around the thirteenth columnar ruthenium layer; and the thirteenth gate electrode Formed around the thirteenth gate insulating film; the thirteenth second conductivity type diffusion layer is formed on the upper portion of the thirteenth columnar layer; and the thirteenth second conductivity type diffusion layer is spread over the thirteenth columnar layer Lower part The eleventh planar germanium layer is formed on the upper portion; the eleventh gate wiring is connected to the eleventh and the twelfth gate electrodes; and the twenty-first planar germanium layer is formed on the second set of coordinates on the substrate. a 21st columnar layer formed on the 21st planar layer of the second row and the first row of the coordinates; and a 21st gate insulating film formed around the 21st columnar layer; a 21st gate electrode is formed around the 21st gate insulating film; a 21st second conductivity type diffusion layer is formed on an upper portion of the 21st columnar layer; and a 22nd second conductivity type diffusion layer is provided in the above a lower portion of the 21st columnar layer and an upper portion of the 21st planar layer; the 22nd columnar layer is formed on the 21st planar layer of the second row and the second column of the coordinates; a 22nd gate insulating film is formed around the 22nd columnar layer; a 22nd gate electrode is formed around the 22nd gate insulating film; and a 21st first conductivity type diffusion layer is formed in the above 22 upper portion of the columnar layer; the 22nd first conductivity type diffusion layer, extending over the 22nd columnar layer a lower portion is formed on an upper portion of the 21st planar ruthenium layer; and a 23rd columnar ruthenium layer is formed on the 21st planar ruthenium layer in the second row and the third column of the coordinates; the 23rd gate insulating film And formed on the periphery of the 23rd columnar layer; the 23rd gate electrode is formed around the 23rd gate insulating film; and the 23rd second conductivity type diffusion layer is formed in the 23rd columnar layer Upper part a 24th second conductivity type diffusion layer is formed over the lower portion of the 23rd columnar layer and the upper portion of the 21st planar layer; and the 21st gate line is connected to the 22nd and the 23rd gate An electrode, along a center line extending along the eleventh gate line, is along a line connecting a center of the eleventh columnar layer and a center of the twelfth columnar layer, in the second row of the coordinate The row direction shift is 11th predetermined amount, and the center line extending along the 21st gate wiring is at the coordinates of the center line connecting the center of the 22nd columnar layer and the center of the 23rd columnar layer In the first line, the eleventh predetermined amount is shifted in the row direction.

較佳的是，上述半導體裝置包括：第11絕緣膜側牆，形成於上述第11閘極配線的側壁；以及矽化物，遍及上述第12第二導電型擴散層上與上述第12第一導電型擴散層上而形成，上述第11規定量大於下述值，該值是自第11絕緣膜側牆的寬度與上述第11閘極配線的寬度的一半長度之和，減去上述第11平面狀矽層的寬度的一半長度所得的值。 Preferably, the semiconductor device includes: a first insulating film spacer, a sidewall formed on the eleventh gate wiring; and a telluride over the twelfth second conductive diffusion layer and the twelfth first conductive The eleventh predetermined amount is formed by a value larger than a sum of a width from a side wall of the eleventh insulating film and a half of a width of the eleventh gate wiring, and the eleventh plane is subtracted from the eleventh plane. The value obtained by half the length of the layer of the layer.

較佳的是，遍及上述第11柱狀矽層與上述第12柱狀矽層之間、及上述第21柱狀矽層與上述第22柱狀矽層之間，而形成有第11接觸部，上述第11閘極配線經由上述第11接觸部而電性連接於上述第21平面狀矽層。 Preferably, the eleventh contact portion is formed between the eleventh columnar layer and the second columnar layer and between the 21st columnar layer and the 22nd columnar layer The eleventh gate wiring is electrically connected to the 21st planar germanium layer via the eleventh contact portion.

較佳的是，上述第11規定量大於下述值，該值是自上 述第11平面狀矽層的寬度，減去第11絕緣膜側牆的寬度與上述第11閘極配線的寬度的一半長度之和所得的值。 Preferably, the eleventh predetermined amount is greater than the following value, the value is from the top The width of the eleventh planar tantalum layer is obtained by subtracting the sum of the width of the side wall of the eleventh insulating film and the half length of the width of the eleventh gate wiring.

根據本發明，能夠提供一種半導體裝置，其元件形成區域所佔的面積小，且使用CMOS SGT。 According to the present invention, it is possible to provide a semiconductor device in which the area occupied by the element formation region is small and a CMOS SGT is used.

101、103、104、106、301‧‧‧n型SGT 101, 103, 104, 106, 301‧‧‧n type SGT

102、105、302‧‧‧p型SGT 102, 105, 302‧‧‧p type SGT

107‧‧‧第11閘極電極 107‧‧‧11th gate electrode

108‧‧‧第12閘極電極 108‧‧‧12th gate electrode

109‧‧‧第13閘極電極 109‧‧‧13th gate electrode

110‧‧‧第21閘極電極 110‧‧‧21st gate electrode

111‧‧‧第22閘極電極 111‧‧‧22nd gate electrode

112‧‧‧第23閘極電極 112‧‧‧23rd gate electrode

113‧‧‧第11閘極配線 113‧‧‧11th gate wiring

114、115、306‧‧‧閘極配線 114, 115, 306‧‧‧ gate wiring

116‧‧‧第21閘極配線 116‧‧‧21st gate wiring

117、118、119、120、234、235、236、237、238、239、240、241、242、243、308、510、511、512、513、514‧‧‧矽化物 117, 118, 119, 120, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 308, 510, 511, 512, 513, 514 ‧ ‧ 矽

121‧‧‧第11平面狀矽層 121‧‧‧11th planar layer

122‧‧‧第21平面狀矽層 122‧‧‧21st planar layer

123、125、126、257、258、259、260、261、262、520、521、522、523‧‧‧接觸部 123, 125, 126, 257, 258, 259, 260, 261, 262, 520, 521, 522, 523 ‧ ‧ contact

124‧‧‧第11接觸部 124‧‧‧11th Contact

127‧‧‧第11絕緣膜側牆 127‧‧‧11th insulating film side wall

128、129、130‧‧‧絕緣膜側牆 128, 129, 130‧‧ ‧ insulating film side wall

201、501‧‧‧基板 201, 501‧‧‧ substrate

202‧‧‧第12n型擴散層 202‧‧‧12n-type diffusion layer

203‧‧‧第12p型擴散層 203‧‧‧12p type diffusion layer

204‧‧‧第14n型擴散層 204‧‧‧14n type diffusion layer

205‧‧‧第22n型擴散層 205‧‧‧22n-type diffusion layer

206‧‧‧第22p型擴散層 206‧‧‧22p type diffusion layer

207‧‧‧第24n型擴散層 207‧‧‧Type 24n diffusion layer

208‧‧‧第11柱狀矽層 208‧‧‧11th columnar layer

209‧‧‧第12柱狀矽層 209‧‧‧12th columnar layer

210‧‧‧第13柱狀矽層 210‧‧‧13th columnar layer

211‧‧‧第21柱狀矽層 211‧‧‧21st columnar layer

212‧‧‧第22柱狀矽層 212‧‧‧22nd columnar layer

213‧‧‧第23柱狀矽層 213‧‧‧23rd columnar layer

214、508‧‧‧元件分離膜 214, 508‧‧‧ component separation membrane

215‧‧‧第11閘極絕緣膜、第12閘極絕緣膜 215‧‧‧11th gate insulating film, 12th gate insulating film

216、218、220、222、507‧‧‧金屬膜 216, 218, 220, 222, 507‧‧‧ metal film

217‧‧‧第13閘極絕緣膜 217‧‧‧13th gate insulating film

219‧‧‧第21閘極絕緣膜 219‧‧‧21st gate insulating film

221‧‧‧第22閘極絕緣膜、第23閘極絕緣膜 221‧‧‧22nd gate insulating film, 23rd gate insulating film

223、224、225、226、509‧‧‧多晶矽 223, 224, 225, 226, 509‧‧ ‧ polysilicon

227‧‧‧第11n型擴散層 227‧‧‧11n-type diffusion layer

228‧‧‧第11p型擴散層 228‧‧‧11p diffusion layer

229‧‧‧第13n型擴散層 229‧‧‧13n-type diffusion layer

230‧‧‧第21n型擴散層 230‧‧‧21n type diffusion layer

231‧‧‧第21p型擴散層 231‧‧‧21p diffusion layer

232‧‧‧第23n型擴散層 232‧‧‧23n type diffusion layer

244、246、248、250、252、254、516、518‧‧‧氧化膜 244, 246, 248, 250, 252, 254, 516, 518‧‧ ‧ oxide film

245、247、249、251、253、255、517、519‧‧‧氮化膜 245, 247, 249, 251, 253, 255, 517, 519‧‧ ‧ nitride film

256、515‧‧‧層間絕緣膜 256, 515‧‧‧ interlayer insulating film

303‧‧‧第1閘極電極 303‧‧‧1st gate electrode

304‧‧‧第2閘極電極 304‧‧‧2nd gate electrode

305‧‧‧第1閘極配線 305‧‧‧1st gate wiring

307‧‧‧第1絕緣膜側牆 307‧‧‧1st insulating film side wall

309‧‧‧第1平面狀矽層 309‧‧‧1st planar layer

502‧‧‧第2n型擴散層 502‧‧‧2n type diffusion layer

503‧‧‧第2p型擴散層 503‧‧‧2p diffusion layer

504‧‧‧第1柱狀矽層 504‧‧‧1st columnar layer

505‧‧‧第2柱狀矽層 505‧‧‧2nd columnar layer

506‧‧‧第1閘極絕緣膜、第2閘極絕緣膜 506‧‧‧1st gate insulating film, 2nd gate insulating film

524‧‧‧第1n型擴散層 524‧‧‧1n type diffusion layer

525‧‧‧第1p型擴散層 525‧‧‧1p type diffusion layer

圖1的(A)是本發明的實施方式的半導體裝置的平面圖，(B)是(A)的X3-X3'線上的剖面圖，(C)是(A)的Y3-Y3'線上的剖面圖，(D)是(A)的Y4-Y4'線上的剖面圖。 1(A) is a plan view of a semiconductor device according to an embodiment of the present invention, (B) is a cross-sectional view taken along line X3-X3' of (A), and (C) is a cross-section taken along line Y3-Y3' of (A). Fig. (D) is a cross-sectional view taken along line Y4-Y4' of (A).

圖2的(A)是本發明的實施方式的半導體裝置的平面圖，(B)是(A)的X1-X1'線上的剖面圖，(C)是(A)的Y1-Y1'線上的剖面圖。 2(A) is a plan view of a semiconductor device according to an embodiment of the present invention, (B) is a cross-sectional view taken along line X1-X1' of (A), and (C) is a cross-section taken along line Y1-Y1' of (A) Figure.

圖3的(A)是本發明的實施方式的半導體裝置的平面圖，(B)是(A)的X2-X2'線上的剖面圖，(C)是(A)的Y2-Y2'線上的剖面圖。 3(A) is a plan view of a semiconductor device according to an embodiment of the present invention, (B) is a cross-sectional view taken along line X2-X2' of (A), and (C) is a cross-section taken along line Y2-Y2' of (A). Figure.

如圖1的(A)、(B)、(C)、(D)所示，本發明的實施方式的半導體裝置具有：第1平面狀矽層309，形成於基板501上；以及第1柱狀矽層504及第2柱狀矽層505，形成於第1平面狀矽層309上。 As shown in (A), (B), (C), and (D) of FIG. 1, a semiconductor device according to an embodiment of the present invention includes a first planar germanium layer 309 formed on a substrate 501, and a first pillar The crucible layer 504 and the second columnar crucible layer 505 are formed on the first planar crucible layer 309.

本實施方式的半導體裝置具有：第1閘極絕緣膜506， 形成於第1柱狀矽層504的周圍；以及第1閘極電極303，形成於第1閘極絕緣膜506的周圍。 The semiconductor device of the present embodiment includes a first gate insulating film 506, The first gate electrode layer 303 is formed around the first columnar layer 504, and the first gate electrode 303 is formed around the first gate insulating film 506.

本實施方式的半導體裝置具有：第2閘極絕緣膜506，形成於第2柱狀矽層505的周圍；第2閘極電極304，形成於第2閘極絕緣膜506的周圍；第1閘極配線305，連接於第1閘極電極303以及第2閘極電極304；第1n型擴散層524，形成於第1柱狀矽層504的上部；第2n型擴散層502，遍及第1柱狀矽層504的下部與平面狀矽層309的上部而形成；第1p型擴散層525，形成於第2柱狀矽層505的上部；以及第2p型擴散層503，遍及第2柱狀矽層505的下部與平面狀矽層309的上部而形成。 The semiconductor device of the present embodiment includes a second gate insulating film 506 formed around the second columnar layer 505, and a second gate electrode 304 formed around the second gate insulating film 506; the first gate The pole wiring 305 is connected to the first gate electrode 303 and the second gate electrode 304; the first n-type diffusion layer 524 is formed on the upper portion of the first columnar layer 504; and the second n-type diffusion layer 502 is spread over the first column. The lower portion of the layer 504 and the upper portion of the planar layer 309 are formed; the first p-type diffusion layer 525 is formed on the upper portion of the second columnar layer 505; and the second p-type diffusion layer 503 is formed over the second columnar layer 矽The lower portion of the layer 505 is formed with the upper portion of the planar tantalum layer 309.

在本實施方式的半導體裝置中，沿著第1閘極配線305延伸的中心線，更詳細而言，沿著第1閘極配線305而沿水平方向延伸、並且通過該第1閘極配線305的寬度方向的中心的中心線，相對於連結第1柱狀矽層504的中心與第2柱狀矽層505的中心的線而偏移第1規定量。 In the semiconductor device of the present embodiment, the center line extending along the first gate wiring 305 extends in the horizontal direction along the first gate wiring 305 and passes through the first gate wiring 305. The center line of the center in the width direction is shifted by the first predetermined amount with respect to the line connecting the center of the first columnar layer 504 and the center of the second columnar layer 505.

此處，對於閘極絕緣膜506，可使用氧化膜、氮化膜、氮氧化膜、高介電質膜等被用於半導體的絕緣膜來作為材料。 Here, as the gate insulating film 506, an insulating film used for a semiconductor such as an oxide film, a nitride film, an oxynitride film, or a high dielectric film can be used as the material.

根據本實施方式的半導體裝置，藉由上述特徵，可獲得下述效果。 According to the semiconductor device of the present embodiment, the above effects can be obtained by the above features.

即，可於平面狀矽層309上形成矽化物308，以將n型SGT的第2n型擴散層502與p型SGT的第2p型擴散層503電性連接，上述平面狀矽層309是存在於第1閘極配線305的第1 邊周圍的元件形成區域。因此，與在存在於閘極配線的相向的第1及第2邊周圍的元件形成區域中形成有矽化物的情況相比，可縮窄作為元件形成區域的平面狀矽層309的寬度。 That is, the germanide 308 can be formed on the planar germanium layer 309 to electrically connect the second n-type diffusion layer 502 of the n-type SGT and the second p-type diffusion layer 503 of the p-type SGT, and the planar germanium layer 309 is present. The first of the first gate wiring 305 The components around the sides form an area. Therefore, the width of the planar germanium layer 309 as the element formation region can be narrowed compared to the case where the germanium compound is formed in the element formation region around the first and second sides facing the gate wiring.

而且，由於作為元件形成區域的平面狀矽層的寬度短，因此可實現高積體的CMOS SGT反相器。 Further, since the width of the planar germanium layer as the element formation region is short, a highly integrated CMOS SGT inverter can be realized.

本實施方式的半導體裝置中，如圖1的(A)、(B)、(C)、(D)所示，第1柱狀矽層504形成n型SGT301，並且第2柱狀矽層505形成p型SGT302。 In the semiconductor device of the present embodiment, as shown in FIGS. 1A (A), (B), (C), and (D), the first columnar layer 504 forms an n-type SGT 301, and the second columnar layer 505 is formed. A p-type SGT302 is formed.

本實施方式的半導體裝置具有：第1絕緣膜側牆307，形成於第1閘極配線305的側壁上；以及矽化物308，遍及第2n型擴散層502上與第2p型擴散層503上而形成。 The semiconductor device of the present embodiment includes a first insulating film spacer 307 formed on the sidewall of the first gate wiring 305, and a germanide 308 over the second n-type diffusion layer 502 and the second p-type diffusion layer 503. form.

而且，第1規定量大於下述值，該值是自第1絕緣膜側牆307的寬度與第1閘極配線305的寬度的一半長度之和，減去第1平面狀矽層309的寬度的一半長度所得的值。 Further, the first predetermined amount is larger than the sum of the width from the width of the first insulating film side wall 307 and the half of the width of the first gate wiring 305, and the width of the first planar tantalum layer 309 is subtracted. The resulting value of half the length.

而且，第1規定量大於下述值，該值是自第1平面狀矽層309的寬度的一半長度，減去第1絕緣膜側牆307的寬度與第1閘極配線305的寬度的一半長度之和所得的值。 Further, the first predetermined amount is larger than a value which is half the width of the first planar tantalum layer 309, and the width of the first insulating film spacer 307 is subtracted from the width of the first gate wiring 305. The resulting value of the sum of the lengths.

根據本實施方式的半導體裝置，藉由上述特徵，可在平面狀矽層上形成矽化物，該平面狀矽層是形成於閘極配線的第1邊周圍的元件形成區域。 According to the semiconductor device of the present embodiment, the germanium compound can be formed on the planar germanium layer by the above-described feature, and the planar germanium layer is an element formation region formed around the first side of the gate wiring.

本實施方式的半導體裝置具有：第1閘極電極303，包含積層結構，該積層結構包含形成於第1閘極絕緣膜506周圍的 金屬膜507以及多晶矽509；以及第2閘極電極304，包含積層結構，該積層結構包含形成於第2閘極絕緣膜506周圍的金屬膜507以及多晶矽509。 The semiconductor device of the present embodiment includes the first gate electrode 303 and a laminated structure including the periphery of the first gate insulating film 506. The metal film 507 and the polysilicon 509 and the second gate electrode 304 include a laminated structure including a metal film 507 and a polysilicon 509 formed around the second gate insulating film 506.

此處，閘極既可僅由金屬膜形成，也可由矽化物形成。另外，對於金屬膜，可使用鈦、氮化鈦、鉭、氮化鉭等被用於半導體的金屬。 Here, the gate electrode may be formed only of a metal film or a germanide. Further, as the metal film, a metal used for a semiconductor such as titanium, titanium nitride, tantalum or tantalum nitride can be used.

本實施方式的半導體裝置中，以連接於第1閘極電極303的方式而形成有閘極配線306。 In the semiconductor device of the present embodiment, the gate wiring 306 is formed to be connected to the first gate electrode 303.

本實施方式的半導體裝置具有：第2絕緣膜側牆，包含遍及第1柱狀矽層504的上部側壁與第1閘極電極303上部而形成的氧化膜516及氮化膜517；第3絕緣膜側牆，包含遍及第2柱狀矽層505的上部側壁與第2閘極電極304上部而形成的氧化膜518及氮化膜519；第1絕緣膜側牆307，遍及第2及第3絕緣膜側牆、第1閘極電極303及第2閘極電極304、第1閘極配線305與閘極配線306的側壁而形成；以及矽化物511、513，遍及第1n型擴散層524上與第1p型擴散層525上而形成。 The semiconductor device of the present embodiment includes a second insulating film spacer, and includes an oxide film 516 and a nitride film 517 formed over the upper sidewall of the first columnar layer 504 and the upper portion of the first gate electrode 303; and the third insulating layer The film side wall includes an oxide film 518 and a nitride film 519 formed over the upper side wall of the second columnar layer 505 and the upper portion of the second gate electrode 304, and the first insulating film side wall 307 throughout the second and third layers. The insulating film spacer, the first gate electrode 303 and the second gate electrode 304, the first gate wiring 305 and the sidewall of the gate wiring 306 are formed, and the germanium 511 and 513 are formed over the first n-type diffusion layer 524. It is formed on the first p-type diffusion layer 525.

本實施方式的半導體裝置中，第2閘極電極304的上部是由第3絕緣膜側牆518、519予以覆蓋，側壁是由第1絕緣膜側牆307予以覆蓋。第3絕緣膜側牆518、519的側壁是由第1絕緣膜側牆307予以覆蓋。因此，當於平面狀矽層309上部的擴散層上形成的接觸部523向第2閘極電極304側偏移時，可防止第2閘極電極304與接觸部523彼此短路。 In the semiconductor device of the present embodiment, the upper portion of the second gate electrode 304 is covered by the third insulating film spacers 518 and 519, and the sidewalls are covered by the first insulating film spacer 307. The side walls of the third insulating film side walls 518, 519 are covered by the first insulating film side wall 307. Therefore, when the contact portion 523 formed on the diffusion layer on the upper portion of the planar tantalum layer 309 is shifted toward the second gate electrode 304 side, the second gate electrode 304 and the contact portion 523 can be prevented from being short-circuited with each other.

而且，於閘極配線306上形成有矽化物510，於第1閘極配線305上形成有矽化物512。而且，分別於第2p型擴散層503上形成有矽化物514。而且，於矽化物510上形成有接觸部520，於矽化物511上形成有接觸部521，於矽化物513上形成有接觸部522，於矽化物514上形成有接觸部523。 Further, a germanide 510 is formed on the gate wiring 306, and a germanide 512 is formed on the first gate wiring 305. Further, a telluride 514 is formed on the second p-type diffusion layer 503. Further, a contact portion 520 is formed on the germanide 510, a contact portion 521 is formed on the germanide 511, a contact portion 522 is formed on the germanide 513, and a contact portion 523 is formed on the germanide 514.

而且，分別於第1平面狀矽層309的周圍形成有元件分離膜508，於n型SGT301、p型SGT302的周圍形成有層間絕緣膜515。 Further, an element isolation film 508 is formed around the first planar germanium layer 309, and an interlayer insulating film 515 is formed around the n-type SGT 301 and the p-type SGT 302.

其次，圖2的(A)、(B)、(C)以及圖3的(A)、(B)、(C)表示將本實施方式的半導體裝置適用於SRAM時的結構。 Next, (A), (B), and (C) of FIG. 2 and (A), (B), and (C) of FIG. 3 show a configuration in which the semiconductor device of the present embodiment is applied to an SRAM.

如圖2的(A)、(B)、(C)以及圖3的(A)、(B)、(C)所示，本實施方式的半導體裝置具有：第11平面狀矽層121，在包含於基板201上設定的行及列的座標的第一行，沿行方向延伸；第11柱狀矽層208，在第11平面狀矽層121上，形成於基板201上的座標的第一行第一列；第11閘極絕緣膜215，形成於第11柱狀矽層208的周圍；以及第11閘極電極107，形成於第11閘極絕緣膜215的周圍。 As shown in (A), (B), and (C) of FIG. 2, and (A), (B), and (C) of FIG. 3, the semiconductor device of the present embodiment has the eleventh planar germanium layer 121. The first row of the coordinates included in the row and column set on the substrate 201 extends in the row direction; the eleventh columnar layer 208 is formed on the eleventh planar layer 121, and the first of the coordinates formed on the substrate 201 The first column is arranged; the eleventh gate insulating film 215 is formed around the eleventh columnar layer 208; and the eleventh gate electrode 107 is formed around the eleventh gate insulating film 215.

本實施方式的半導體裝置更具有：n型SGT101，包含第11n型擴散層227及第12n型擴散層202，上述第11n型擴散層227形成於第11柱狀矽層208的上部，上述第12n型擴散層202形成於第11柱狀矽層208的下部與第11平面狀矽層121的上部；第12柱狀矽層209，在第11平面狀矽層121上，形成於基板 201上的座標的第一行第二列；第12閘極絕緣膜215，形成於第12柱狀矽層209的周圍；以及第12閘極電極108，形成於第12閘極絕緣膜215的周圍。 The semiconductor device of the present embodiment further includes an n-type SGT 101 including an 11n-type diffusion layer 227 and a 12n-type diffusion layer 202. The 11th-type diffusion layer 227 is formed on an upper portion of the 11th columnar layer 208, and the 12th The diffusion layer 202 is formed on the lower portion of the eleventh columnar layer 208 and the upper portion of the eleventh planar layer 121, and the second columnar layer 209 is formed on the substrate on the eleventh planar layer 121. a first row and a second column of coordinates on 201; a 12th gate insulating film 215 formed around the 12th columnar layer 209; and a 12th gate electrode 108 formed on the 12th gate insulating film 215 around.

本實施方式的半導體裝置更具有：p型SGT102，包含第11p型擴散層228及第12p型擴散層203，上述第11p型擴散層228形成於第12柱狀矽層209的上部，上述第12p型擴散層203形成於第12柱狀矽層209的下部與第11平面狀矽層121的上部；第13柱狀矽層210，在第11平面狀矽層121上，形成於基板201上的座標的第一行第三列；第13閘極絕緣膜217，形成於第13柱狀矽層210的周圍；以及第13閘極電極109，形成於第13閘極絕緣膜217的周圍。 The semiconductor device of the present embodiment further includes a p-type SGT 102 including an 11th p-type diffusion layer 228 and a twelfth p-type diffusion layer 203, and the 11th p-type diffusion layer 228 is formed on an upper portion of the twelfth columnar layer 209, and the 12th p The type diffusion layer 203 is formed on the lower portion of the twelfth columnar layer 209 and the upper portion of the eleventh planar layer 121; and the thirteenth columnar layer 210 is formed on the substrate 201 on the eleventh planar layer 121. The first row and the third column of the coordinates; the thirteenth gate insulating film 217 is formed around the thirteenth columnar layer 210; and the thirteenth gate electrode 109 is formed around the thirteenth gate insulating film 217.

本實施方式的半導體裝置更具有：n型SGT103，包含第13n型擴散層229及第14n型擴散層204，上述第13n型擴散層229形成於第13柱狀矽層210的上部，上述第14n型擴散層204形成於第13柱狀矽層210的下部與第11平面狀矽層121的上部；以及第11閘極配線113，連接於第11閘極電極107及第12閘極電極108。 The semiconductor device of the present embodiment further includes an n-type SGT 103 including a 13n-type diffusion layer 229 and a 14n-type diffusion layer 204, and the 13th-type diffusion layer 229 is formed on an upper portion of the 13th columnar layer 210, and the 14th The diffusion layer 204 is formed on the lower portion of the thirteen pillar-shaped tantalum layer 210 and the upper portion of the eleventh planar germanium layer 121, and the eleventh gate wiring 113 is connected to the eleventh gate electrode 107 and the twelfth gate electrode 108.

本實施方式的半導體裝置更具有：第21平面狀矽層122，在基板201上的座標的第二行，沿行方向延伸；第21柱狀矽層211，在第21平面狀矽層122上，形成於基板201上的座標的第二行第一列；第21閘極絕緣膜219，形成於第21柱狀矽層211的周圍；以及第21閘極電極110，形成於第21閘極絕緣膜219 的周圍。 The semiconductor device of the present embodiment further includes a 21st planar germanium layer 122 extending in the row direction on the second row of the coordinates on the substrate 201, and a 21st columnar germanium layer 211 on the 21st planar germanium layer 122. a second row and a first column of coordinates formed on the substrate 201; a 21st gate insulating film 219 formed around the 21st columnar layer 211; and a 21st gate electrode 110 formed at the 21st gate Insulating film 219 Around.

本實施方式的半導體裝置更具有：n型SGT104，包含第21n型擴散層230及第22n型擴散層205，上述第21n型擴散層230形成於第21柱狀矽層211的上部，上述第22n型擴散層205形成於第21柱狀矽層211的下部與第21平面狀矽層122的上部；第22柱狀矽層212，形成於第21平面狀矽層122上的座標的第二行第二列；第22閘極絕緣膜221，形成於第22柱狀矽層212的周圍；以及第22閘極電極111，形成於第22閘極絕緣膜221的周圍。 The semiconductor device of the present embodiment further includes an n-type SGT 104 including a 21n-type diffusion layer 230 and a 22n-type diffusion layer 205, and the 21st-type diffusion layer 230 is formed on an upper portion of the 21st columnar layer 211, and the 22n The diffusion layer 205 is formed on the lower portion of the 21st columnar layer 211 and the upper portion of the 21st planar layer 122; and the 22nd columnar layer 212 is formed on the second line of the 21st planar layer 122. The second column; the 22nd gate insulating film 221 is formed around the 22nd columnar layer 212; and the 22nd gate electrode 111 is formed around the 22nd gate insulating film 221.

本實施方式的半導體裝置更具有：p型SGT105，包含第21p型擴散層231及第22p型擴散層206，上述第21p型擴散層231形成於第22柱狀矽層212的上部，上述第22p型擴散層206形成於第22柱狀矽層212的下部與第21平面狀矽層122的上部；第23柱狀矽層213，形成於第21平面狀矽層122上的座標的第二行第三列；第23閘極絕緣膜221，形成於第23柱狀矽層213的周圍；以及第23閘極電極112，形成於第23閘極絕緣膜221的周圍。 The semiconductor device of the present embodiment further includes a p-type SGT 105 including a 21st p-type diffusion layer 231 and a 22p-type diffusion layer 206, and the 21st p-type diffusion layer 231 is formed on an upper portion of the 22nd columnar layer 212, and the 22p The type diffusion layer 206 is formed on the lower portion of the 22nd columnar layer 212 and the upper portion of the 21st planar layer 122; and the 23rd columnar layer 213 is formed on the second line of the 21st plane layer 122. The third column; the 23rd gate insulating film 221 is formed around the 23rd columnar layer 213; and the 23rd gate electrode 112 is formed around the 23rd gate insulating film 221.

本實施方式的半導體裝置更具有：n型SGT106，包含第23n型擴散層232及第24n型擴散層207，上述第23n型擴散層232形成於第23柱狀矽層213的上部，上述第24n型擴散層207形成於第23柱狀矽層213的下部與第21平面狀矽層122的上部；以及第21閘極配線116，連接於第22閘極電極111及第23 閘極電極112。 The semiconductor device of the present embodiment further includes an n-type SGT 106 including a 23n-type diffusion layer 232 and a 24n-type diffusion layer 207, and the 23rd-type diffusion layer 232 is formed on an upper portion of the 23rd columnar layer 213, and the 24th The type diffusion layer 207 is formed on the lower portion of the 23rd columnar layer 213 and the upper portion of the 21st planar layer 122; and the 21st gate line 116 is connected to the 22nd gate electrode 111 and the 23rd Gate electrode 112.

本實施方式的半導體裝置中，沿著第11閘極配線113延伸的中心線，相對於連結第11柱狀矽層208的中心與第12柱狀矽層209的中心的線，而向基板201上的座標的第二行方向偏移第11規定量。 In the semiconductor device of the present embodiment, the center line extending along the eleventh gate line 113 is directed to the substrate 201 with respect to a line connecting the center of the eleventh columnar layer 208 and the center of the twelfth columnar layer 209. The second row direction of the upper coordinate is offset by the eleventh specified amount.

而且，本實施方式的半導體裝置中，沿著第21閘極配線116延伸的中心線，相對於連結第22柱狀矽層212的中心與第23柱狀矽層213的中心的線，而向基板201上的座標的第一行方向偏移第11規定量。 Further, in the semiconductor device of the present embodiment, the center line extending along the 21st gate line 116 is aligned with the line connecting the center of the 22nd columnar layer 212 and the center of the 23rd columnar layer 213. The first row direction of the coordinates on the substrate 201 is shifted by the eleventh predetermined amount.

本實施方式的半導體裝置更具有：第11絕緣膜側牆127，形成於第11閘極配線113的側壁上；以及矽化物117，形成於第12n型擴散層202上與第12p型擴散層203上。並且，第11規定量大於下述值，該值是自第11絕緣膜側牆127的寬度與第11閘極配線113的寬度的一半長度之和，減去第11平面狀矽層121的寬度的一半長度所得的值。 The semiconductor device of the present embodiment further includes: a first insulating film spacer 127 formed on a sidewall of the eleventh gate wiring 113; and a germanide 117 formed on the twelfth n-type diffusion layer 202 and the twelfth p-type diffusion layer 203 on. Further, the eleventh predetermined amount is larger than the sum of the width from the width of the eleventh insulating film spacer 127 and the width of the eleventh gate wiring 113, and the width of the eleventh planar crucible layer 121 is subtracted. The resulting value of half the length.

本實施方式中，於第11柱狀矽層208與第12柱狀矽層209之間、以及第21柱狀矽層211與第22柱狀矽層212之間，形成有第11接觸部124。第11接觸部124將第11閘極配線113與第21平面狀矽層122電性連接。 In the present embodiment, the eleventh contact portion 124 is formed between the eleventh columnar layer 208 and the twelfth columnar layer 209 and between the twenty columnar layer 211 and the twenty columnar layer 212. . The eleventh contact portion 124 electrically connects the eleventh gate wiring 113 and the twenty-first planar germanium layer 122.

而且，本實施方式中，第11規定量大於下述值，該值是自第11平面狀矽層121的寬度的一半長度，減去第11絕緣膜側牆127的寬度與第11閘極配線113的寬度的一半長度之和所得 的值。 Further, in the present embodiment, the eleventh predetermined amount is larger than a value which is half the width of the eleventh planar tantalum layer 121, and the width of the eleventh insulating film spacer 127 is subtracted from the eleventh gate wiring. The sum of the lengths of half the width of 113 Value.

本實施方式中，藉由於第11平面狀矽層121上形成矽化物，從而可將n型SGT101的第12n型擴散層202與p型SGT102的第12p型擴散層203電性連接，上述第11平面狀矽層121是存在於第11閘極配線113的第1邊周圍的元件形成區域。 In the present embodiment, the 12th n-type diffusion layer 202 of the n-type SGT 101 and the 12th p-type diffusion layer 203 of the p-type SGT 102 can be electrically connected to each other by the formation of a germanide on the 11th planar germanium layer 121. The planar germanium layer 121 is an element formation region existing around the first side of the eleventh gate wiring 113.

本實施方式中，第11平面狀矽層121呈由第11閘極配線113與第11絕緣膜側牆127予以覆蓋的結構，上述第11平面狀矽層121是存在於第11閘極配線113的第2邊周圍的元件形成區域。 In the present embodiment, the eleventh planar germanium layer 121 is covered by the eleventh gate wiring 113 and the eleventh insulating film spacer 127, and the eleventh planar germanium layer 121 is present in the eleventh gate wiring 113. The component forming area around the second side.

因此，根據本實施方式，當於第11柱狀矽層208與第12柱狀矽層209之間、以及第21柱狀矽層211與第22柱狀矽層212之間形成第11接觸部124時，可藉由第11接觸部124來電性連接第11閘極配線113與第21平面狀矽層122，另一方面，可使第11接觸部124與第11平面狀矽層121彼此絕緣。 Therefore, according to the present embodiment, the eleventh contact portion is formed between the eleventh columnar layer 208 and the twelfth columnar layer 209, and between the twenty columnar layer 211 and the twenty columnar layer 212. At 124 o'clock, the eleventh gate line 113 and the twenty-plane planar layer 122 can be electrically connected by the eleventh contact portion 124, and the eleventh contact portion 124 and the eleventh planar layer 121 can be insulated from each other. .

根據本實施方式，可藉由第11接觸部124來電性連接SRAM的反相器的輸出入端。其結果，可提供高積體的SRAM。 According to the present embodiment, the input/output terminal of the inverter of the SRAM can be electrically connected to the eleventh contact portion 124. As a result, a high-integrated SRAM can be provided.

本實施方式中，對於閘極絕緣膜221，可使用氧化膜、氮化膜、氮氧化膜、高介電質膜等被用於半導體的絕緣膜。 In the present embodiment, as the gate insulating film 221, an insulating film used for a semiconductor such as an oxide film, a nitride film, an oxynitride film, or a high dielectric film can be used.

本實施方式的半導體裝置更具有：第11閘極電極107，包含形成於第11閘極絕緣膜215周圍的金屬膜216以及多晶矽223的積層結構；第12閘極電極108，包含形成於第12閘極絕緣膜215周圍的金屬膜216以及多晶矽223的積層結構；以及 第13閘極電極109，包含形成於第13閘極絕緣膜217周圍的金屬膜218以及多晶矽224的積層結構。此處，閘極亦可僅由金屬膜構成。而且，對於閘極，亦可使用矽化物來作為材料。而且，對於金屬膜，可使用鈦、氮化鈦、鉭、氮化鉭等被用於半導體的金屬。 The semiconductor device of the present embodiment further includes a eleventh gate electrode 107 including a laminated structure of a metal film 216 and a polysilicon 223 formed around the eleventh gate insulating film 215, and a twelfth gate electrode 108 including a second electrode. a laminated structure of the metal film 216 around the gate insulating film 215 and the polysilicon 223; The thirteenth gate electrode 109 includes a laminated structure of the metal film 218 and the polysilicon 224 formed around the thirteenth gate insulating film 217. Here, the gate electrode may be composed only of a metal film. Moreover, for the gate, a telluride can also be used as the material. Further, as the metal film, a metal used for a semiconductor such as titanium, titanium nitride, tantalum or tantalum nitride can be used.

以連接於第13閘極電極109的方式而形成有閘極配線114。 The gate wiring 114 is formed to be connected to the thirteenth gate electrode 109.

本實施方式的半導體裝置更具有：絕緣膜側牆，包含遍及第11柱狀矽層208的上部側壁與第11閘極電極107上部而形成的氧化膜244與氮化膜245；絕緣膜側牆，包含遍及第12柱狀矽層209的上部側壁與第12閘極電極108上部而形成的氧化膜246與氮化膜247；絕緣膜側牆，包含遍及第13柱狀矽層210的上部側壁與第13閘極電極109上部而形成的氧化膜248與氮化膜249；以及矽化物234、236、237，遍及第11n型擴散層227上、第11p型擴散層228上與第13n型擴散層229上而形成。 The semiconductor device of the present embodiment further includes an insulating film spacer, including an oxide film 244 and a nitride film 245 formed over the upper sidewall of the eleventh columnar layer 208 and the upper portion of the eleventh gate electrode 107; the insulating film spacer An oxide film 246 and a nitride film 247 formed over the upper sidewall of the twelfth columnar layer 209 and the upper portion of the twelfth gate electrode 108, and the insulating film spacer including the upper sidewall of the thirteenth columnar layer 210 The oxide film 248 and the nitride film 249 formed on the upper portion of the thirteenth gate electrode 109; and the germanium 234, 236, and 237 are spread over the 11n-type diffusion layer 227, the 11-th type diffusion layer 228, and the 13n-type diffusion. Layer 229 is formed.

遍及第12p型擴散層203上與第14n型擴散層204上而形成有矽化物118，且於第11閘極配線113上形成有矽化物235。於閘極配線114上形成有矽化物238。 A telluride 118 is formed on the 12p-type diffusion layer 203 and the 14n-type diffusion layer 204, and a germanide 235 is formed on the 11th gate wiring 113. A telluride 238 is formed on the gate wiring 114.

於閘極配線114的側壁形成有絕緣膜側牆128。 An insulating film spacer 128 is formed on the sidewall of the gate wiring 114.

分別於矽化物234上形成有接觸部257，於矽化物236上形成有接觸部258，於矽化物237上形成有接觸部259。 A contact portion 257 is formed on the germanide 234, a contact portion 258 is formed on the germanide 236, and a contact portion 259 is formed on the germanide 237.

本實施方式的半導體裝置還具有：第21閘極電極 110，包含形成於第21閘極絕緣膜219周圍的金屬膜220以及多晶矽225的積層結構；第22閘極電極111，包含積層結構，該積層結構包含形成於第22閘極絕緣膜221周圍的金屬膜222以及多晶矽226；以及第23閘極電極112，包含積層結構，該積層結構包含形成於第23閘極絕緣膜221周圍的金屬膜222以及多晶矽226。 The semiconductor device of the present embodiment further has: a 21st gate electrode 110. A multilayer structure including a metal film 220 formed around the 21st gate insulating film 219 and a polysilicon 225; the 22nd gate electrode 111 includes a buildup structure including a periphery formed around the 22nd gate insulating film 221. The metal film 222 and the polysilicon 226 and the 23rd gate electrode 112 include a buildup structure including a metal film 222 and a polysilicon 226 formed around the 23rd gate insulating film 221.

此處，閘極亦可僅包含金屬膜。而且，對於閘極，亦可使用矽化物。進而，對於金屬膜，可使用鈦、氮化鈦、鉭、氮化鉭等被用於半導體的金屬。 Here, the gate may also include only a metal film. Moreover, for the gate, a telluride can also be used. Further, as the metal film, a metal used for a semiconductor such as titanium, titanium nitride, tantalum or tantalum nitride can be used.

而且，本實施方式中，以連接於第21閘極電極110的方式而形成有閘極配線115。 Further, in the present embodiment, the gate wiring 115 is formed to be connected to the 21st gate electrode 110.

本實施方式的半導體裝置更具有：絕緣膜側牆，包含遍及第21柱狀矽層211的上部側壁與第21閘極電極110上部而形成的氧化膜250與氮化膜251；絕緣膜側牆，包含遍及第22柱狀矽層212的上部側壁與第22閘極電極111上部而形成的氧化膜252與氮化膜253；絕緣膜側牆，包含遍及第23柱狀矽層213的上部側壁與第23閘極電極112上部而形成的氧化膜254與氮化膜255；以及矽化物240、241、243，遍及第21n型擴散層230上、第21p型擴散層231上與第23n型擴散層232上而形成。 The semiconductor device of the present embodiment further includes an insulating film spacer, including an oxide film 250 and a nitride film 251 formed over the upper sidewall of the 21st columnar layer 211 and the upper portion of the 21st gate electrode 110; and the insulating film spacer The oxide film 252 and the nitride film 253 formed over the upper sidewall of the 22nd columnar layer 212 and the upper portion of the 22nd gate electrode 111; the insulating film spacer includes the upper sidewall of the 23rd columnar layer 213 The oxide film 254 and the nitride film 255 formed on the upper portion of the 23rd gate electrode 112; and the tellurides 240, 241, and 243 spread over the 21st n-type diffusion layer 230, the 21p-type diffusion layer 231, and the 23n-type diffusion. Formed on layer 232.

本實施方式中，遍及第22n型擴散層205上與第22p型擴散層206上而形成有矽化物119，且於第21閘極配線116上形成有矽化物242。於閘極配線115上形成有矽化物239。 In the present embodiment, a germanide 119 is formed over the 22n-type diffusion layer 205 and the 22p-type diffusion layer 206, and a germanide 242 is formed on the 21st gate wiring 116. A germanide 239 is formed on the gate wiring 115.

遍及第22p型擴散層206上與第24n型擴散層207上而形成有矽化物120。 A telluride 120 is formed over the 22p-type diffusion layer 206 and the 24n-type diffusion layer 207.

於閘極配線115的側壁形成有絕緣膜側牆129。於第21閘極配線116的側壁形成有絕緣膜側牆130。 An insulating film spacer 129 is formed on the sidewall of the gate wiring 115. An insulating film spacer 130 is formed on a sidewall of the 21st gate wiring 116.

分別於矽化物240上形成有接觸部260，於矽化物241上形成有接觸部261，於矽化物243上形成有接觸部262。 A contact portion 260 is formed on the telluride 240, a contact portion 261 is formed on the germanide 241, and a contact portion 262 is formed on the germanide 243.

分別於矽化物239上形成有接觸部123，於矽化物235、119上形成有第11接觸部124，於矽化物118、242上形成有接觸部125，於矽化物238上形成有接觸部126。 A contact portion 123 is formed on the telluride 239, a thirteenth contact portion 124 is formed on the telluride 235, 119, a contact portion 125 is formed on the germanium compound 118, 242, and a contact portion 126 is formed on the germanide 238. .

於第11平面狀矽層121與第21平面狀矽層122的周圍，形成有元件分離膜214。而且，於n型SGT101、103、104、106與p型SGT102、104的周圍，形成有層間絕緣膜256。 An element separation film 214 is formed around the eleventh planar germanium layer 121 and the twenty-first planar germanium layer 122. Further, an interlayer insulating film 256 is formed around the n-type SGTs 101, 103, 104, and 106 and the p-type SGTs 102 and 104.

根據本實施方式，藉由以上結構，可藉由第11接觸部124來電性連接SRAM的反相器的輸出入端，因此可提供高積體的SRAM。 According to the present embodiment, with the above configuration, the output terminal of the inverter of the SRAM can be electrically connected by the eleventh contact portion 124, so that a high-integration SRAM can be provided.

於以下說明的本發明的實施方式中，沿著第1閘極配線延伸的中心線相對於連結第1柱狀矽層的中心與第2柱狀矽層的中心的線，而偏移第1規定量。 In the embodiment of the present invention described below, the center line extending along the first gate line is offset from the line connecting the center of the first columnar layer and the center of the second columnar layer. The specified amount.

藉此，可於平面狀矽層上形成矽化物，從而將n型SGT的第2n型擴散層與p型SGT的第2p型擴散層電性連接，上述平面狀矽層是形成於閘極配線的第1邊側周圍的元件形成區域。因此，與在存在於閘極配線的相向的兩邊周圍的元件形成區域中 形成有矽化物時相比，可縮短作為元件形成區域的平面狀矽層的寬度。而且，由於作為元件形成區域的平面狀矽層的寬度短，因此可實現高積體的CMOS SGT反相器。 Thereby, a germanide can be formed on the planar germanium layer to electrically connect the second n-type diffusion layer of the n-type SGT and the second p-type diffusion layer of the p-type SGT, and the planar germanium layer is formed on the gate wiring. The element forming region around the first side. Therefore, in the element formation region around the opposite sides existing on the gate wiring When the germanium compound is formed, the width of the planar germanium layer as the element formation region can be shortened. Further, since the width of the planar germanium layer as the element formation region is short, a highly integrated CMOS SGT inverter can be realized.

根據本發明的實施方式，半導體裝置具有：第1絕緣膜側牆，形成於第1閘極配線的側壁；以及矽化物，遍及第2n型擴散層上與第2p型擴散層上而形成。進而，第1規定量大於下述值，該值是自第1絕緣膜側牆的寬度與第1閘極配線的寬度的一半長度之和，減去第1平面狀矽層的寬度的一半長度所得的值。藉此，可於平面狀矽層上形成矽化物，上述平面狀矽層是存在於閘極配線的第1邊周圍的元件形成區域。 According to an embodiment of the present invention, a semiconductor device includes a first insulating film spacer, a sidewall formed on the first gate wiring, and a germanide formed over the second n-type diffusion layer and the second p-type diffusion layer. Further, the first predetermined amount is larger than a value obtained by subtracting the half length of the width of the first planar film layer from the half of the width of the first insulating film side wall and the width of the first gate wiring. The value obtained. Thereby, a telluride can be formed on the planar germanium layer, and the planar germanium layer is an element formation region existing around the first side of the gate wiring.

根據本發明的實施方式，第2閘極電極的上部是由第3絕緣膜側牆予以覆蓋，側壁是由第1絕緣膜側牆予以覆蓋。第3絕緣膜側牆的側壁是由第1絕緣膜側牆予以覆蓋。因此，當於平面狀矽層上部的擴散層上形成的接觸部向第2閘極電極側偏移(相對位置發生偏離(shift))時，可防止第2閘極電極與接觸部彼此短路。 According to the embodiment of the present invention, the upper portion of the second gate electrode is covered by the third insulating film side wall, and the side wall is covered by the first insulating film side wall. The side wall of the third insulating film side wall is covered by the first insulating film side wall. Therefore, when the contact portion formed on the diffusion layer on the upper portion of the planar germanium layer is shifted toward the second gate electrode side (the relative position is shifted), the second gate electrode and the contact portion can be prevented from being short-circuited with each other.

根據本發明的實施方式，可提供作為元件形成區域的平面狀矽層的寬度短的CMOS SGT的結構。藉此，可提供高積體的SRAM。 According to an embodiment of the present invention, a structure of a CMOS SGT having a short width of a planar germanium layer as an element formation region can be provided. Thereby, a high-integrated SRAM can be provided.

根據本發明的實施方式，可於第11平面狀矽層上形成矽化物，從而將n型SGT的第12n型擴散層與p型SGT的第12p型擴散層電性連接，上述第11平面狀矽層是存在於第11閘極配 線的第1邊周圍的元件形成區域。而且，第11平面狀矽層是由第11閘極配線與第11絕緣膜側牆予以覆蓋，上述第11平面狀矽層是存在於第11閘極配線的第2邊周圍的元件形成區域。因此，藉由於第11柱狀矽層與第12柱狀矽層之間、以及第21柱狀矽層與第22柱狀矽層之間形成第11接觸部，從而第11接觸部可電性連接第11閘極配線與第21平面狀矽層，另一方面，可使第11接觸部與第11平面狀矽層絕緣。 According to the embodiment of the present invention, the telluride can be formed on the eleventh planar germanium layer, and the twelfth nn type diffusion layer of the n-type SGT and the tf-type SGT of the p-type SGT can be electrically connected to the eleventh planar layer. The 矽 layer is present in the 11th gate An element forming region around the first side of the line. Further, the eleventh planar germanium layer is covered by the eleventh gate wiring and the eleventh insulating film side wall, and the eleventh planar germanium layer is an element formation region existing around the second side of the eleventh gate wiring. Therefore, the eleventh contact portion can be electrically formed by forming the eleventh contact portion between the eleventh columnar layer and the twelfth columnar layer and between the twenty columnar layer and the second columnar layer. The eleventh gate wiring and the twenty-first planar crucible layer are connected, and on the other hand, the eleventh contact portion and the eleventh planar crucible layer can be insulated.

根據本發明的實施方式，可藉由第11接觸部來電性連接SRAM的反相器的輸出入端。藉此，提供高積體的SRAM。 According to an embodiment of the present invention, the input/output terminal of the inverter of the SRAM can be electrically connected to the eleventh contact portion. Thereby, a high-integration SRAM is provided.

再者，本發明並不脫離其廣義的精神與範圍，可採用各種實施方式以及變形。而且，上述實施方式是用於說明本發明的一實施例，並不限定本發明的範圍。 Further, the present invention is not to be construed as being limited to Further, the above embodiment is for explaining an embodiment of the present invention, and does not limit the scope of the present invention.

例如，於上述實施方式中，將p型(包含p+型)與n型(包含n+型)設為彼此相反的導電型的半導體裝置的製造方法、以及藉由該製造方法而獲得的半導體裝置當然亦包含在本發明的技術範圍內。 For example, in the above embodiment, a method of manufacturing a semiconductor device in which a p-type (including p + type) and an n type (including n + type) are opposite to each other and a semiconductor obtained by the manufacturing method The device is of course also included in the technical scope of the present invention.

301‧‧‧n型SGT 301‧‧‧n type SGT

302‧‧‧p型SGT 302‧‧‧p type SGT

303‧‧‧第1閘極電極 303‧‧‧1st gate electrode

304‧‧‧第2閘極電極 304‧‧‧2nd gate electrode

305‧‧‧第1閘極配線 305‧‧‧1st gate wiring

306‧‧‧閘極配線 306‧‧‧gate wiring

307‧‧‧第1絕緣膜側牆 307‧‧‧1st insulating film side wall

308、510、511、512、513、514‧‧‧矽化物 308, 510, 511, 512, 513, 514‧‧ ‧ Telluride

309‧‧‧第1平面狀矽層 309‧‧‧1st planar layer

501‧‧‧基板 501‧‧‧Substrate

502‧‧‧第2n型擴散層 502‧‧‧2n type diffusion layer

503‧‧‧第2p型擴散層 503‧‧‧2p diffusion layer

504‧‧‧第1柱狀矽層 504‧‧‧1st columnar layer

505‧‧‧第2柱狀矽層 505‧‧‧2nd columnar layer

506‧‧‧第1閘極絕緣膜、第2閘極絕緣膜 506‧‧‧1st gate insulating film, 2nd gate insulating film

507‧‧‧金屬膜 507‧‧‧Metal film

508‧‧‧元件分離膜 508‧‧‧ component separation membrane

509‧‧‧多晶矽 509‧‧‧ Polysilicon

515‧‧‧層間絕緣膜 515‧‧‧Interlayer insulating film

516、518‧‧‧氧化膜 516, 518‧‧ ‧ oxide film

517、519‧‧‧氮化膜 517, 519‧‧‧ nitride film

520、521、522、523‧‧‧接觸部 520, 521, 522, 523‧ ‧ contact

524‧‧‧第1n型擴散層 524‧‧‧1n type diffusion layer

525‧‧‧第1p型擴散層 525‧‧‧1p type diffusion layer

Claims (8)

一種半導體裝置，其特徵在於包括：第1平面狀矽層，形成於基板上；第1以及第2柱狀矽層，形成於上述第1平面狀矽層上；第1閘極絕緣膜，形成於上述第1柱狀矽層的周圍；第1閘極電極，形成於上述第1閘極絕緣膜的周圍；第2閘極絕緣膜，形成於上述第2柱狀矽層的周圍；第2閘極電極，形成於上述第2閘極絕緣膜的周圍；第1閘極配線，連接於上述第1以及上述第2閘極電極；第1第二導電型擴散層，形成於上述第1柱狀矽層的上部；第2第二導電型擴散層，遍及上述第1柱狀矽層的下部與上述第1平面狀矽層的上部而形成；第1第一導電型擴散層，形成於上述第2柱狀矽層的上部；以及第2第一導電型擴散層，遍及上述第2柱狀矽層的下部與上述第1平面狀矽層的上部而形成，沿著上述第1閘極配線延伸的中心線相對於連結上述第1柱狀矽層的中心與上述第2柱狀矽層的中心的線而偏移第1規定量。 A semiconductor device comprising: a first planar germanium layer formed on a substrate; first and second columnar germanium layers formed on the first planar germanium layer; and a first gate insulating film formed Around the first columnar layer, a first gate electrode is formed around the first gate insulating film, and a second gate insulating film is formed around the second columnar layer; a gate electrode is formed around the second gate insulating film; a first gate wiring is connected to the first and second gate electrodes; and a first second conductivity type diffusion layer is formed on the first pillar An upper portion of the ruthenium layer; a second second conductivity type diffusion layer formed over the lower portion of the first columnar ruthenium layer and an upper portion of the first planar ruthenium layer; and the first first conductivity type diffusion layer formed on the An upper portion of the second columnar layer and a second first conductivity type diffusion layer are formed over the lower portion of the second columnar layer and the upper portion of the first planar layer, along the first gate line a center line extending relative to a center connecting the first columnar layer and the second columnar layer The line of the heart is offset by the first predetermined amount. 如申請專利範圍第1項所述之半導體裝置，其包括：第1絕緣膜側牆，形成於上述第1閘極配線的側壁；以及矽化物，遍及上述第2第二導電型擴散層上與上述第2第一導電型擴散層上而形成， 上述第1規定量大於下述值，該值是自第1絕緣膜側牆的寬度與上述第1閘極配線的寬度的一半長度之和，減去上述第1平面狀矽層的寬度的一半長度所得的值。 The semiconductor device according to claim 1, comprising: a first insulating film spacer formed on a sidewall of the first gate wiring; and a telluride over the second conductive diffusion layer Formed on the second first conductivity type diffusion layer, The first predetermined amount is larger than a value obtained by subtracting a width of a width of the first insulating film side wall from a half of a width of the first gate wiring, and subtracting a half of a width of the first planar tantalum layer. The value obtained from the length. 如申請專利範圍第1項所述之半導體裝置，其中上述第1規定量大於下述值，該值是自上述第1平面狀矽層的寬度的一半長度，減去第1絕緣膜側牆的寬度與上述第1閘極配線的寬度的一半長度之和所得的值。 The semiconductor device according to claim 1, wherein the first predetermined amount is larger than a value obtained by subtracting a length of the first insulating film sidewall from a half of a width of the first planar germanium layer. The value obtained by the sum of the width and the half length of the width of the first gate wiring described above. 如申請專利範圍第2項所述之半導體裝置，其包括：第2絕緣膜側牆，遍及上述第1柱狀矽層的上部側壁與上述第1閘極電極上部而形成；第3絕緣膜側牆，遍及上述第2柱狀矽層的上部側壁與上述第2閘極電極上部而形成；第1絕緣膜側牆，遍及上述第2以及上述第3絕緣膜側牆、上述第1以及上述第2閘極電極與上述第1閘極配線的側壁而形成；以及矽化物，遍及上述第1第二導電型擴散層上與上述第1第一導電型擴散層上而形成。 The semiconductor device according to claim 2, comprising: a second insulating film spacer, formed on an upper sidewall of the first columnar layer and an upper portion of the first gate electrode; and a third insulating film side a wall is formed over the upper side wall of the second columnar layer and the upper portion of the second gate electrode; and the first insulating film side wall extends over the second and third insulating film side walls, the first and the first 2 a gate electrode and a sidewall of the first gate wiring; and a telluride formed over the first first conductivity type diffusion layer and the first first conductivity type diffusion layer. 一種半導體裝置，其特徵在於包括：第11平面狀矽層，在包含於基板上設定的行及列的座標的第一行，以沿該行方向延伸的方式而形成；第11柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第一列； 第11閘極絕緣膜，形成於上述第11柱狀矽層的周圍；第11閘極電極，形成於上述第11閘極絕緣膜的周圍；第11第二導電型擴散層，形成於上述第11柱狀矽層的上部；第12第二導電型擴散層，遍及上述第11柱狀矽層的下部與上述第11平面狀矽層的上部而形成；第12柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第二列；第12閘極絕緣膜，形成於上述第12柱狀矽層的周圍；第12閘極電極，形成於上述第12閘極絕緣膜的周圍；第11第一導電型擴散層，形成於上述第12柱狀矽層的上部；第12第一導電型擴散層，遍及上述第12柱狀矽層的下部與上述第11平面狀矽層的上部而形成；第13柱狀矽層，在上述第11平面狀矽層上，形成於上述座標的第一行第三列；第13閘極絕緣膜，形成於上述第13柱狀矽層的周圍；第13閘極電極，形成於上述第13閘極絕緣膜的周圍；第13第二導電型擴散層，形成於上述第13柱狀矽層的上部；第14第二導電型擴散層，遍及上述第13柱狀矽層的下部與上述第11平面狀矽層的上部而形成；第11閘極配線，連接於上述第11以及上述第12閘極電極；第21平面狀矽層，形成於在上述基板上設定的座標的第二行； 第21柱狀矽層，於上述第21平面狀矽層上，形成於上述座標的第二行第一列；第21閘極絕緣膜，形成於上述第21柱狀矽層的周圍；第21閘極電極，形成於上述第21閘極絕緣膜的周圍；第21第二導電型擴散層，形成於上述第21柱狀矽層的上部；第22第二導電型擴散層，遍及上述第21柱狀矽層的下部與上述第21平面狀矽層的上部而形成；第22柱狀矽層，在上述第21平面狀矽層上，形成於上述座標的第二行第二列；第22閘極絕緣膜，形成於上述第22柱狀矽層的周圍；第22閘極電極，形成於上述第22閘極絕緣膜的周圍；第21第一導電型擴散層，形成於上述第22柱狀矽層的上部；第22第一導電型擴散層，遍及上述第22柱狀矽層的下部與上述第21平面狀矽層的上部而形成；第23柱狀矽層，在上述第21平面狀矽層上，形成於上述座標的第二行第三列；第23閘極絕緣膜，形成於上述第23柱狀矽層的周圍；第23閘極電極，形成於上述第23閘極絕緣膜的周圍；第23第二導電型擴散層，形成於上述第23柱狀矽層的上部；第24第二導電型擴散層，遍及上述第23柱狀矽層的下部與上述第21平面狀矽層的上部而形成；以及第21閘極配線，連接於上述第22以及上述第23閘極電極， 沿著上述第11閘極配線延伸的中心線相對於連結上述第11柱狀矽層的中心與上述第12柱狀矽層的中心的線而在上述座標的第二行中，沿該行方向偏移第11規定量，沿著上述第21閘極配線延伸的中心線相對於連結上述第22柱狀矽層的中心與上述第23柱狀矽層的中心的線而在上述座標的第一行中，沿該行方向偏移第11規定量。 A semiconductor device comprising: an eleventh planar germanium layer formed on a first row of coordinates included in rows and columns set on a substrate, extending in the row direction; and an eleventh columnar layer Forming on the eleventh planar enamel layer on the first row and the first column of the coordinates; The eleventh gate insulating film is formed around the eleventh columnar layer; the eleventh gate electrode is formed around the eleventh gate insulating film; and the eleventh second conductivity type diffusion layer is formed on the first An upper portion of the columnar ruthenium layer; a twelfth second conductivity type diffusion layer formed over the lower portion of the eleventh columnar ruthenium layer and the upper portion of the eleventh planar ruthenium layer; and the twelfth columnar ruthenium layer a planar ruthenium layer formed on the first row and the second column of the coordinates; a twelfth gate insulating film formed around the twelfth columnar ruthenium layer; and a twelfth gate electrode formed on the twelfth gate a periphery of the pole insulating film; an eleventh first conductivity type diffusion layer formed on an upper portion of the twelfth columnar layer; and a twelfth first conductivity type diffusion layer in a lower portion of the twelfth columnar layer and the eleventh portion Formed on the upper portion of the planar ruthenium layer; the thirteenth columnar ruthenium layer is formed on the eleventh planar ruthenium layer in the first row and the third column of the coordinates; and the thirteenth gate insulating film is formed on the thirteenth a periphery of the columnar layer; a thirteenth gate electrode formed around the thirteenth gate insulating film; a second conductive diffusion layer formed on an upper portion of the thirteenth columnar layer; and a fourth second conductivity diffusion layer formed on a lower portion of the thirteenth columnar layer and an upper portion of the eleventh planar layer; a thirteenth gate wiring connected to the eleventh and the twelfth gate electrode; and a twenty-first planar germanium layer formed on a second row of coordinates set on the substrate; a 21st columnar layer formed on the 21st planar layer of the second row and the first row of the coordinates; and a 21st gate insulating film formed around the 21st columnar layer; 21st a gate electrode is formed around the 21st gate insulating film; a 21st second conductivity type diffusion layer is formed on an upper portion of the 21st columnar layer; and a 22nd second conductivity type diffusion layer is provided in the 21st a lower portion of the columnar tantalum layer and an upper portion of the 21st planar tantalum layer; and a 22nd columnar tantalum layer formed on the 21st planar tantalum layer in the second row and the second column of the coordinates; 22nd a gate insulating film is formed around the 22nd columnar layer; a 22nd gate electrode is formed around the 22nd gate insulating film; and a 21st first conductivity type diffusion layer is formed in the 22nd column An upper portion of the ruthenium layer; a 22nd first conductivity type diffusion layer formed over the lower portion of the 22nd columnar ruthenium layer and an upper portion of the 21st planar ruthenium layer; and a 23rd columnar ruthenium layer at the 21st plane a second row and a third column of the above-mentioned coordinates; a 23rd gate insulating film formed on the layer 23 around the columnar layer; a 23rd gate electrode formed around the 23rd gate insulating film; and a 23rd second conductivity type diffusion layer formed on the upper portion of the 23rd columnar layer; a second conductive diffusion layer formed over the lower portion of the 23rd columnar layer and the upper portion of the 21st planar germanium layer; and a 21st gate wiring connected to the 22nd and the 23rd gate electrode a center line extending along the eleventh gate line is along the line connecting the center of the eleventh columnar layer and the center of the twelfth columnar layer in the second row of the coordinates Offset by a predetermined amount, the center line extending along the 21st gate wiring is at the first of the coordinates with respect to a line connecting the center of the 22nd columnar layer and the center of the 23rd columnar layer In the row, the eleventh predetermined amount is shifted in the row direction. 如申請專利範圍第5項所述的半導體裝置，其包括：第11絕緣膜側牆，形成於上述第11閘極配線的側壁；以及矽化物，遍及上述第12第二導電型擴散層上與上述第12第一導電型擴散層上而形成，上述第11規定量大於下述值，該值是自第11絕緣膜側牆的寬度與上述第11閘極配線的寬度的一半長度之和，減去上述第11平面狀矽層的寬度的一半長度所得的值。 The semiconductor device according to claim 5, comprising: an eleventh insulating film spacer formed on a sidewall of the eleventh gate wiring; and a telluride over the twelfth second conductivity type diffusion layer The first first conductivity type diffusion layer is formed on the first, and the eleventh predetermined amount is larger than a value obtained by a sum of a width from a side wall of the eleventh insulating film and a half length of a width of the eleventh gate line. The value obtained by subtracting half the width of the eleventh planar tantalum layer is obtained. 如申請專利範圍第6項所述的半導體裝置，其中遍及上述第11柱狀矽層與上述第12柱狀矽層之間、及上述第21柱狀矽層與上述第22柱狀矽層之間，而形成有第11接觸部，上述第11閘極配線經由上述第11接觸部而電性連接於上述第21平面狀矽層。 The semiconductor device according to claim 6, wherein the first columnar layer and the second columnar layer and the second columnar layer and the second columnar layer are An eleventh contact portion is formed, and the eleventh gate wiring is electrically connected to the 21st planar germanium layer via the eleventh contact portion. 如申請專利範圍第5項所述的半導體裝置，其中上述第11規定量大於下述值，該值是自上述第11平面狀矽層的寬度的一半長度，減去第11絕緣膜側牆的寬度與上述第11閘極配線的寬度的一半長度之和所得的值。 The semiconductor device according to claim 5, wherein the eleventh predetermined amount is larger than a value which is half the width of the eleventh planar germanium layer, and the side wall of the eleventh insulating film is subtracted The value obtained by the sum of the width and the half length of the width of the eleventh gate wiring described above.
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