JP5911948B2 - Semiconductor device - Google Patents

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JP5911948B2
JP5911948B2 JP2014263130A JP2014263130A JP5911948B2 JP 5911948 B2 JP5911948 B2 JP 5911948B2 JP 2014263130 A JP2014263130 A JP 2014263130A JP 2014263130 A JP2014263130 A JP 2014263130A JP 5911948 B2 JP5911948 B2 JP 5911948B2
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metal
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columnar semiconductor
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JP2015233115A (en
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舛岡　富士雄
富士雄 舛岡
広記 中村
広記 中村
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Unisantis Electronics Singapore Pte Ltd
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Description

本発明は半導体装置の製造方法、及び、半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

半導体集積回路、特にＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。このようなＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。このような問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲート電極が柱状半導体層を取り囲む構造のSurrounding Gate Transistor（以下、「ＳＧＴ」という。）が提案されている（例えば、特許文献１、特許文献２、特許文献３を参照）。   Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

シリコン柱が細くなると、シリコンの密度は５×１０22個／ｃｍ3であるから、シリコン柱内に不純物を存在させることが難しくなってくる。 When the silicon pillar is thinned, the density of silicon is 5 × 10 22 pieces / cm 3 , so that it becomes difficult for impurities to exist in the silicon pillar.

従来のＳＧＴでは、チャネル濃度を１０17ｃｍ-3以下と低不純物濃度とし、ゲート材料の仕事関数を変えることによってしきい値電圧を決定することが提案されている（例えば、特許文献４を参照）。 In the conventional SGT, it is proposed to determine the threshold voltage by changing the work function of the gate material by setting the channel concentration to a low impurity concentration of 10 17 cm −3 or less (see, for example, Patent Document 4). ).

平面型ＭＯＳトランジスタにおいて、ＬＤＤ領域のサイドウォールが低濃度層と同一の導電型を有する多結晶シリコンにより形成され、ＬＤＤ領域の表面キャリアがその仕事関数差によって誘起され、酸化膜サイドウォールＬＤＤ型ＭＯＳトランジスタに比してＬＤＤ領域のインピーダンスが低減できることが示されている（例えば、特許文献５を参照）。その多結晶シリコンサイドウォールは電気的にゲート電極と絶縁されていることが示されている。また図中には多結晶シリコンサイドウォールとソース・ドレインとは層間絶縁膜により絶縁していることが示されている。   In the planar MOS transistor, the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (see, for example, Patent Document 5). The polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.

特開平２−７１５５６号公報JP-A-2-71556 特開平２−１８８９６６号公報Japanese Patent Laid-Open No. 2-188966 特開平３−１４５７６１号公報Japanese Patent Laid-Open No. 3-145761 特開２００４−３５６３１４号公報JP 2004-356314 A 特開平１１−２９７９８４号公報JP 11-297984 A

そこで、本発明は、トランジスタを金属と半導体との仕事関数差によって形成する構造を持つＳＧＴを提供することを目的とする。   Therefore, an object of the present invention is to provide an SGT having a structure in which a transistor is formed by a work function difference between a metal and a semiconductor.

第１の発明の半導体装置は、１０17ｃｍ-3以下の不純物濃度の柱状半導体と、前記柱状半導体を囲む第１の絶縁物と、前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、前記第１の金属と前記柱状半導体の一端とを接続する第４の金属と、前記第２の金属と前記柱状半導体の他方の一端とを接続する第５の金属を有し、前記第３の金属の仕事関数は４．２ｅＶから５．０ｅＶの間であることを特徴とする。 A semiconductor device according to a first aspect of the present invention is a columnar semiconductor having an impurity concentration of 10 17 cm −3 or less, a first insulator surrounding the columnar semiconductor, and a first insulator surrounding the first insulator at one end of the columnar semiconductor. 1 metal, a second metal surrounding the first insulator at the other end of the columnar semiconductor, and the first insulation in a region sandwiched between the first metal and the second metal. A third metal surrounding the object, a second insulator formed between the first metal and the third metal, and formed between the second metal and the third metal. A third metal, a fourth metal that connects the first metal and one end of the columnar semiconductor, and a fifth metal that connects the second metal and the other end of the columnar semiconductor. It has a metal and the work function of the third metal is between 4.2 eV and 5.0 eV.

また、前記半導体は、シリコンであることを特徴とする。   Further, the semiconductor is silicon.

また、前記第１の金属と前記第２の金属の仕事関数は４．０ｅＶから４．２ｅＶの間であることを特徴とする。   The work function of the first metal and the second metal is between 4.0 eV and 4.2 eV.

また、前記第１の金属と前記第２の金属の仕事関数は５．０ｅＶから５．２ｅＶの間であることを特徴とする。   The work function of the first metal and the second metal is between 5.0 eV and 5.2 eV.

第２の発明の半導体装置は、柱状半導体と、前記柱状半導体を囲む第１の絶縁物と、前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、前記第１の金属と前記柱状半導体の一端とを接続する第４の金属と、前記第２の金属と前記柱状半導体の他方の一端とを接続する第５の金属を有することを特徴とする。   According to a second aspect of the present invention, there is provided a semiconductor device including: a columnar semiconductor; a first insulator surrounding the columnar semiconductor; a first metal surrounding the first insulator at one end of the columnar semiconductor; and the other of the columnar semiconductors. A second metal surrounding the first insulator at one end thereof, a third metal surrounding the first insulator in a region sandwiched between the first metal and the second metal, and A second insulator formed between the first metal and the third metal; a third insulator formed between the second metal and the third metal; It has the 4th metal which connects the 1st metal and the end of the columnar semiconductor, and the 5th metal which connects the 2nd metal and the other end of the columnar semiconductor.

ここで、前記柱状半導体と前記第１の金属との仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起される。   Here, carriers are induced at one end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the first metal, and the other of the columnar semiconductors due to a work function difference between the columnar semiconductor and the second metal. Carriers are induced at one end.

第３の発明の半導体装置は、柱状半導体と、前記柱状半導体の一端を取り囲む第１の絶縁物と、前記第１の絶縁物を取り囲む第１の金属と、前記柱状半導体の他方の一端を取り囲む第４の絶縁物と、前記第４の絶縁物を取り囲む第２の金属と、前記第１の金属と前記第２の金属とに挟まれた領域で前記柱状半導体を取り囲む第５の絶縁物と、前記第５の絶縁物を取り囲む第３の金属と、前記第１の金属と前記第３の金属の間に形成された第２の絶縁物と、前記第２の金属と前記第３の金属の間に形成された第３の絶縁物と、前記第１の金属と前記柱状半導体の一端を接続する第４の金属と、前記第２の金属と前記柱状半導体の他方の一端を接続する第５の金属を有することを特徴とする。   A semiconductor device according to a third aspect of the invention surrounds a columnar semiconductor, a first insulator surrounding one end of the columnar semiconductor, a first metal surrounding the first insulator, and the other end of the columnar semiconductor. A fourth insulator, a second metal surrounding the fourth insulator, and a fifth insulator surrounding the columnar semiconductor in a region sandwiched between the first metal and the second metal; , A third metal surrounding the fifth insulator, a second insulator formed between the first metal and the third metal, the second metal and the third metal A third insulator formed between the first metal and one end of the columnar semiconductor; a second metal connecting the second metal and the other end of the columnar semiconductor; It has 5 metals.

ここで、前記柱状半導体と前記第１の金属との仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起される。   Here, carriers are induced at one end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the first metal, and the other of the columnar semiconductors due to a work function difference between the columnar semiconductor and the second metal. Carriers are induced at one end.

第４の発明の半導体装置は、柱状半導体と、前記柱状半導体の一端の少なくとも一部を取り囲む第１の絶縁物と、前記第１の絶縁物の少なくとも一部を取り囲む第１の金属と、前記柱状半導体の他方の一端の少なくとも一部を取り囲む第４の絶縁物と、前記第４の絶縁物の少なくとも一部を取り囲む第２の金属と、前記第１の金属と前記第２の金属とに挟まれた領域で前記柱状半導体の少なくとも一部を取り囲む第５の絶縁物と、前記第５の絶縁物の少なくとも一部を取り囲む第３の金属と、前記第１の金属と前記第３の金属の間に形成された第２の絶縁物と、前記第２の金属と前記第３の金属の間に形成された第３の絶縁物と、前記第１の金属と前記柱状半導体の一端とを接続する第４の金属と、前記第２の金属と前記柱状半導体の他方の一端とを接続する第５の金属を有することを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor device including: a columnar semiconductor; a first insulator surrounding at least a part of one end of the columnar semiconductor; a first metal surrounding at least a part of the first insulator; A fourth insulator surrounding at least a part of the other end of the columnar semiconductor; a second metal surrounding at least a part of the fourth insulator; and the first metal and the second metal. A fifth insulator surrounding at least part of the columnar semiconductor in the sandwiched region; a third metal surrounding at least part of the fifth insulator; the first metal and the third metal; A second insulator formed between the second metal, the third insulator formed between the second metal and the third metal, and one end of the first metal and the columnar semiconductor. A fourth metal to be connected; the other of the second metal and the columnar semiconductor; And having a fifth metal connecting the end.

ここで、前記柱状半導体と前記第１の金属の仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起される。   Here, carriers are induced at one end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the first metal, and the other end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the second metal. Carriers are induced in

本発明によれば、トランジスタを金属とシリコンとの仕事関数差によって形成する構造を持つＳＧＴを提供することができる。   According to the present invention, an SGT having a structure in which a transistor is formed by a work function difference between metal and silicon can be provided.

前記柱状シリコンの一端の前記第１の絶縁物を取り囲む第１の金属と、前記柱状シリコンの他方の一端の前記第１の絶縁物を取り囲む第２の金属と、によって、金属とシリコンとの仕事関数差によってキャリアが誘起されるため、第１の金属と前記第２の金属の仕事関数が４．０ｅＶから４．２ｅＶの間であればｎ型トランジスタとなり、前記第１の金属と前記第２の金属の仕事関数が５．０ｅＶから５．２ｅＶの間であればｐ型トランジスタとなる。不純物が柱状シリコン内に存在しない状態でトランジスタ動作が可能となる。従って、拡散層を形成するための不純物注入が不要となる。   Work of metal and silicon by a first metal surrounding the first insulator at one end of the columnar silicon and a second metal surrounding the first insulator at the other end of the columnar silicon. Since carriers are induced by the functional difference, an n-type transistor is formed if the work function of the first metal and the second metal is between 4.0 eV and 4.2 eV, and the first metal and the second metal If the work function of the metal is between 5.0 eV and 5.2 eV, a p-type transistor is obtained. Transistor operation can be performed in a state where impurities are not present in the columnar silicon. Therefore, impurity implantation for forming the diffusion layer is not necessary.

（ａ）は本発明の一実施形態に係る半導体装置の斜視図鳥瞰図であり、（ｂ）は（ａ）のＸ−Ｘ’面での断面図である。(A) is a perspective view bird's-eye view of the semiconductor device which concerns on one Embodiment of this invention, (b) is sectional drawing in the X-X 'surface of (a). （ａ）は本発明の他の実施形態に係る半導体装置の斜視図であり、（ｂ）は（ａ）のＸ−Ｘ’面での断面図である。(A) is a perspective view of the semiconductor device which concerns on other embodiment of this invention, (b) is sectional drawing in the X-X 'surface of (a). （ａ）は本発明の更に他の実施形態に係る半導体装置の斜視図であり、（ｂ）は（ａ）のＸ−Ｘ’面での断面図である。(A) is a perspective view of the semiconductor device which concerns on other embodiment of this invention, (b) is sectional drawing in the X-X 'surface of (a).

以下、本発明の一実施形態に係る、ＳＧＴの構造を有する半導体装置を、図１を参照しながら説明する。   Hereinafter, a semiconductor device having an SGT structure according to an embodiment of the present invention will be described with reference to FIG.

基板１１０上に、１０17ｃｍ-3以下の不純物濃度の柱状シリコン１０１と、前記柱状シリコン１０１を囲む第１の絶縁物１０２と、前記柱状シリコン１０１の一端の前記第１の絶縁物１０２を取り囲む第１の金属１０４と、前記柱状シリコン１０１の他方の一端の前記第１の絶縁物１０２を取り囲む第２の金属１０５と、前記第１の金属１０４と前記第２の金属１０５とに挟まれた領域で前記第１の絶縁物１０２を取り囲む第３の金属１０３と、前記第１の金属１０４と前記第３の金属１０３との間に形成された第２の絶縁物１０７と、前記第２の金属１０５と前記第３の金属１０３との間に形成された第３の絶縁物１０６と、前記第１の金属１０４と前記柱状シリコン１０１の一端とを接続する第４の金属１０８と、前記第２の金属１０５と前記柱状シリコン１０１の他方の一端とを接続する第５の金属１０９を有し、前記第３の金属１０３の仕事関数は４．２ｅＶから５．０ｅＶの間であることを特徴とする。 A columnar silicon 101 having an impurity concentration of 10 17 cm −3 or less, a first insulator 102 surrounding the columnar silicon 101, and the first insulator 102 at one end of the columnar silicon 101 are surrounded on a substrate 110. Sandwiched between the first metal 104, the second metal 105 surrounding the first insulator 102 at the other end of the columnar silicon 101, and the first metal 104 and the second metal 105 A third metal 103 surrounding the first insulator 102 in a region; a second insulator 107 formed between the first metal 104 and the third metal 103; A third insulator 106 formed between the metal 105 and the third metal 103; a fourth metal 108 connecting the first metal 104 and one end of the columnar silicon 101; Two metals 105 And the other end of the columnar silicon 101, and the work function of the third metal 103 is between 4.2 eV and 5.0 eV.

第４の金属１０８により、前記第１の金属１０４と前記柱状シリコン１０１の一端とは同電位が印加される。   The same potential is applied to the first metal 104 and one end of the columnar silicon 101 by the fourth metal 108.

同様に、第５の金属１０９により、前記第２の金属１０５と前記柱状シリコン１０１の他方の一端とは同電位が印加される。   Similarly, the same potential is applied to the second metal 105 and the other end of the columnar silicon 101 by the fifth metal 109.

従って、柱状シリコン１０１の一端と他方の一端は、金属とシリコンとの仕事関数差によってキャリアが誘起されることとなる。   Therefore, at one end of the columnar silicon 101 and the other end, carriers are induced by the work function difference between the metal and silicon.

前記第１の金属１０４と前記第２の金属１０５の仕事関数が４．０ｅＶから４．２ｅＶの間であるとき、ｎ型シリコンの仕事関数４．０５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｎ型シリコンとして機能する。前記第１の金属１０４と前記第２の金属１０５は、例えば、タンタルとチタンの化合物（ＴａＴｉ）や窒化タンタル（ＴａＮ）が好ましい。   When the work functions of the first metal 104 and the second metal 105 are between 4.0 eV and 4.2 eV, the work function of the n-type silicon is in the vicinity of 4.05 eV. The other end functions as n-type silicon. For example, the first metal 104 and the second metal 105 are preferably a compound of tantalum and titanium (TaTi) or tantalum nitride (TaN).

前記第１の金属１０４と前記第２の金属１０５の仕事関数が５．０ｅＶから５．２ｅＶの間であるとき、ｐ型シリコンの仕事関数５．１５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｐ型シリコンとして機能する。前記第１の金属１０４と前記第２の金属１０５は、例えば、ルテニウム（Ｒｕ）や窒化チタン（ＴｉＮ）が好ましい。   When the work functions of the first metal 104 and the second metal 105 are between 5.0 eV and 5.2 eV, the work function of the p-type silicon is in the vicinity of 5.15 eV. The other end functions as p-type silicon. The first metal 104 and the second metal 105 are preferably, for example, ruthenium (Ru) or titanium nitride (TiN).

このとき、前記第３の金属１０３の仕事関数は４．２ｅＶから５．０ｅＶの間であると、半導体装置はエンハンスメント型トランジスタとして動作することができる。   At this time, when the work function of the third metal 103 is between 4.2 eV and 5.0 eV, the semiconductor device can operate as an enhancement type transistor.

上記により、前記第１の金属１０４と前記第２の金属１０５の仕事関数が４．０ｅＶから４．２ｅＶの間であるとき、ｎ型シリコンの仕事関数４．０５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｎ型シリコンのソース・ドレインとして機能し、柱状シリコン１０１の第３の金属１０３に取り囲まれる部分は、ｉ型シリコン、もしくは薄い濃度のｎ型シリコン、もしくは薄い濃度のｐ型シリコンとして機能する。従って、ｎ型トランジスタとして機能する。   As described above, when the work functions of the first metal 104 and the second metal 105 are between 4.0 eV and 4.2 eV, the work function of the n-type silicon is in the vicinity of 4.05 eV. One end and the other end of 101 function as a source / drain of n-type silicon, and a portion surrounded by the third metal 103 of the columnar silicon 101 is i-type silicon, or light n-type silicon, or light concentration It functions as p-type silicon. Therefore, it functions as an n-type transistor.

また、前記第１の金属１０４と前記第２の金属１０５の仕事関数が５．０ｅＶから５．２ｅＶの間であるとき、ｐ型シリコンの仕事関数５．１５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｐ型シリコンのソース・ドレインとして機能し、柱状シリコン１０１の第３の金属１０３に取り囲まれる部分は、ｉ型シリコン、もしくは薄い濃度のｎ型シリコン、もしくは薄い濃度のｐ型シリコンとして機能する。従って、ｐ型トランジスタとして機能する。   Further, when the work functions of the first metal 104 and the second metal 105 are between 5.0 eV and 5.2 eV, the work function of the p-type silicon is in the vicinity of 5.15 eV. One end and the other end of p-type silicon function as a source / drain of p-type silicon, and a portion surrounded by the third metal 103 of the columnar silicon 101 is i-type silicon, lightly-doped n-type silicon, or lightly-doped silicon. Functions as p-type silicon. Therefore, it functions as a p-type transistor.

以上により、不純物が柱状シリコン内に存在しない状態でトランジスタ動作が可能となる。従って、拡散層を形成するための不純物注入が不要となる。   As described above, transistor operation can be performed in a state where impurities are not present in the columnar silicon. Therefore, impurity implantation for forming the diffusion layer is not necessary.

以下、本発明の他の実施形態に係る、ＳＧＴの構造を有する半導体装置を、図２を参照しながら説明する。   Hereinafter, a semiconductor device having an SGT structure according to another embodiment of the present invention will be described with reference to FIG.

基板２１０上に、柱状半導体２０１と、前記柱状半導体２０１の一端の部分を囲む第１の絶縁物２１１と、前記第１の絶縁物２１１を囲む第１の金属２０４と、前記柱状半導体２０１の他端の部分を囲む第４の絶縁物２１２と、前記第４の絶縁物２１２を囲む第２の金属２０５と、前記第１の金属２０４と第２の金属２０５の間の前記柱状半導体２０１の部分を囲む第５の絶縁物２０２と、前記第５の絶縁物２０２を囲む第３の金属２０３と、前記第１の金属２０４と第３の金属２０３との間に配置される第２の絶縁物２０７と、前記第２の金属２０５と第３の金属２０３の間に配置される第３の絶縁物２０６と、前記第１の金属２０４と前記柱状半導体２０１の前記一端を接続する第４の金属２０８と、前記第５の金属２０５と前記柱状半導体２０１の前記他端とを接続する第５の金属２０９とが設けられている。   On the substrate 210, the columnar semiconductor 201, the first insulator 211 that surrounds one end portion of the columnar semiconductor 201, the first metal 204 that surrounds the first insulator 211, and the columnar semiconductor 201 A fourth insulator 212 surrounding an end portion; a second metal 205 surrounding the fourth insulator 212; and a portion of the columnar semiconductor 201 between the first metal 204 and the second metal 205 A fifth insulator 202 surrounding the first insulator 202, a third metal 203 surrounding the fifth insulator 202, and a second insulator disposed between the first metal 204 and the third metal 203. 207, a third insulator 206 disposed between the second metal 205 and the third metal 203, and a fourth metal connecting the first metal 204 and the one end of the columnar semiconductor 201. 208, the fifth metal 205 and the columnar half A fifth metal 209 for connecting the other end of the body 201 is provided.

以下、本発明の更に別の実施形態に係る、ＳＧＴの構造を有する半導体装置を、図３を参照しながら説明する。   Hereinafter, a semiconductor device having an SGT structure according to still another embodiment of the present invention will be described with reference to FIG.

基板３１０上に、柱状半導体３０１と、前記柱状半導体３０１の少なくとも一端の部分を囲む第１の絶縁物３１１と、前記第１の絶縁物３１１の少なくとも一部を囲む第１の金属３０４と、前記柱状半導体３０１の前記一端で前記柱状半導体３０１の少なくとも一部を囲む第４の絶縁物３１２と、前記第４の絶縁物３１２の少なくとも一部を囲む第２の金属３０５と、前記第１の金属３０４と第２の金属３０５の間の前記柱状半導体３０１の部分の少なくとも一部を囲む第４の絶縁物３０２と、前記第４の絶縁物３０２の少なくとも一部を囲む第３の金属３０３と、前記第１の金属３０４と第３の金属３０３の間に配置される第２の絶縁物３０７と、前記第２の金属３０５と第３の金属３０３の間に配置される第３の絶縁物３０６と、前記第１の金属３０４と前記柱状半導体３０１の第１端とを接続する第４の金属３０８と、前記第２の金属３０５と前記柱状半導体３０１の第２端とを接続する第５の金属３０９とが設けられている。   On the substrate 310, a columnar semiconductor 301, a first insulator 311 surrounding at least one end portion of the columnar semiconductor 301, a first metal 304 surrounding at least a part of the first insulator 311; A fourth insulator 312 surrounding at least a part of the columnar semiconductor 301 at the one end of the columnar semiconductor 301, a second metal 305 surrounding at least a part of the fourth insulator 312, and the first metal A fourth insulator 302 surrounding at least part of the portion of the columnar semiconductor 301 between 304 and the second metal 305; a third metal 303 surrounding at least part of the fourth insulator 302; A second insulator 307 disposed between the first metal 304 and the third metal 303, and a third insulator 306 disposed between the second metal 305 and the third metal 303. And the above A fourth metal 308 connecting the first metal 304 and the first end of the columnar semiconductor 301, and a fifth metal 309 connecting the second metal 305 and the second end of the columnar semiconductor 301. It has been.

なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。   It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

１０１，２０１，３０１ 柱状シリコン
１０２，２１１，３１１ 第１の絶縁物
１０３，２０３，３０３ 第３の金属
１０４，２０４，３０４ 第１の金属
１０５，２０５，３０５ 第２の金属
１０６，２０６，３０６ 第３の絶縁物
１０７，２０７，３０７ 第２の絶縁物
１０８，２０８，３０８ 第４の金属
１０９，２０９，３０９ 第５の金属
１１０，２１０，３１０ 基板 101, 201, 301 Columnar silicon 102, 211, 311 First insulator 103, 203, 303 Third metal 104, 204, 304 First metal 105, 205, 305 Second metal 106, 206, 306 Second Third insulator 107, 207, 307 Second insulator 108, 208, 308 Fourth metal 109, 209, 309 Fifth metal 110, 210, 310 Substrate

Claims (6)

１０17ｃｍ-3以下の不純物濃度の柱状半導体と、
前記柱状半導体を囲む第１の絶縁物と、
前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、
前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、
前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とは電気的に接続され、
前記第２の金属と前記柱状半導体の他方の一端とは電気的に接続され、
前記第３の金属の仕事関数は４.２ｅＶから５.０ｅＶの間であり、前記第１の金属と前記第２の金属の仕事関数は４.０ｅＶから４.２ｅＶの間であることを特徴とする半導体装置。 A columnar semiconductor having an impurity concentration of 10 17 cm −3 or less;
A first insulator surrounding the columnar semiconductor;
A first metal surrounding the first insulator at one end of the columnar semiconductor;
A second metal surrounding the first insulator at the other end of the columnar semiconductor;
A third metal surrounding the first insulator in a region sandwiched between the first metal and the second metal;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
The first metal and one end of the columnar semiconductor are electrically connected;
The second metal and the other end of the columnar semiconductor are electrically connected;
The work function of the third metal is between 4.2 eV and 5.0 eV, and the work functions of the first metal and the second metal are between 4.0 eV and 4.2 eV. A semiconductor device. １０17ｃｍ-3以下の不純物濃度の柱状半導体と、
前記柱状半導体を囲む第１の絶縁物と、
前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、
前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、
前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とは電気的に接続され、
前記第２の金属と前記柱状半導体の他方の一端とは電気的に接続され、
前記第３の金属の仕事関数は４.２ｅＶから５.０ｅＶの間であり、前記第１の金属と前記第２の金属の仕事関数は５.０ｅＶから５.２ｅＶの間であることを特徴とする半導体装置。 A columnar semiconductor having an impurity concentration of 10 17 cm −3 or less;
A first insulator surrounding the columnar semiconductor;
A first metal surrounding the first insulator at one end of the columnar semiconductor;
A second metal surrounding the first insulator at the other end of the columnar semiconductor;
A third metal surrounding the first insulator in a region sandwiched between the first metal and the second metal;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
The first metal and one end of the columnar semiconductor are electrically connected;
The second metal and the other end of the columnar semiconductor are electrically connected;
The work function of the third metal is between 4.2 eV and 5.0 eV, and the work functions of the first metal and the second metal are between 5.0 eV and 5.2 eV. A semiconductor device. 前記半導体は、シリコンであることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor is silicon. 柱状半導体と、
前記柱状半導体を囲む第１の絶縁物と、
前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、
前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、
前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とは電気的に接続され、
前記第２の金属と前記柱状半導体の他方の一端とは電気的に接続され、
を有し、
前記柱状半導体と前記第１の金属との仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起されることを特徴とする半導体装置。 Columnar semiconductors,
A first insulator surrounding the columnar semiconductor;
A first metal surrounding the first insulator at one end of the columnar semiconductor;
A second metal surrounding the first insulator at the other end of the columnar semiconductor;
A third metal surrounding the first insulator in a region sandwiched between the first metal and the second metal;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
The first metal and one end of the columnar semiconductor are electrically connected;
The second metal and the other end of the columnar semiconductor are electrically connected;
Have
Carriers are induced at one end of the columnar semiconductor by a work function difference between the columnar semiconductor and the first metal, and carriers at the other end of the columnar semiconductor are induced by a work function difference between the columnar semiconductor and the second metal. Is induced, a semiconductor device. 柱状半導体と、
前記柱状半導体の一端を取り囲む第１の絶縁物と、
前記第１の絶縁物を取り囲む第１の金属と、
前記柱状半導体の他方の一端を取り囲む第４の絶縁物と、
前記第４の絶縁物を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記柱状半導体を取り囲む第５の絶縁物と、
前記第５の絶縁物を取り囲む第３の金属と、
前記第１の金属と前記第３の金属の間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属の間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とは電気的に接続され、
前記第２の金属と前記柱状半導体の他方の一端とは電気的に接続され、
を有し、
前記柱状半導体と前記第１の金属との仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起されることを特徴とする半導体装置。 Columnar semiconductors,
A first insulator surrounding one end of the columnar semiconductor;
A first metal surrounding the first insulator;
A fourth insulator surrounding the other end of the columnar semiconductor;
A second metal surrounding the fourth insulator;
A fifth insulator surrounding the columnar semiconductor in a region sandwiched between the first metal and the second metal;
A third metal surrounding the fifth insulator;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
The first metal and one end of the columnar semiconductor are electrically connected;
The second metal and the other end of the columnar semiconductor are electrically connected;
Have
Carriers are induced at one end of the columnar semiconductor by a work function difference between the columnar semiconductor and the first metal, and carriers at the other end of the columnar semiconductor are induced by a work function difference between the columnar semiconductor and the second metal. Is induced, a semiconductor device. 柱状半導体と、
前記柱状半導体の一端の少なくとも一部を取り囲む第１の絶縁物と、
前記第１の絶縁物の少なくとも一部を取り囲む第１の金属と、
前記柱状半導体の他方の一端の少なくとも一部を取り囲む第４の絶縁物と、
前記第４の絶縁物の少なくとも一部を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記柱状半導体の少なくとも一部を取り囲む第５の絶縁物と、
前記第５の絶縁物の少なくとも一部を取り囲む第３の金属と、
前記第１の金属と前記第３の金属の間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属の間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とは電気的に接続され、
前記第２の金属と前記柱状半導体の他方の一端とは電気的に接続され、
を有し、
前記柱状半導体と前記第１の金属の仕事関数差によって前記柱状半導体の一端においてキャリアが誘起され、前記柱状半導体と前記第２の金属との仕事関数差によって前記柱状半導体の他方の一端においてキャリアが誘起されることを特徴とする半導体装置。 Columnar semiconductors,
A first insulator surrounding at least a part of one end of the columnar semiconductor;
A first metal surrounding at least a portion of the first insulator;
A fourth insulator surrounding at least a part of the other end of the columnar semiconductor;
A second metal surrounding at least a portion of the fourth insulator;
A fifth insulator surrounding at least a part of the columnar semiconductor in a region sandwiched between the first metal and the second metal;
A third metal surrounding at least a portion of the fifth insulator;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
The first metal and one end of the columnar semiconductor are electrically connected;
The second metal and the other end of the columnar semiconductor are electrically connected;
Have
Carriers are induced at one end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the first metal, and carriers are generated at the other end of the columnar semiconductor due to a work function difference between the columnar semiconductor and the second metal. A semiconductor device characterized by being induced.
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