JP5670605B2 - Semiconductor device - Google Patents
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- JP5670605B2 JP5670605B2 JP2014527412A JP2014527412A JP5670605B2 JP 5670605 B2 JP5670605 B2 JP 5670605B2 JP 2014527412 A JP2014527412 A JP 2014527412A JP 2014527412 A JP2014527412 A JP 2014527412A JP 5670605 B2 JP5670605 B2 JP 5670605B2
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- 239000004065 semiconductor Substances 0.000 title claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 86
- 239000002184 metal Substances 0.000 claims description 86
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 239000012212 insulator Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 38
- 239000010410 layer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 240000004050 Pentaglottis sempervirens Species 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本発明は半導体装置の製造方法、及び、半導体装置に関する。 The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
半導体集積回路、特にＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。このようなＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。このような問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲート電極が柱状半導体層を取り囲む構造のSurrounding Gate Transistor（以下、「ＳＧＴ」という。）が提案されている（例えば、特許文献１、特許文献２、特許文献３を参照）。 Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).
シリコン柱が細くなると、シリコンの密度は５×１０22個／ｃｍ3であるから、シリコン柱内に不純物を存在させることが難しくなってくる。When the silicon pillar is thinned, the density of silicon is 5 × 10 22 pieces / cm 3 , so that it becomes difficult for impurities to exist in the silicon pillar.
従来のＳＧＴでは、チャネル濃度を１０17ｃｍ-3以下と低不純物濃度とし、ゲート材料の仕事関数を変えることによってしきい値電圧を決定することが提案されている（例えば、特許文献４を参照）。In the conventional SGT, it is proposed to determine the threshold voltage by changing the work function of the gate material by setting the channel concentration to a low impurity concentration of 10 17 cm −3 or less (see, for example, Patent Document 4). ).
平面型ＭＯＳトランジスタにおいて、ＬＤＤ領域のサイドウォールが低濃度層と同一の導電型を有する多結晶シリコンにより形成され、ＬＤＤ領域の表面キャリアがその仕事関数差によって誘起され、酸化膜サイドウォールＬＤＤ型ＭＯＳトランジスタに比してＬＤＤ領域のインピーダンスが低減できることが示されている（例えば、特許文献５を参照）。その多結晶シリコンサイドウォールは電気的にゲート電極と絶縁されていることが示されている。また図中には多結晶シリコンサイドウォールとソース・ドレインとは層間絶縁膜により絶縁していることが示されている。 In the planar MOS transistor, the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (see, for example, Patent Document 5). The polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.
そこで、本発明は、トランジスタを金属と半導体との仕事関数差によって形成する構造を持つＳＧＴを提供することを目的とする。 Therefore, an object of the present invention is to provide an SGT having a structure in which a transistor is formed by a work function difference between a metal and a semiconductor.
本発明の半導体装置は、１０17ｃｍ-3以下の不純物濃度の柱状半導体と、前記柱状半導体を囲む第１の絶縁物と、前記柱状半導体の一端の前記第１の絶縁物を取り囲む第１の金属と、前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、前記第１の金属と前記柱状半導体の一端とを接続する第４の金属と、前記第２の金属と前記柱状半導体の他方の一端とを接続する第５の金属を有し、前記第３の金属の仕事関数は４．２ｅＶから５．０ｅＶの間であることを特徴とする。The semiconductor device of the present invention includes a columnar semiconductor having an impurity concentration of 10 17 cm −3 or less, a first insulator surrounding the columnar semiconductor, and a first insulator surrounding the first insulator at one end of the columnar semiconductor. The first insulator in a region sandwiched between the metal, the second metal surrounding the first insulator at the other end of the columnar semiconductor, and the first metal and the second metal. An enclosing third metal; a second insulator formed between the first metal and the third metal; and formed between the second metal and the third metal. A third metal, a fourth metal that connects the first metal and one end of the columnar semiconductor, and a fifth metal that connects the second metal and the other end of the columnar semiconductor. And the work function of the third metal is between 4.2 eV and 5.0 eV.
また、前記半導体は、シリコンであることを特徴とする。 Further, the semiconductor is silicon.
また、前記第１の金属と前記第２の金属の仕事関数は４．０ｅＶから４．２ｅＶの間であることを特徴とする。 The work function of the first metal and the second metal is between 4.0 eV and 4.2 eV.
また、前記第１の金属と前記第２の金属の仕事関数は５．０ｅＶから５．２ｅＶの間であることを特徴とする。 The work function of the first metal and the second metal is between 5.0 eV and 5.2 eV.
本発明によれば、トランジスタを金属とシリコンとの仕事関数差によって形成する構造を持つＳＧＴを提供することができる。 According to the present invention, an SGT having a structure in which a transistor is formed by a work function difference between metal and silicon can be provided.
前記柱状シリコンの一端の前記第１の絶縁物を取り囲む第１の金属と、前記柱状シリコンの他方の一端の前記第１の絶縁物を取り囲む第２の金属と、によって、金属とシリコンとの仕事関数差によってキャリアが誘起されるため、第１の金属と前記第２の金属の仕事関数が４．０ｅＶから４．２ｅＶの間であればｎ型トランジスタとなり、前記第１の金属と前記第２の金属の仕事関数が５．０ｅＶから５．２ｅＶの間であればｐ型トランジスタとなる。不純物が柱状シリコン内に存在しない状態でトランジスタ動作が可能となる。従って、拡散層を形成するための不純物注入が不要となる。 Work of metal and silicon by a first metal surrounding the first insulator at one end of the columnar silicon and a second metal surrounding the first insulator at the other end of the columnar silicon. Since carriers are induced by the functional difference, an n-type transistor is formed if the work function of the first metal and the second metal is between 4.0 eV and 4.2 eV, and the first metal and the second metal If the work function of the metal is between 5.0 eV and 5.2 eV, a p-type transistor is obtained. Transistor operation can be performed in a state where impurities are not present in the columnar silicon. Therefore, impurity implantation for forming the diffusion layer is not necessary.
以下、本発明の実施形態に係る、ＳＧＴの構造を有する半導体装置を、図１を参照しながら説明する。 Hereinafter, a semiconductor device having an SGT structure according to an embodiment of the present invention will be described with reference to FIG.
基板１１０上に、１０17ｃｍ-3以下の不純物濃度の柱状シリコン１０１と、前記柱状シリコン１０１を囲む第１の絶縁物１０２と、前記柱状シリコン１０１の一端の前記第１の絶縁物１０２を取り囲む第１の金属１０４と、前記柱状シリコン１０１の他方の一端の前記第１の絶縁物１０２を取り囲む第２の金属１０５と、前記第１の金属１０４と前記第２の金属１０５とに挟まれた領域で前記第１の絶縁物１０２を取り囲む第３の金属１０３と、前記第１の金属１０４と前記第３の金属１０３との間に形成された第２の絶縁物１０７と、前記第２の金属１０５と前記第３の金属１０３との間に形成された第３の絶縁物１０６と、前記第１の金属１０４と前記柱状シリコン１０１の一端とを接続する第４の金属１０８と、前記第２の金属１０５と前記柱状シリコン１０１の他方の一端とを接続する第５の金属１０９を有し、前記第３の金属１０３の仕事関数は４．２ｅＶから５．０ｅＶの間であることを特徴とする。A
第４の金属１０８により、前記第１の金属１０４と前記柱状シリコン１０１の一端とは同電位が印加される。
The same potential is applied to the
第５の金属１０９により、前記第２の金属１０５と前記柱状シリコン１０１の他方の一端とは同電位が印加される。
The same potential is applied to the
従って、柱状シリコン１０１の一端と他方の一端は、金属とシリコンとの仕事関数差によってキャリアが誘起されることとなる。
Therefore, at one end of the
前記第１の金属１０４と前記第２の金属１０５の仕事関数が４．０ｅＶから４．２ｅＶの間であるとき、ｎ型シリコンの仕事関数４．０５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｎ型シリコンとして機能する。前記第１の金属１０４と前記第２の金属１０５は、例えば、タンタルとチタンの化合物（ＴａＴｉ）や窒化タンタル（ＴａＮ）が好ましい。
When the work functions of the
前記第１の金属１０４と前記第２の金属１０５の仕事関数が５．０ｅＶから５．２ｅＶの間であるとき、ｐ型シリコンの仕事関数５．１５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｐ型シリコンとして機能する。前記第１の金属１０４と前記第２の金属１０５は、例えば、ルテニウム（Ｒｕ）や窒化チタン（ＴｉＮ）が好ましい。
When the work functions of the
このとき、前記第３の金属１０３の仕事関数は４．２ｅＶから５．０ｅＶの間であると、エンハンスメント型として動作することができる。
At this time, when the work function of the
上記により、前記第１の金属１０４と前記第２の金属１０５の仕事関数が４．０ｅＶから４．２ｅＶの間であるとき、ｎ型シリコンの仕事関数４．０５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｎ型シリコンのソースドレインとして機能し、柱状シリコン１０１の第３の金属１０３に取り囲まれる部分は、ｉ型シリコン、もしくは薄い濃度のｎ型シリコン、もしくは薄い濃度のｐ型シリコンとして機能する。従って、ｎ型トランジスタとして機能する。
As described above, when the work functions of the
また、前記第１の金属１０４と前記第２の金属１０５の仕事関数が５．０ｅＶから５．２ｅＶの間であるとき、ｐ型シリコンの仕事関数５．１５ｅＶの近傍であるため、柱状シリコン１０１の一端と他方の一端は、ｐ型シリコンのソースドレインとして機能し、柱状シリコン１０１の第３の金属１０３に取り囲まれる部分は、ｉ型シリコン、もしくは薄い濃度のｎ型シリコン、もしくは薄い濃度のｐ型シリコンとして機能する。従って、ｐ型トランジスタとして機能する。
Further, when the work functions of the
以上により、不純物が柱状シリコン内に存在しない状態でトランジスタ動作が可能となる。従って、拡散層を形成するための不純物注入が不要となる。 As described above, transistor operation can be performed in a state where impurities are not present in columnar silicon. Therefore, impurity implantation for forming the diffusion layer is not necessary.
なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。 It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.
１０１．柱状シリコン
１０２．第１の絶縁物
１０３．第３の金属
１０４．第１の金属
１０５．第２の金属
１０６．第３の絶縁物
１０７．第２の絶縁物
１０８．第４の金属
１０９．第５の金属
１１０．基板101.
Claims (4)
前記柱状半導体を取り囲む第１の絶縁物と、
前記柱状半導体の一端の前記第１絶縁物を取り囲む第１の金属と、
前記柱状半導体の他方の一端の前記第１の絶縁物を取り囲む第２の金属と、
前記第１の金属と前記第２の金属とに挟まれた領域で前記第１の絶縁物を取り囲む第３の金属と、
前記第１の金属と前記第３の金属との間に形成された第２の絶縁物と、
前記第２の金属と前記第３の金属との間に形成された第３の絶縁物と、
前記第１の金属と前記柱状半導体の一端とを接続する第４の金属と、
前記第２の金属と前記柱状半導体の他方の一端を接続する第５の金属を有し、
前記第３の金属の仕事関数は４.２ｅＶから５.０ｅＶの間であることを特徴とする半導体装置。 A columnar semiconductor having an impurity concentration of 10 17 cm −3 or less;
A first insulator surrounding the columnar semiconductor;
A first metal surrounding the first insulator at one end of the columnar semiconductor;
A second metal surrounding the first insulator at the other end of the columnar semiconductor;
A third metal surrounding the first insulator in a region sandwiched between the first metal and the second metal;
A second insulator formed between the first metal and the third metal;
A third insulator formed between the second metal and the third metal;
A fourth metal connecting the first metal and one end of the columnar semiconductor;
A fifth metal connecting the second metal and the other end of the columnar semiconductor;
The semiconductor device according to claim 3, wherein the work function of the third metal is between 4.2 eV and 5.0 eV.
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| US9496360B2 (en) | 2013-01-25 | 2016-11-15 | Unisantis Electronics Singapore Pte. Ltd. | Vertical transistor with source/drain regions induced by work-function differences between a semiconductor pillar body and surrounding metal electrodes |
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| JP6200103B2 (en) | 2015-10-15 | 2017-09-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． | Semiconductor device |
| WO2017085788A1 (en) * | 2015-11-17 | 2017-05-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and semiconductor device manufacturing method |
| JP6317507B2 (en) * | 2017-05-24 | 2018-04-25 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． | Semiconductor device |
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| US9496360B2 (en) | 2013-01-25 | 2016-11-15 | Unisantis Electronics Singapore Pte. Ltd. | Vertical transistor with source/drain regions induced by work-function differences between a semiconductor pillar body and surrounding metal electrodes |
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