CN1063580C - 制造具有多层互连的半导体器件的方法 - Google Patents

制造具有多层互连的半导体器件的方法 Download PDF

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Publication number
CN1063580C
CN1063580C CN95115252A CN95115252A CN1063580C CN 1063580 C CN1063580 C CN 1063580C CN 95115252 A CN95115252 A CN 95115252A CN 95115252 A CN95115252 A CN 95115252A CN 1063580 C CN1063580 C CN 1063580C
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CN
China
Prior art keywords
insulating film
substrate
forming
interconnection
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN95115252A
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English (en)
Chinese (zh)
Other versions
CN1127935A (zh
Inventor
落合昭彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of CN1127935A publication Critical patent/CN1127935A/zh
Application granted granted Critical
Publication of CN1063580C publication Critical patent/CN1063580C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
CN95115252A 1994-07-26 1995-07-26 制造具有多层互连的半导体器件的方法 Expired - Fee Related CN1063580C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP194873/94 1994-07-26
JP6194873A JPH0845935A (ja) 1994-07-26 1994-07-26 多層配線の形成方法
JP194873/1994 1994-07-26

Publications (2)

Publication Number Publication Date
CN1127935A CN1127935A (zh) 1996-07-31
CN1063580C true CN1063580C (zh) 2001-03-21

Family

ID=16331734

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95115252A Expired - Fee Related CN1063580C (zh) 1994-07-26 1995-07-26 制造具有多层互连的半导体器件的方法

Country Status (4)

Country Link
US (1) US5589419A (enExample)
JP (1) JPH0845935A (enExample)
KR (1) KR960005951A (enExample)
CN (1) CN1063580C (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3512496B2 (ja) * 1994-11-25 2004-03-29 株式会社半導体エネルギー研究所 Ｓｏｉ型半導体集積回路の作製方法
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
KR100702119B1 (ko) * 2001-06-30 2007-03-30 주식회사 하이닉스반도체 반도체소자의 본딩패드 및 그 제조방법
JP4651924B2 (ja) * 2003-09-18 2011-03-16 シャープ株式会社 薄膜半導体装置および薄膜半導体装置の製造方法
US7285477B1 (en) * 2006-05-16 2007-10-23 International Business Machines Corporation Dual wired integrated circuit chips
FR2910704A1 (fr) * 2007-04-05 2008-06-27 Commissariat Energie Atomique Procede de realisation d'un dispositif a circuit integre interconnecte

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0575283A2 (en) * 1992-06-17 1993-12-22 International Business Machines Corporation Advanced silicon on oxide semiconductor device structure for BICMOS integrated circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450543A (en) * 1987-08-21 1989-02-27 Nec Corp Manufacture of semiconductor device
US5168078A (en) * 1988-11-29 1992-12-01 Mcnc Method of making high density semiconductor structure
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
EP0537677B1 (en) * 1991-10-16 1998-08-19 Sony Corporation Method of forming an SOI structure with a DRAM
US5496764A (en) * 1994-07-05 1996-03-05 Motorola, Inc. Process for forming a semiconductor region adjacent to an insulating layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0575283A2 (en) * 1992-06-17 1993-12-22 International Business Machines Corporation Advanced silicon on oxide semiconductor device structure for BICMOS integrated circuits

Also Published As

Publication number Publication date
JPH0845935A (ja) 1996-02-16
US5589419A (en) 1996-12-31
CN1127935A (zh) 1996-07-31
KR960005951A (enExample) 1996-02-23

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