CN106332437A - Electroplating method - Google Patents
Electroplating method Download PDFInfo
- Publication number
- CN106332437A CN106332437A CN201510362044.3A CN201510362044A CN106332437A CN 106332437 A CN106332437 A CN 106332437A CN 201510362044 A CN201510362044 A CN 201510362044A CN 106332437 A CN106332437 A CN 106332437A
- Authority
- CN
- China
- Prior art keywords
- electrodepositable
- district
- perforation
- circuit board
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
Abstract
The invention discloses an electroplating method for electroplating a circuit board. The circuit board has a first electroplating region and a second electroplating region, wherein the area of the first electroplating region is smaller than that of the second electroplating region. The electroplating method comprises: an accompanying electroplating plate having a first through hole and a second through hole is provided, wherein the accompanying electroplating plate also has a third electroplating region and a fourth electroplating region and the two regions encircle the first through hole and the second through hole respectively, a first minimum width is formed between the inner edge and the outer edge of the third electroplating region and a second minimum width smaller than the first minimum width is formed between the inner edge and the outer edge of the fourth electroplating region; the accompanying electroplating plate is placed on the circuit board, so that the first electroplating region and the second electroplating region are arranged in the first through hole and the second through hole; and conducting material electroplating on the third electroplating region and the fourth electroplating region is carried out and conducting material electroplating on first electroplating region and the second electroplating region is carried out by the first through hole and the second through hole.
Description
Technical field
The present invention relates to a kind of electro-plating method.
Background technology
Existing circuit board is the main carriers of electric equipment products.Need complicated conduction on cloth on circuit boards
Circuit and various electronic component, make to be reached the function of expection running by electric current, the circulation of various signal.
For part electronic equipment, it is necessary to by bigger current loading (such as, more than 100A) and temperature
Lifting range must control the demand below 20 degree, therefore circuit board domestic demand imbed 200 microns with
On copper thick.
But, if the size in the electrodepositable district on circuit board differs, will be unable to dimension the most after plating
The thickness evenness of the conductive material in Chi Ge electrodepositable district.Specifically, refer to Fig. 4, it is for painting
Show existing circuit board 6 structural representation after plating.As shown in Figure 4, existing base material 60 has
There are two perforation 600a, 600b, and the area that the area of perforation 600a is less than perforation 600b.In this structure
Under configuration, at follow-up two perforation 600a, 600b that conductive material 4 is plated on by circuit layer 62
Time interior, will be more than by bigger the wearing of area by the density of electric fluxline of the less perforation 600a of area
The density of electric fluxline of hole 600b.Therefore, this will result in the conductive material 4 being plated in perforation 600a
Thickness is more than the thickness of the conductive material 4 being plated in perforation 600b.
Summary of the invention
In view of this, a purpose of the present invention is to propose a kind of electro-plating method solving the problems referred to above.
In order to achieve the above object, according to one embodiment of the present invention, a kind of electro-plating method is in order to electroplate
Circuit board.Circuit board has the first electrodepositable district and the second electrodepositable district.The area in the first electrodepositable district
Area less than the second electrodepositable district.Electro-plating method comprises: provides and accompanies plating plate, wherein accompanies plating plate to have the
One perforation and the second perforation, also have the 3rd electrodepositable district and the 4th electrodepositable district respectively around first
Perforation and the second perforation, have the first minimum widith between outer rim and the inner edge in the 3rd electrodepositable district, and the 4th
There is between outer rim and the inner edge in electrodepositable district the second minimum widith, and the first minimum widith is more than second
Minimum widith；Placement accompanies plating plate on circuit board so that the first electrodepositable district is with the second electrodepositable district respectively
Within being positioned at the first perforation and the second perforation；And electroplating of conductive material can to the 3rd electrodepositable district and the 4th
Electroplating region, and respectively via the first perforation with the second perforation electroplating of conductive material to the first electrodepositable district and the
Two electrodepositable districts.
In one or more embodiment of the present invention, above-mentioned plating plate of accompanying comprises electric-conductor and insulation
Part.Dielectric insulator segments ground coated with conductive part.3rd electrodepositable district forms electric-conductor quilt with the 4th electrodepositable district
The surface that insulating part is exposed.
In one or more embodiment of the present invention, the material of above-mentioned insulating part comprises polytetrafluoroethyl-ne
Alkene.
In one or more embodiment of the present invention, above-mentioned circuit board comprises base material and circuit layer.
Base material has contrary first surface and second surface, also has and runs through first surface and second surface
3rd perforation and the 4th perforation.First surface is towards accompanying plating plate.Circuit layer is arranged at second surface, and
Cover the opening that the 3rd perforation is positioned on second surface with the 4th perforation so that the 3rd perforation and the 4th perforation
Form the first electrodepositable district and the second electrodepositable district respectively.
In one or more embodiment of the present invention, on the direction being parallel to first surface, the 3rd can
The inner edge of electroplating region is at least separated by a minimum range with the 3rd perforation, and the inner edge in the 4th electrodepositable district and the
Four perforation are at least separated by above-mentioned minimum range.
In one or more embodiment of the present invention, above-mentioned minimum range is-300～300 millimeters.
In one or more embodiment of the present invention, the area in the 3rd above-mentioned electrodepositable district is more than the 4th
The area in electrodepositable district.
In one or more embodiment of the present invention, the area and the 3rd in the first above-mentioned electrodepositable district can
The sum of the area of electroplating region, the area in the substantially equal to second electrodepositable district and the area in the 4th electrodepositable district
Sum.
In one or more embodiment of the present invention, plating plate step bag on circuit board is accompanied in above-mentioned placement
Contain: make the 3rd electrodepositable district and the 4th electrodepositable district back to circuit board.
In one or more embodiment of the present invention, electro-plating method also comprises: removes and accompanies plating plate；And
Reclaim and be plated on the 3rd electrodepositable district and the conductive material in the 4th electrodepositable district.
In sum, the electro-plating method of the present invention is to utilize to accompany plating plate to electroplate together with circuit board.Tool
For body, the electro-plating method of the present invention is to utilize to accompany the electrodepositable district on plating plate respectively may be used on circuit board to compensate
Area discrepancy between electroplating region so that when electroplating by the electric power in circuit board Shang Ge electrodepositable district
Line density is close, and the thickness of the conductive material electroplated in holding circuit Ban Shangge electrodepositable district is uniform
Property.
The above only in order to illustrate problem that the present invention to be solved, solve problem technological means and
Its effect produced etc., the detail of the present invention is by embodiment below and relevant accompanying drawing
It is discussed in detail.
Accompanying drawing explanation
Fig. 1 is the flow chart of the electro-plating method of an embodiment of the present invention；
Fig. 2 is the top view accompanying plating plate to be positioned on circuit board of an embodiment of the present invention；
Fig. 3 A is circuit board in Fig. 2 and accompany the plating plate profile along line segment 3A-3A ', wherein circuit
Plate is not yet plated with accompanying plating plate；
Fig. 3 B is circuit board in Fig. 3 A and accompany another profile of plating plate, wherein circuit board with accompany plating
Plate is plated；
Fig. 3 C is the profile of circuit board finished product；
Fig. 4 is existing circuit board structural representation after plating.
Symbol description
1,6: circuit board
1 ': circuit board finished product
10,60: base material
100: first surface
102: second surface
104: the three perforation
106: the four perforation
12: the first circuit layers
14: second circuit layer
2: accompany plating plate
20: electric-conductor
22: insulating part
24: the first perforation
26: the second perforation
3: resist
4: conductive material
5a: power supply
5b: the first electrode
5c: the second electrode
600a, 600b: perforation
62: circuit layer
D: minimum range
W1: the first minimum widith
W2: the second minimum widith
Z1: the first electrodepositable district
Z2: the second electrodepositable district
Z3: the three electrodepositable district
Z4: the four electrodepositable district
S101～S105: step
Detailed description of the invention
Multiple embodiments of the present invention, as clearly stated, many practices will be disclosed below with accompanying drawing
On details will be explained in the following description.It should be appreciated, however, that the details in these practices is not
Application is to limit the present invention.It is to say, in some embodiments of the present invention, thin in these practices
Joint is non-essential.Additionally, for the sake of simplifying accompanying drawing, some existing usual structures and element are at accompanying drawing
Middle will illustrate it in the way of simple signal.
Refer to Fig. 1 to Fig. 3 C.Fig. 1 is the flow process of the electro-plating method illustrating an embodiment of the present invention
Figure.Fig. 2 is that the plating plate 2 of accompanying illustrating an embodiment of the present invention is positioned over the top view on circuit board 1.
Fig. 3 A is to illustrate circuit board 1 in Fig. 2 and accompany the plating plate 2 profile along line segment 3A-3A ', wherein
Circuit board 1 is not yet plated with accompanying plating plate 2.Fig. 3 B is that the circuit board 1 in Fig. 3 A plates plate 2 with accompanying
Another profile, wherein circuit board 1 with accompany plating plate 2 be plated.Fig. 3 C is for illustrating circuit board
The profile of product 1 '.
As it is shown in figure 1, and coordinate reference Fig. 2 Yu Fig. 3 A, in the present embodiment, electro-plating method use
With electroplating circuit board 1.Circuit board 1 has the first electrodepositable district Z1 and the second electrodepositable district Z2.The
The area of the one electrodepositable district Z1 area less than the second electrodepositable district Z2.Electro-plating method comprises step S101
To step S105, as follows.
Step S101: provide and accompany plating plate 2, wherein accompanies plating plate 2 to have the first perforation 24 and second and wears
Hole 26, also has the 3rd electrodepositable district Z3 and the 4th electrodepositable district Z4 respectively around the first perforation 24
With the second perforation 26, between outer rim and the inner edge of the 3rd electrodepositable district Z3, there is the first minimum widith W1,
There is between outer rim and the inner edge of the 4th electrodepositable district Z4 the second minimum widith W2, and the first minimum
Width W1 is more than the second minimum widith W2 (see Fig. 2).
Specifically, as shown in Figure 3A, in the present embodiment, plating plate 2 is accompanied to comprise electric-conductor 20
And insulating part 22.Insulating part 22 partly coated with conductive part 20.Therefore, Fig. 3 A～Fig. 3 C leads
The surface that exposed by insulating part 22 of electricity part 20, i.e. forms the 3rd electrodepositable district Z3 in Fig. 2 and the
Four electrodepositable district Z4 (because only that the surface that electric-conductor 20 is exposed by insulating part 22 just can be plated).
In one embodiment, the material of insulating part 22 comprises politef, but the present invention not with
This is limited, and the art tool usually intellectual can flexibly change and uses other to have the material of identical characteristics
Material.
It addition, in the present embodiment, circuit board 1 comprises base material the 10, first circuit layer 12 and
Two circuit layers 14.Base material 10 has contrary first surface 100 and second surface 102, also has
Run through the 3rd perforation 104 and the 4th perforation 106 of first surface 100 and second surface 102.First
Circuit layer 12 is arranged on the first surface 100 of base material 10, and exposes the 3rd perforation 104 and the 4th
Perforation 106 is positioned at the opening on second surface 102.Second circuit layer 14 is arranged at the second of base material 10
Surface 102, and cover the 3rd perforation 104 and bore a hole with the 4th and 106 be positioned at the opening on second surface 102.
The 3rd perforation 104 and the 4th perforation 106 in Fig. 3 A form the first electrodepositable district Z1 in Fig. 2 respectively
With the second electrodepositable district Z2.
It is noted that when carrying out plating step (i.e. step S103), in order to make conductive material 4 the most electric
It is plated in the 3rd perforation 104 and the 4th perforation 106 of circuit board 1, can be in advance at the position being not intended to plating
(on the i.e. first circuit layer 12 and second circuit layer 14) coating resist 3, and expose the position to be electroplated (i.e.
First perforation 24 and the second perforation 26 of base material 10), as shown in Figure 3A.And owing to resist 3 stops
Reason, the most controlled conductive material 4 processed only can be by first in follow-up plating step (i.e. step S103)
Perforation 24 and the second perforation 26 intersection with second circuit layer 14 respectively start to be electroplated to base material 10
First surface 100, as shown in Figure 3 B.
Step S102: place and accompany plating plate 2 on circuit board 1 so that first on circuit board 1 can electricity
Within plating district Z1 and the second electrodepositable district Z2 lays respectively at the first perforation 24 and the second perforation 26.
In this step, can make further to accompany the 3rd electrodepositable district Z3 on plating plate 2 and the 4th electrodepositable
District Z4 is back to circuit board 1, and makes the first surface 100 of base material 10 towards accompanying plating plate 2.
In one embodiment, on the direction being parallel to first surface 100, the 3rd electrodepositable district Z3
Inner edge be at least separated by minimum range D with the 3rd perforation 104, and the inner edge of the 4th electrodepositable district Z4 with
4th perforation 106 is at least separated by minimum range D (see Fig. 2).In one embodiment, above-mentioned minimum
Distance D is-300～300 millimeters.Wherein, when minimum range D be on the occasion of time, represent and be parallel to the
On the direction on one surface 100, the inner edge of the 3rd electrodepositable district Z3 be positioned at the 3rd perforation 104 outer rim it
Outward, and the inner edge of the 4th electrodepositable district Z4 is positioned at outside the outer rim of the 4th perforation 106；Work as minimum range
When D is negative value, representing on the direction being parallel to first surface 100, the 3rd electrodepositable district Z3's is interior
Within edge is positioned at the outer rim of the 3rd perforation 104, and the inner edge of the 4th electrodepositable district Z4 is positioned at the 4th perforation
Within the outer rim of 106.Further, when above-mentioned minimum range D is closer to 0, electroplating thickness uniformity is more
Good.
Step S103: electroplating of conductive material 4 to the 3rd electrodepositable district Z3 and the 4th electrodepositable district Z4, and
Respectively via first perforation 24 with second perforation 26 electroplating of conductive material 4 to the first electrodepositable district Z1 and
Second electrodepositable district Z2.
Reality perform plating step time, can by the first electrode 5b (such as anode) opposing circuit board 1 with accompany
Plating plate 2 arranges and (that is, makes the first electrodepositable district Z1 on circuit board 1 and the second electrodepositable district Z2 and accompany
The 3rd electrodepositable district Z3 on plating plate 2 and the 4th electrodepositable district Z4 is towards the first electrode 5b), then by the
Two electrode 5c (such as negative electrode) are electrically connected to the second circuit layer 14 of circuit board 1 and plate leading of plate 2 with accompanying
Electricity part 20, i.e. may utilize the electric lines of force that power supply 5a produces between the first electrode 5b and the second electrode 5c,
And the first electrodepositable district Z1 that conductive material 4 can be electroplated on circuit board 1 under the effect of electric lines of force
With the second electrodepositable district Z2 and accompany plating plate 2 on the 3rd electrodepositable district Z3 and the 4th electrodepositable district Z4.
Further, Fig. 2 with Fig. 3 B should be clear from, by accompanying the 3rd electrodepositable district Z3 on plating plate 2
The first electrodepositable district Z1 on circuit board 1 and the second electrodepositable district is compensated respectively with the 4th electrodepositable district Z4
Area discrepancy between Z2, can make can by the first electrodepositable district Z1 and second when electroplating
The density of electric fluxline of electroplating region Z2 is close, for maintaining the first electrodepositable district Z1 and the second electrodepositable district
The thickness evenness of the conductive material 4 electroplated in Z2.
Furthermore, it is understood that for leading of being electroplated in making the first electrodepositable district Z1 and the second electrodepositable district Z2
The thickness of electric material 4 is more uniform, in one embodiment, can design and make to accompany the 3rd on plating plate 2 can
The area of the electroplating region Z3 area more than the 4th electrodepositable district Z4.In one embodiment, one can be entered again
Step design make the area of the area of the first electrodepositable district Z1 and the 3rd electrodepositable district Z3 and, essence is first-class
In the area of the second electrodepositable district Z2 and the 4th electrodepositable district Z4 area and.
Step S104: remove and accompany plating plate 2.
After completing plating step (i.e. step S103) and removing and accompanying plating plate 2, stripping can be carried out again
(stripping) processing technology, resist 3 to be removed, i.e. can get circuit board finished product 1 ', such as Fig. 3 C institute
Show.
Step S105: reclaim and be plated on the conduction on the 3rd electrodepositable district Z3 and the 4th electrodepositable district Z4
Material 4.
After completing plating step (i.e. step S103), being plated on the 3rd electrodepositable district Z3 and the 4th can
Conductive material 4 on electroplating region Z4 can be peeled off easily, and recyclable and be recycled and reused for follow-up electricity
In plating processing technology, therefore can save the cost of plated material.
By above for the detailed description of detailed description of the invention of the present invention, it is apparent that the present invention
Electro-plating method is to utilize to accompany plating plate to electroplate together with circuit board.Specifically, the plating side of the present invention
Method be utilize accompany plating plate on electrodepositable district to compensate the area discrepancy between circuit board Shang Ge electrodepositable district,
Make when electroplating close by the density of electric fluxline in circuit board Shang Ge electrodepositable district, be used for maintaining electricity
The thickness evenness of the conductive material electroplated in Ban Shangge electrodepositable district, road.
Although disclosing the present invention in conjunction with embodiment of above, but it not being in order to limit the present invention, appoint
What skilled person, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations,
Therefore protection scope of the present invention should be with being as the criterion that the claim enclosed is defined.
Claims (10)
1. an electro-plating method, in order to electroplate a circuit board, this circuit board have the first electrodepositable district and
Second electrodepositable district, the area in this first electrodepositable district is less than the area in this second electrodepositable district, this plating
Method comprises:
Thering is provided one to accompany plating plate, wherein this accompanies plating plate to have the first perforation and the second perforation, also has the 3rd
Electrodepositable district and the 4th electrodepositable district are respectively around this first perforation and this second perforation, and the 3rd can electricity
Between outer rim and the inner edge in plating district, there is one first minimum widith, the outer rim in the 4th electrodepositable district and inner edge
Between there is one second minimum widith, and this first minimum widith is more than this second minimum widith；
Placing this accompanies plating plate on this circuit board so that this first electrodepositable district is distinguished with this second electrodepositable
Within not being positioned at this first perforation and this second perforation；And
Electroplate a conductive material to the 3rd electrodepositable district and the 4th electrodepositable district, and respectively via this
One perforation electroplates this conductive material to this first electrodepositable district and this second electrodepositable district with this second perforation.
2. electro-plating method as claimed in claim 1, wherein this accompanies plating plate to comprise:
Electric-conductor；And
Insulating part, is partly coated with this electric-conductor, wherein the 3rd electrodepositable district and the 4th electrodepositable district
Form the surface that this electric-conductor is exposed by this insulating part.
3. electro-plating method as claimed in claim 2, wherein the material of this insulating part comprises politef.
4. electro-plating method as claimed in claim 1, wherein this circuit board comprises:
Base material, has contrary first surface and second surface, also has and runs through this first surface and be somebody's turn to do
3rd perforation of second surface and the 4th perforation, wherein this first surface accompanies plating plate towards this；And
Circuit layer, is arranged at this second surface, and cover the 3rd perforation and the 4th perforation be positioned at this
Opening on two surfaces so that the 3rd perforation with the 4th perforation formed respectively this first electrodepositable district with
This second electrodepositable district.
5. electro-plating method as claimed in claim 4, wherein on the direction being parallel to this first surface,
The inner edge in the 3rd electrodepositable district is at least separated by a minimum range, and the 4th electrodepositable with the 3rd perforation
The inner edge in district is at least separated by this minimum range with the 4th perforation.
6. electro-plating method as claimed in claim 5, wherein this minimum range is-300～300 millimeters.
7. electro-plating method as claimed in claim 1, wherein the area in the 3rd electrodepositable district more than this
The area in four electrodepositable districts.
8. electro-plating method as claimed in claim 7, the wherein area and the 3rd in this first electrodepositable district
The sum of the area in electrodepositable district, is substantially equal to area and the 4th electrodepositable district in this second electrodepositable district
The sum of area.
9. electro-plating method as claimed in claim 1, wherein places this and accompanies plating plate step on this circuit board
Suddenly comprise:
Make the 3rd electrodepositable district and the 4th electrodepositable district back to this circuit board.
10. electro-plating method as claimed in claim 1, also comprises:
Remove this and accompany plating plate；And
Reclaim and be plated on the 3rd electrodepositable district and this conductive material in the 4th electrodepositable district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510362044.3A CN106332437B (en) | 2015-06-26 | 2015-06-26 | Electro-plating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510362044.3A CN106332437B (en) | 2015-06-26 | 2015-06-26 | Electro-plating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106332437A true CN106332437A (en) | 2017-01-11 |
| CN106332437B CN106332437B (en) | 2018-11-02 |
Family
ID=57722425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510362044.3A Active CN106332437B (en) | 2015-06-26 | 2015-06-26 | Electro-plating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106332437B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107278042A (en) * | 2017-08-07 | 2017-10-20 | 大连崇达电路有限公司 | A kind of circuit board VCP's accompanies plating plate |
| CN113355709A (en) * | 2020-03-04 | 2021-09-07 | 北大方正集团有限公司 | Plating capability evaluation method, plating method and device |
| CN115802633A (en) * | 2022-11-28 | 2023-03-14 | 福莱盈电子股份有限公司 | Electroplating uniformity method of circuit board |
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| US6235994B1 (en) * | 1998-06-29 | 2001-05-22 | International Business Machines Corporation | Thermal/electrical break for printed circuit boards |
| TW511424B (en) * | 2001-11-26 | 2002-11-21 | Hitachi Chemical Co Taiwan Ltd | Manufacturing method of printed circuit board with high integration of electronic device |
| CN1505456A (en) * | 2002-12-05 | 2004-06-16 | 华为技术有限公司 | A printed circuit board and processing method thereof |
| CN102109757A (en) * | 2009-12-29 | 2011-06-29 | 富葵精密组件(深圳)有限公司 | Negative, design method for same, and circuit substrate made of same |
| CN203307457U (en) * | 2013-05-16 | 2013-11-27 | 陈焕宗 | Coating copper control device of electroplating process |
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2015
- 2015-06-26 CN CN201510362044.3A patent/CN106332437B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235994B1 (en) * | 1998-06-29 | 2001-05-22 | International Business Machines Corporation | Thermal/electrical break for printed circuit boards |
| TW511424B (en) * | 2001-11-26 | 2002-11-21 | Hitachi Chemical Co Taiwan Ltd | Manufacturing method of printed circuit board with high integration of electronic device |
| CN1505456A (en) * | 2002-12-05 | 2004-06-16 | 华为技术有限公司 | A printed circuit board and processing method thereof |
| CN102109757A (en) * | 2009-12-29 | 2011-06-29 | 富葵精密组件(深圳)有限公司 | Negative, design method for same, and circuit substrate made of same |
| CN203307457U (en) * | 2013-05-16 | 2013-11-27 | 陈焕宗 | Coating copper control device of electroplating process |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107278042A (en) * | 2017-08-07 | 2017-10-20 | 大连崇达电路有限公司 | A kind of circuit board VCP's accompanies plating plate |
| CN107278042B (en) * | 2017-08-07 | 2023-09-12 | 大连崇达电路有限公司 | Accompanying plating board of circuit board VCP |
| CN113355709A (en) * | 2020-03-04 | 2021-09-07 | 北大方正集团有限公司 | Plating capability evaluation method, plating method and device |
| CN113355709B (en) * | 2020-03-04 | 2024-04-16 | 北大方正集团有限公司 | Electroplating capability assessment method, electroplating method and device |
| CN115802633A (en) * | 2022-11-28 | 2023-03-14 | 福莱盈电子股份有限公司 | Electroplating uniformity method of circuit board |
| CN115802633B (en) * | 2022-11-28 | 2023-12-26 | 福莱盈电子股份有限公司 | Electroplating uniformity method of circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106332437B (en) | 2018-11-02 |
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