CN106328541A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN106328541A
CN106328541A CN201610498779.3A CN201610498779A CN106328541A CN 106328541 A CN106328541 A CN 106328541A CN 201610498779 A CN201610498779 A CN 201610498779A CN 106328541 A CN106328541 A CN 106328541A
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layer
photoresist oxidant
oxidant layer
photoresist
semiconductor device
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樱井仁美
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Seiko Instruments Inc
Ablic Inc
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Abstract

本发明提供半导体装置的制造方法，用于抑制对多晶硅层(4)进行离子注入时的沟道效应，使在多晶硅层(4)的构图中使用的第1光致抗蚀剂层(5)在第2光致抗蚀剂层(8)的开口部露出，将第1光致抗蚀剂层(5)作为由多晶硅层(4)构成的栅电极(4‑1)的掩模来离子注入杂质。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法，尤其涉及相对于多晶硅层的图案自对准地形成离子注入杂质层的制造方法。
背景技术
作为相对于多晶硅层的图案自对准地形成杂质层的使用例之一，在现有的MOS晶体管的制造中，可举出形成晶体管的源-漏区域的杂质层的例子。采用以下所示的工序。
首先，如图2的(a)所示，例如在硅衬底11上形成元件分离绝缘膜12和栅绝缘膜13。接着，在硅衬底11上的整个面形成了多晶硅层14后，涂覆光致抗蚀剂层并利用与多晶硅层14的构图对应的光掩模进行曝光，形成第1光致抗蚀剂层15。
继而，如图2的(b)所示，将第1光致抗蚀剂层15作为掩模材料来蚀刻去除多晶硅层14，在形成了由多晶硅层14构成的栅电极14-1、14-2、电阻14-3和布线后，去除第1光致抗蚀剂层15。
继而，如图2的(c)所示，以使得期望的、例如将栅电极14-1作为电极的MOS晶体管的源极和漏极形成在期望的区域的方式，对第2光致抗蚀剂层16进行构图，利用离子注入法选择性形成源-漏杂质层17。
此时被离子注入杂质的、第2光致抗蚀剂层16的开口部不仅形成在期望的MOS晶体管的源-漏区域上，还形成在栅电极14-1上，因此栅电极14-1成为离子注入时的掩模，从而能够相对于栅电极14-1自对准地形成源-漏杂质层17。
由此，具备以下所示的优点。
(1)无需考虑源-漏杂质层与栅电极在光致抗蚀剂层图案加工时的对位偏差，能够使得晶体管相应地变得细微。
(2)无需对源-漏杂质层用的光致抗蚀剂层图案过度地进行细微加工，能够更为简单地进行至少源-漏杂质层用的加工。
如上所示那样，形成相对于多晶硅层的栅电极图案自对准地具备源-漏杂质层的MOS晶体管。
进而，如图2的(d)所示，根据需要，对例如将栅电极14-2作为电极的MOS晶体管，在期望的区域反复进行上述图2的(c)的工序，由此形成源-漏杂质层18，形成多种MOS晶体管。
已广泛知晓自对准地具备源-漏杂质层的MOS晶体管及其制造方法，例如，非专利文献1中公开了利用上述工序形成MOS晶体管的源-漏杂质层的方法。
非专利文献1：岸野正刚著《超LSI材料·プロセスの基礎》欧姆公司、1987年12月25日、第11-12页
发明内容
然而，非专利文献1所示的MOS晶体管的制造方法具有以下所示的缺陷。
通常用作晶体管的栅电极的多晶硅层由单晶粒的集合体构成，因而在源-漏杂质的离子注入时由于注入杂质通过晶粒间的间隙的沟道效应(channeling)现象，导致穿透由多晶硅层构成的栅电极，栅电极下硅衬底的晶体管的沟道区域也被注入杂质。
这种现象会成为导致作为确定晶体管的阈值的重要要素之一的沟道区域的杂质浓度大幅波动的要因，会妨碍晶体管性能的稳定化。
于是，本申请发明的课题在于，提供一种能够防止沟道效应现象，使得晶体管的阈值变得稳定的MOS晶体管的制造方法。
为了解决上述课题，本发明在相对于多晶硅层的图案自对准地形成杂质层时，采取以下所述的手段。
(1)在保留在多晶硅层的构图中使用的第1光致抗蚀剂层的状态下，离子注入杂质。
(2)在保留在多晶硅层的构图中使用的第1光致抗蚀剂层的状态下，对杂质层用的第2光致抗蚀剂层进行构图，并离子注入杂质。
本发明通过在多晶硅层的图案上保留第1光致抗蚀剂层的状态下，进行杂质层形成的离子注入，由此具备以下所述的效果。
(1)能够抑制隔着多晶硅层的图案的离子注入时的沟道效应现象，例如即使相对于多晶硅层的栅电极通过离子注入自对准地形成MOS晶体管的源-漏杂质层，由于不存在向晶体管的沟道区域的杂质注入，因此也能够使晶体管的阈值稳定。
(2)在离子注入前无需去除多晶硅层的图案上的第1光致抗蚀剂层，能够在后续的光致抗蚀剂去除工序、例如第2光致抗蚀剂层去除时去除第1光致抗蚀剂层，因此能够削减工序。
附图说明
图1是示出本发明的半导体装置的制造方法的工序步骤剖视图。
图2是示出现有的半导体装置的制造方法的工序步骤剖视图。
标号说明
1、11：硅衬底；2、12：元件分离绝缘膜；3、13：栅绝缘膜；4、14：多晶硅层；4-1、4-2、14-1、14-2：栅电极；4-3、14-3：由多晶硅层构成的布线电阻膜；5、15：第1光致抗蚀剂层；6：抗蚀剂硬化层；7、9、10、17、18：源-漏杂质层；8、16：第2光致抗蚀剂层。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
首先，如图1的(a)所示，例如在硅衬底1上形成元件分离绝缘膜2和栅绝缘膜3。接着，在硅衬底1上的整个面上形成了多晶硅层4后，涂覆光致抗蚀剂层并利用与多晶硅层4的构图对应的光掩模进行曝光，形成第1光致抗蚀剂层5。
接着，对构图有第1光致抗蚀剂层5的硅衬底表面进行UV(紫外线)照射，在光致抗蚀剂层5的表面形成具备耐溶剂性和耐曝光性的抗蚀剂硬化层6。
此时的UV照射只要符合温度170～190℃、UV曝光量12～15J/cm2的范围的条件，则能够形成具备目标耐溶剂性和耐曝光性的抗蚀剂硬化层6。
通常对光致抗蚀剂层进行曝光、显像以形成了图案后，通过略高的温度进行焙烤以将光致抗蚀剂层内的有机溶剂向外部排出，虽然加入了烧结抗蚀剂层的工序，然而利用这种单纯的焙烤时，无法期待针对光致抗蚀剂层表面的耐溶剂性和耐曝光性的效果。
接着，如图1的(b)所示，将具有抗蚀剂硬化层6的第1光致抗蚀剂层5作为掩模材料对多晶硅层4进行蚀刻去除，形成由多晶硅层4构成的栅电极4-1、4-2、电阻膜4-3和布线。作为栅电极和电阻膜，除了多晶硅层之外，还可以使用钛、钽或钨等高熔点金属或它们的金属硅化物等的单层膜或层叠膜。
接下来，在栅电极4-1、4-2、电阻膜4-3和布线上继续保留具有抗蚀剂硬化层6的第1光致抗蚀剂层5，并且可以根据需要对硅衬底1整个面进行离子注入，对由多晶硅层构成的栅电极4-1、4-2自对准地形成源-漏杂质层7。由于在栅电极4-1、4-2、电阻膜4-3和布线上存在具有抗蚀剂硬化层6的第1光致抗蚀剂层5，因此能够抑制被离子注入的杂质离子的沟道效应。
继而，如图1的(c)所示，从具有抗蚀剂硬化层6的第1光致抗蚀剂层5之上涂覆第2光致抗蚀剂层8后进行构图。第1光致抗蚀剂层5形成有图案，并且作为基底的多晶硅层4被蚀刻，因此硅衬底表面存在对第1光致抗蚀剂层5的厚度加上多晶硅层4的厚度的阶差。该阶差有时会妨碍第2光致抗蚀剂层8的涂覆扩散而产生涂覆不均。通过使得在第2光致抗蚀剂层形成中进行抗蚀剂涂覆时的抗蚀剂滴下量多于在第1光致抗蚀剂层形成中进行抗蚀剂涂覆时的抗蚀剂滴下量，能够避免上述涂覆不均。在后述的第3光致抗蚀剂层形成时也同样，通过使得在第3光致抗蚀剂层形成中进行抗蚀剂涂覆时的抗蚀剂滴下量多于在第1光致抗蚀剂层形成中进行抗蚀剂涂覆时的抗蚀剂滴下量，能够避免上述涂覆不均。另外，第2光致抗蚀剂层形成时的抗蚀剂滴下量与第3光致抗蚀剂层形成时的抗蚀剂滴下量可以为相同量。通过使用使得在第2和第3光致抗蚀剂层形成中进行抗蚀剂涂覆的抗蚀剂的粘度高于在第1光致抗蚀剂层形成中进行抗蚀剂涂覆的抗蚀剂的粘度的方法，也能够避免涂覆不均。
接着，以使得期望的、例如将栅电极4-1作为电极的MOS晶体管的源极和漏极形成在期望的区域的方式，在第2光致抗蚀剂层8设置开口部，利用离子注入法选择性形成源-漏杂质层9。在开口部露出最初形成的具有抗蚀剂硬化层6的第1光致抗蚀剂层5。
被离子注入杂质的第2光致抗蚀剂层8的开口部不仅形成在期望的MOS晶体管的源-漏区域上，还形成在栅电极4-1上，而由于使用在第1光致抗蚀剂层5形成第2光致抗蚀剂层8的双重抗蚀剂法，因此能够利用第1光致抗蚀剂层对期望的栅电极选择性地施加掩模，针对由多晶硅层构成的栅电极，能够以仅对期望的部分注入杂质的方式，自对准地选择性进行杂质的离子注入。在栅电极4-1之上存在具有抗蚀剂硬化层6的第1光致抗蚀剂层5，因此能够抑制被离子注入的杂质离子的沟道效应。
由此，具备以下所示的优点。
(1)无需考虑源-漏杂质层与栅电极在光致抗蚀剂层图案加工时的对位偏差，能够相应地使晶体管变得细微。
(2)无需对源-漏杂质层用的光致抗蚀剂层图案过度地进行细微加工，至少能够更简单地进行源-漏杂质层用的加工。
(3)在由多晶硅层构成的栅电极上存在光致抗蚀剂层，因此能够抑制杂质离子注入时的沟道效应。
(4)在离子注入前无需去除多晶硅层的图案上的第1光致抗蚀剂层，可以在后续的光致抗蚀剂去除工序、例如第2光致抗蚀剂层去除时去除第1光致抗蚀剂层，因此能够削减工序。
此外，在之前的图1的(a)所示的第1光致抗蚀剂层5上存在抗蚀剂硬化层6，由此即使在涂覆了第2光致抗蚀剂层8的情况下溶剂也不会渗透至第1光致抗蚀剂层5，第1光致抗蚀剂层的图案不会破坏。
进而，在第2光致抗蚀剂层8需要返工的情况下，能够在不使用光掩模的情况下，将涂覆或构图有第2光致抗蚀剂层的硅衬底表面的整个面曝光。即使对第2光致抗蚀剂层进行构图从而第1光致抗蚀剂层5露出，由于通过抗蚀剂硬化层6而具备耐曝光性和耐溶剂性，因此整个面曝光以及此后接着进行的用于第2光致抗蚀剂层去除的碱性溶剂处理也不会对第1光致抗蚀剂层带来影响。如上所示那样，形成相对于多晶硅层的栅电极图案自对准地具有源-漏杂质层的MOS晶体管。
此外，对于利用UV照射的抗蚀剂硬化层6的形成，当不在第1光致抗蚀剂层5的构图后进行，而在多晶硅层4的蚀刻后进行时，虽然也能够得到耐曝光性和耐溶剂性的效果，然而通常由于利用UV照射的烧结，会产生第1光致抗蚀剂层的缩减，因此在比被蚀刻的多晶硅层4的图案靠内侧的部分，形成具有抗蚀剂硬化层6的第1光致抗蚀剂层5，抗蚀剂缩减的部分处会露出多晶硅层的表面。
关于该多晶硅层的表面露出的部分，在后面接着进行的源-漏杂质的离子注入时，成为掩模材料的仅为多晶硅层，通过作为上述课题而举出的离子注入的沟道效应，使得栅电极下硅衬底的晶体管的沟道区域也被注入杂质，增大了晶体管的阈值偏差。进而，如果程度严重，则在多晶硅层的表面露出部正下方也形成有源-漏区域，将会对相对于栅电极图案自对准地形成源-漏杂质层带来妨碍。
另一方面，如本申请实施例中说明的那样，如果在第1光致抗蚀剂层5的构图后、多晶硅层4的蚀刻前进行UV照射，形成抗蚀剂硬化层6，则以缩减后的光致抗蚀剂层图案作为掩模进行多晶硅层的蚀刻，因此能够维持由蚀刻后的多晶硅层构成的栅电极的整个上表面被具有抗蚀剂硬化层6的第1光致抗蚀剂层覆盖的状态，成为源-漏杂质离子注入时的完整的掩模材料，因此能够完美地实现源-漏杂质层相对于栅电极的自对准形成以及沟道效应防止。
进而，如图1的(d)所示，根据需要，例如针对将栅电极4-2作为电极的MOS晶体管，在期望的区域反复进行上述图1的(c)的工序，由此能够形成源-漏杂质层10，形成多种MOS晶体管。即，能够通过改变所涂覆的光致抗蚀剂层、开口部、杂质并反复进行如下工序来形成多种MOS晶体管，上述工序为，在选择性去除了第2光致抗蚀剂层后在第1光致抗蚀剂层上涂覆第3光致抗蚀剂层，然后进行构图，在第3光致抗蚀剂层的一部分设置第2开口部，使第1光致抗蚀剂层在该第2开口部露出，然后从第2开口部离子注入第2杂质以形成源-漏杂质层。
在反复进行图1的(c)的工序的情况下，如果源-漏杂质层的离子注入浓度在5×1014atms/cm2以下，则在多晶硅层上的第1光致抗蚀剂层上形成为双重抗蚀剂的源-漏杂质层用的光致抗蚀剂层仅利用湿式法、即光致抗蚀剂去除用溶剂也能够去除，因此只要具有抗蚀剂硬化层的第1光致抗蚀剂层的耐溶剂性仍然存在，就能够在多晶硅层上保留第1光致抗蚀剂层的状态下多次进行杂质层用光致抗蚀剂层形成和离子注入处理。
另一方面，对具有抗蚀剂硬化层的第1光致抗蚀剂层，实施通常应用于高浓度注入等处理后的光致抗蚀剂层的光致抗蚀剂层的灰化处理。第1光致抗蚀剂层5虽然有抗蚀剂硬化层6，但由于仅处于抗蚀剂表面部分而能够通过灰化处理去除抗蚀剂硬化层6，在去除了抗蚀剂硬化层6后，利用通常的光致抗蚀剂去除用溶剂能够去除第1光致抗蚀剂层和形成为双重抗蚀剂的光致抗蚀剂层的双方。
当然，即使在去除形成为双重抗蚀剂的光致抗蚀剂层后，对第1光致抗蚀剂层实施灰化处理并利用溶剂处理去除第1光致抗蚀剂层，也不会存在问题。
此外，本发明的源-漏杂质层不限于高浓度的N型或P型杂质层，还包括作为以MOS晶体管的最终形态构成源极和漏极的一部分的、例如LDD(Lightly Doped Drain：轻掺杂漏极)、DDD(Double Diffused Drain：双扩散漏极)、作为源-漏间穿通阻止块的袋形(pocket)注入层或环状(halo)注入层。
同样地，本发明将MOS晶体管的源-漏杂质层的制造方法作为一例举出，然而不限于此，当然也能够应用于相对于多晶硅层的图案自对准地形成的杂质层的制造方法。

Claims (11)

1.一种半导体装置的制造方法，相对于半导体衬底上的多晶硅层的图案自对准地形成杂质层，所述半导体装置的制造方法的特征在于，包括以下工序：
在半导体衬底上形成多晶硅层；
在所述多晶硅层上涂覆构成双重抗蚀层的第1光致抗蚀剂层后进行构图；
对构图后的所述第1光致抗蚀剂层进行UV照射；
将所述UV照射后的第1光致抗蚀剂层作为掩模，对所述多晶硅层进行蚀刻，形成由所述多晶硅层构成的栅电极和电阻膜；
在所述UV照射后的第1光致抗蚀剂层上涂覆第2光致抗蚀剂层后进行构图，在所述第2光致抗蚀剂层的一部分设置开口部，使所述第1光致抗蚀剂层在所述开口部露出；以及
在所述开口部离子注入第1杂质。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，还包括以下工序：
在离子注入所述第1杂质的工序之后，去除所述第2光致抗蚀剂层；
在所述第1光致抗蚀剂层上涂覆第3光致抗蚀剂层后进行构图，在所述第3光致抗蚀剂层的一部分设置第2开口部，使所述第1光致抗蚀剂层在所述第2开口部露出；以及
在所述第2开口部离子注入第2杂质。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于，
在去除所述第2光致抗蚀剂层的工序中，使用光致抗蚀剂去除用溶剂。
4.根据权利要求1～3中的任意一项所述的半导体装置的制造方法，其特征在于，
所述开口部至少形成在MOS晶体管的源-漏杂质层形成区域上。
5.根据权利要求1所述的半导体装置的制造方法，其特征在于，
在形成由所述多晶硅层构成的栅电极和电阻膜的工序后，还包括如下工序：在保留所述UV照射后的第1光致抗蚀剂层的状态下，对所述半导体衬底的整个面进行离子注入，相对于由所述多晶硅层构成的栅电极自对准地形成源-漏杂质层。
6.根据权利要求1或5所述的半导体装置的制造方法，其特征在于，
在对所述第1光致抗蚀剂层进行构图的工序后、且在对所述多晶硅层进行蚀刻的工序前，进行对所述构图后的所述第1光致抗蚀剂层进行UV照射的工序。
7.根据权利要求2～4中的任意一项所述的半导体装置的制造方法，其特征在于，
在对所述第1光致抗蚀剂层进行构图的工序后、且在对所述多晶硅层进行蚀刻的工序前，进行对所述构图后的所述第1光致抗蚀剂层进行UV照射的工序。
8.根据权利要求1～7中的任意一项所述的半导体装置的制造方法，其特征在于，
使得所述第2光致抗蚀剂层形成时的抗蚀剂滴下量多于所述第1光致抗蚀剂层形成时的抗蚀剂滴下量。
9.根据权利要求2～4、7中的任意一项所述的半导体装置的制造方法，其特征在于，
使得所述第3光致抗蚀剂层形成时的抗蚀剂滴下量多于所述第1光致抗蚀剂层形成时的抗蚀剂滴下量。
10.根据权利要求1～7中的任意一项所述的半导体装置的制造方法，其特征在于，
使得所述第2光致抗蚀剂层形成时的抗蚀剂的粘度高于所述第1光致抗蚀剂层形成时的抗蚀剂的粘度。
11.根据权利要求2～4、7中的任意一项所述的半导体装置的制造方法，其特征在于，
使得所述第3光致抗蚀剂层形成时的抗蚀剂的粘度高于所述第1光致抗蚀剂层形成时的抗蚀剂的粘度。
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