CN106298949A - 屏蔽栅沟槽型功率mos器件的工艺方法 - Google Patents

屏蔽栅沟槽型功率mos器件的工艺方法 Download PDF

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CN106298949A
CN106298949A CN201610929659.4A CN201610929659A CN106298949A CN 106298949 A CN106298949 A CN 106298949A CN 201610929659 A CN201610929659 A CN 201610929659A CN 106298949 A CN106298949 A CN 106298949A
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周颖
丛茂杰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种屏蔽栅沟槽型功率MOS器件的工艺方法，包含步骤：第1步，在硅衬底上进行沟槽刻蚀，然后形成牺牲氧化层；第2步，淀积衬垫氧化层，淀积多晶硅并回刻，形成沟槽内的底层多晶硅；第3步，形成多晶硅层间介质氧化膜；第4步，在整个硅片表面生长一层热氧化层；第5步，回刻热氧化层；第6步，形成栅氧化层；第7步，淀积多晶硅及回刻，在沟槽内形成上层多晶硅。本发明通过在多晶硅层间介质氧化膜工艺之后，先进行一次热氧化层工艺，使底层多晶硅的上表面边角处圆化，相当于增加了硅衬底材质的露出面积，在后续栅氧化层的生成过程中，栅氧化层生长更好，膜厚均匀性更佳，降低了易击穿点的产生。

Description

屏蔽栅沟槽型功率MOS器件的工艺方法
技术领域
本发明涉及半导体器件制造领域，特别是指一种屏蔽栅沟槽型功率MOS器件工艺方法。
背景技术
屏蔽栅沟槽型功率MOS器件，，是当前广泛使用的一种功率半导体器件，其是在半导体材料如硅衬底中刻蚀形成沟槽，淀积介质层之后填充多晶硅，且多晶硅在沟槽中分为上下两层。具体的制造工艺是，先在硅衬底上刻蚀出沟槽，然后淀积牺牲氧化层，再淀积衬垫氧化层，然后沟槽内填充多晶硅并回刻形成第一层多晶硅，然后淀积多晶硅层间介质氧化膜，制作栅氧化层等……，该工艺形成的屏蔽栅沟槽型功率MOS器件，导致Vramp测试性能较差。Vramp测试是对器件栅极加压并逐渐增加电压值一直到器件烧坏的测试，可以测得器件的阈值电压及击穿电压。经过对失效样品的分析，发现器件沟槽栅氧化层的下角处容易发生烧坏，即如图1及图2所示，图2是图1的失效部位放大图。具体分析原因，是由于在屏蔽栅沟槽型功率MOS器件制造工艺中，完成多晶硅层间介质氧化膜之后做沟槽栅氧化层氧化时，栅氧化层下角位置(及图2所示)临近多晶硅层间介质氧化膜氧化受阻，导致膜厚不足，即此处的绝缘介质厚度较其他位置的膜更薄，比如经过实际测量，下角处的膜厚为41纳米，而其他区域的平均膜厚为54纳米，从而下角处的耐压偏低形成一个易击穿点，沟槽栅极耐压不良。
发明内容
本发明所要解决的技术问题在于提供一种屏蔽栅沟槽型功率MOS产品的工艺方法，能改善其Vramp性能。
本发明所述的屏蔽栅沟槽型功率MOS器件的工艺方法，包含如下的工艺步骤：
第1步，在硅衬底上进行沟槽刻蚀，然后形成牺牲氧化层；
第2步，淀积衬垫氧化层，淀积多晶硅并回刻，形成沟槽内的底层多晶硅；
第3步，进行多晶硅层间介质膜生长；
第4步，在整个硅片表面生长一层热氧化层；
第5步，回刻热氧化层；
第6步，形成栅氧化层；
第7步，淀积多晶硅及回刻，在沟槽内形成上层多晶硅。
所述第4步中，形成的热氧化层厚度为
所述第5步中，回刻热氧化层，将硅片表面形成的热氧化层全部去除。
经过第4步及第5步的热氧化层工艺之后，底层多晶硅上表面与沟槽侧壁的夹角处的硅露出面积增加，在第6步形成栅氧化层时，夹角处的硅衬底材质更容易氧化，形成的栅氧化层厚度均一性更好。
本发明所述的屏蔽栅沟槽型功率MOS器件的工艺方法，通过在牺牲氧化层工艺之后，先进行一次热氧化层工艺，使底层多晶硅的上表面边角处圆化，即底层多晶硅的上表面与沟槽侧壁的过渡更为平滑，相当于增加了硅衬底材质的露出面积，在后续栅氧化层的生成过程中，栅氧化层生长更好，膜厚均匀性更佳，降低了易击穿点的产生。
附图说明
图1是失效屏蔽栅沟槽型功率MOS器件沟槽栅氧化层的下角处容易发生烧坏的示意图。
图2是图1的失效部位(虚线圆圈注处)放大图。
图3-8是本发明工艺步骤示意图。
具体实施方式
本发明所述的一种屏蔽栅沟槽型功率MOS器件的工艺方法，包含如下的工艺步骤：
第1步，在硅衬底上进行沟槽刻蚀，然后形成牺牲氧化层；如图3所示。
第2步，淀积衬垫氧化层，淀积多晶硅并回刻，形成沟槽内的底层多晶硅；如图4所示。
第3步，进行多晶硅层间介质氧化膜生长；如图5所示。
第4步，在整个硅片表面生长一层热氧化层；形成的热氧化层厚度为如图6所示。
第5步，回刻热氧化层；将硅片表面形成的热氧化层全部去除。经过热氧化层工艺之后，底层多晶硅上表面与沟槽侧壁的夹角过渡更加平滑，露出面积增加。如图7所示，与热氧化层工艺之前的图5所示的几乎为直角的边角，图7中多晶硅上方与沟槽侧壁的过渡明显更为平滑。
第6步，形成栅氧化层；夹角处的硅衬底材质由于与氧接触面积增大而更容易氧化，形成的栅氧化层厚度均匀性更好。如图8所示。
第7步，淀积多晶硅及回刻，在沟槽内形成上层多晶硅，工艺完成。
经过上述工艺，在传统的易击穿点位置，实际测得的膜厚为45nm，比传统的易击穿点的膜厚41nm厚了约4nm，而Vramp耐压值则提升了2V。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种屏蔽栅沟槽型功率MOS器件的工艺方法，其特征在于，包含如下的工艺步骤：
第1步，在硅衬底上进行沟槽刻蚀，然后形成牺牲氧化层；
第2步，淀积衬垫氧化层，淀积多晶硅并回刻，形成沟槽内的底层多晶硅；
第3步，进行多晶硅层间介质氧化膜的生长；
第4步，在整个硅片表面生长一层热氧化层；
第5步，回刻热氧化层；
第6步，形成栅氧化层；
第7步，淀积多晶硅及回刻，在沟槽内形成上层多晶硅。
2.如权利要求1所述的屏蔽栅沟槽型功率MOS器件的工艺方法，其特征在于，所述第4步中，形成的热氧化层厚度为
3.如权利要求1所述的屏蔽栅沟槽型功率MOS器件的工艺方法，其特征在于，所述第5步中，回刻热氧化层，将硅片表面形成的热氧化层全部去除。
4.如权利要求1所述的屏蔽栅沟槽型功率MOS器件的工艺方法，其特征在于，经过第4步及第5步的热氧化层工艺之后，底层多晶硅上表面与沟槽侧壁的夹角处的硅露出面积增加，在第6步形成栅氧化层时，夹角处的硅衬底材质更容易氧化，形成的栅氧化层厚度均匀性更好。
CN201610929659.4A 2016-10-31 2016-10-31 屏蔽栅沟槽型功率mos器件的工艺方法 Pending CN106298949A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112133759A (zh) * 2020-11-25 2020-12-25 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽结构的半导体器件及其制造方法
CN113035715A (zh) * 2019-12-25 2021-06-25 华润微电子（重庆）有限公司 屏蔽栅沟槽场效应晶体管及其制备方法
WO2022032566A1 (en) * 2020-08-13 2022-02-17 Texas Instruments Incorporated Semiconductor device including lateral insulator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173844A1 (en) * 2003-03-05 2004-09-09 Advanced Analogic Technologies, Inc. Advanced Analogic Technologies (Hongkong) Limited Trench power MOSFET with planarized gate bus
CN101315893A (zh) * 2007-05-30 2008-12-03 上海华虹Nec电子有限公司 沟槽型双层栅功率mos结构实现方法
US20130302958A1 (en) * 2012-05-14 2013-11-14 Zia Hossain Method of making an insulated gate semiconductor device having a shield electrode structure
CN105244374A (zh) * 2015-08-31 2016-01-13 上海华虹宏力半导体制造有限公司 具有屏蔽栅的沟槽栅mosfet的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040173844A1 (en) * 2003-03-05 2004-09-09 Advanced Analogic Technologies, Inc. Advanced Analogic Technologies (Hongkong) Limited Trench power MOSFET with planarized gate bus
CN101315893A (zh) * 2007-05-30 2008-12-03 上海华虹Nec电子有限公司 沟槽型双层栅功率mos结构实现方法
US20130302958A1 (en) * 2012-05-14 2013-11-14 Zia Hossain Method of making an insulated gate semiconductor device having a shield electrode structure
CN105244374A (zh) * 2015-08-31 2016-01-13 上海华虹宏力半导体制造有限公司 具有屏蔽栅的沟槽栅mosfet的制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035715A (zh) * 2019-12-25 2021-06-25 华润微电子（重庆）有限公司 屏蔽栅沟槽场效应晶体管及其制备方法
WO2022032566A1 (en) * 2020-08-13 2022-02-17 Texas Instruments Incorporated Semiconductor device including lateral insulator
US11322594B2 (en) 2020-08-13 2022-05-03 Texas Instruments Incorporated Semiconductor device including a lateral insulator
CN112133759A (zh) * 2020-11-25 2020-12-25 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽结构的半导体器件及其制造方法
CN112133759B (zh) * 2020-11-25 2021-02-05 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽结构的半导体器件及其制造方法

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Application publication date: 20170104