CN106291099A - Chip port frequency test method - Google Patents
Chip port frequency test method Download PDFInfo
- Publication number
- CN106291099A CN106291099A CN201610615663.3A CN201610615663A CN106291099A CN 106291099 A CN106291099 A CN 106291099A CN 201610615663 A CN201610615663 A CN 201610615663A CN 106291099 A CN106291099 A CN 106291099A
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- test
- frequency
- chip port
- vector
- chip
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a kind of chip port frequency test method, including: define the frequency of the test vector of an output pin of described chip, make this frequency meet the test frequency of automatic testing equipment (ATE)；Run other test vectors；And run the test vector of described output pin, to carry out described chip port frequency test.The present invention is in order to realize in the case of test vector frequency can provide highest frequency beyond used ATE under frequency test pattern, by test vector is split, and concurrent test technology realizes the test of chip port output frequency, solve in existing scheme one and need upgrading hardware, the problem of ancillary cost, solving to need other test equipment plug-in in existing scheme two, the testing time is long, and hardware connects inconvenient problem.The present invention, under conditions of ATE hardware is constant, utilizes concurrent test technology to realize the test of chip port upper frequency, improves higher chip port output frequency test convenience and testing efficiency.
Description
Technical field
The present invention relates to chip testing field, particularly relate to a kind of chip port frequency test method.
Background technology
In chip testing, port frequency test is unusual part and parcel.When carrying out port frequency test, automatically test
Device (ATE) applies input signal to the input port of chip, allows circuit enter relevant work state, then captures tested output
Response signal on port, this output signal is sampled by ATE, in a period of time t that calculation procedure limits, output signal
Rising edge number n, the output frequency obtaining this tested port is f=n/t, is compared with port desired output frequency values by f, if
Unanimously it is judged as this port output frequency of chip correct, is judged as this port output frequency of chip extremely if inconsistent.
When existing chip port output frequency is tested, generally use a test vector to complete this test item, be used for
The input port of state is set and is all placed in this test vector for the output port tested, the following institute of test vector example
Show.The frequency of this test vector is generally not capable of exceeding the peak frequency f that this ATE allows under frequency test pattern, as used ATE
During test frequency, this peak frequency is that the time cycle tset performing often row vector in following test vector can not be less than t=
1/f。
When test vector frequency is beyond available highest frequency under used ATE frequency test pattern, generally just like
Lower way:
Prior art one: upgrading hardware；
Change the ATE of greater degree, but this is the most expensive, need to pay the highest cost；
Prior art two: do not use ATE directly to carry out chip output mouth frequency test, while running test vector,
By the plug-in oscillograph of ATE, carry out output port frequency test；ATE and plug-in oscillograph communication can lengthen the testing time, and outward
Hang oscillograph test also inconvenient on hardware connects.
In sum, developing rapidly along with integrated circuit so that its port frequency is more and more higher, uses prior art,
Or improve testing cost, or scale of mass production test cannot be carried out expeditiously.
Summary of the invention
In order to solve the problem that prior art exists, the present invention provides a kind of chip port frequency test method, including:
Define the frequency of the test vector of an output pin of described chip, make this frequency meet the survey of automatic testing equipment
Examination frequency；
Run other test vectors；And
Run the test vector of described output pin, to carry out described chip port frequency test.
Optionally, the test frequency of described automatic testing equipment is less than the frequency of other test vectors described.
Optionally, the test vector of described output pin and other test vectors are in the different portions of described automatic testing equipment
Partite transport row.
Optionally, the method carrying out described chip port frequency test is, obtains the output of output pin in a period of time t
Rising edge number n of signal, the output frequency being calculated this tested port is f=n/t.
Optionally, after described chip port frequency test completes, the test vector of described output pin out of service, its
He continues to run with by test vector.
Optionally, other test vectors described are clock and arrange pin vector.
Optionally, the test vector of described output pin is clock and arranges pin vector.
Optionally, test vector and other test vectors of described output pin are run by different test items.
Optionally, the test frequency of described automatic testing equipment is this automatic testing equipment frequency under frequency test pattern
Rate.
Optionally, described automatic testing equipment frequency in test mode is less than its test supported in the normal mode
The highest frequency of vector.
The invention provides a kind of chip port frequency test method, including: define an output pin of described chip
The frequency of test vector, makes this frequency meet the test frequency of automatic testing equipment (ATE)；Run other test vectors；And
Run the test vector of described output pin, to carry out described chip port frequency test.The present invention in order to realize test to
In the case of amount frequency can provide highest frequency beyond used ATE under frequency test pattern, by test vector is carried out
Split, and concurrent test technology realize the test of chip port output frequency, solves in existing scheme one and needs upgrading hardware,
The problem of ancillary cost, solves to need other test equipment plug-in in existing scheme two, and the testing time is long, and hardware connects inconvenience
Problem.The present invention, under conditions of ATE hardware is constant, utilizes concurrent test technology to realize the survey of chip port upper frequency
Examination, improves higher chip port output frequency test convenience and testing efficiency.
Accompanying drawing explanation
Fig. 1 is the flow chart of the chip port frequency test method described in one embodiment of the invention；
Fig. 2 be the chip port frequency test method described in one embodiment of the invention implement schematic diagram.
Detailed description of the invention
When testing for chip port output frequency, it usually needs first run test vector, chip is made to enter test institute
The duty needed, now, tested port has rate-adaptive pacemaker, captures this signal and is analyzed, obtains in a period of time t, output
Rising edge number n of signal, the output frequency being calculated this tested port is f=n/t.
When the frequency of test vector is beyond automatic testing equipment (ATE) available highest frequency under frequency test pattern
During fc, ATE does not support directly to test in same test item port output frequency.Such as existing automatic testing equipment itself
Holding test vector highest frequency is fo=400MHz, but only supports that under frequency test pattern test vector highest frequency is fc=
200MHz, it is now desired to test expected value is the port output frequency of 350MHz, uses the frequency test mould of automatic testing equipment
Formula cannot be directly realized by.
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
A kind of chip port frequency test method of the present invention, as it is shown in figure 1, include:
Define the frequency of the test vector of an output pin of described chip, make this frequency meet automatic testing equipment
(ATE) test frequency；
Run other test vectors；And
Run the test vector of described output pin, to carry out described chip port frequency test.
Generally, the test frequency of described automatic testing equipment is less than the frequency of other test vectors described.Above-mentioned automatic survey
The test frequency of electricity testing device is this automatic testing equipment (ATE) frequency in test mode, and this frequency is supported to survey less than it
The highest frequency of examination vector.
In the present embodiment, can directly the test vector carrying out port frequency test be divided into the test vector of output pin
With other test vectors, the present embodiment is two parts.Wherein, former test vector " pat_0 " is as follows, wherein performs every
The time cycle of row vector is tset=1/350MHz；
Pat_0:
It is divided into the test vector of other test vectors and output pin.The test vector of output pin is " pat_fcp ",
Other test vectors are clock and arrange pin vector " pat_clk_set ", as follows:
Pat_clk_set:
The time cycle of where each row vector is tset1=1/350MHz；
Pat_fcp:
The time cycle of where each row vector is tset2=1/50MHz；
It addition, the test vector of described output pin and other test vectors are in the different piece of described automatic testing equipment
Running, specifically, it is different that the channel resource used by two test vectors of partition must be distributed in automatic testing equipment
On Engine.
It is as follows that then testing process is set, first passes through test item Test_setup and win the race a test vector " pat_
Clk_set ", make the output of chip tested port treat measured frequency, and this vector runs on backstage always, clock will not stop, tested end
Mouth has rate-adaptive pacemaker always, then runs second test vector " pat_fcp " by test item Test_Meas, tests at this
Chip port output frequency is recorded according to automatic testing equipment frequency test method in Xiang.
Test source code is as follows:
Publ ic Funct ion BackGround_test_setup()As Long
Dim test_setup_PAT As String (definition is arranged with test vector)
Test_setup_PAT=". patterns pat_clk_set.PAT "
If (TheExec.Flow.IsTestBPStart=True) Then
If (in test flow, opcode is " TestBPStart ", then arranged by test vector " pat_clk_set "
Chip enters relevant work state, and allows this test vector run always, and clock will not stop, and tested port has frequency defeated always
Go out)
If (in test flow, opcode is " TestBPEnd ", then stopped by " pat_clk_set " test vector, test
Terminate)
A kind of chip port frequency test method of the present embodiment is concrete as in figure 2 it is shown, include:
1. chip powers up, and applies the voltage of regulation to the power supply of chip；
2. by running test vector " pat_clk_set ", arranging chip and enter relevant work state, the tested port of chip is opened
Begin to have rate-adaptive pacemaker, set vector " pat_clk_set " and run on backstage always；
3. carry out chip port frequency test by test item " Test_Meas "；
4. judging to have tested whether, without completing, continue test, if completed, stopping test vector " pat_
clk_set”；
5. test terminates.
The technical scheme is that to realize exceeding used ATE under frequency test pattern in test vector frequency
In the case of can providing highest frequency, by test vector is split, and concurrent test technology to realize chip port defeated
Going out the test of frequency, solve in existing scheme one and need upgrading hardware, the problem of ancillary cost, outside solving to need in existing scheme two
Hanging other test equipment, the testing time is long, and hardware connects inconvenient problem.The present invention under conditions of ATE hardware is constant,
Utilize concurrent test technology to realize the test of chip port upper frequency, improve the test of higher chip port output frequency convenient
Property and testing efficiency.
Obviously, those skilled in the art can carry out various change and the modification spirit without deviating from the present invention to invention
And scope.So, if the present invention these amendment and modification belong to the claims in the present invention and equivalent technologies thereof scope it
In, then the present invention is also intended to change and including modification include these.
Claims (10)
1. a chip port frequency test method, it is characterised in that including:
Define the frequency of the test vector of an output pin of described chip, make this frequency meet the test frequency of automatic testing equipment
Rate；
Run other test vectors；And
Run the test vector of described output pin, to carry out described chip port frequency test.
2. chip port frequency test method as claimed in claim 1, it is characterised in that the test of described automatic testing equipment
Frequency is less than the frequency of other test vectors described.
3. chip port frequency test method as claimed in claim 1, it is characterised in that the test vector of described output pin
Run in the different piece of described automatic testing equipment with other test vectors.
4. chip port frequency test method as claimed in claim 1, it is characterised in that carry out described chip port frequency and survey
The method of examination is, obtains rising edge number n of the output signal of output pin in a period of time t, is calculated this tested port
Output frequency be f=n/t.
5. chip port frequency test method as claimed in claim 1, it is characterised in that at described chip port frequency test
After completing, the test vector of described output pin out of service, other test vectors continue to run with.
6. chip port frequency test method as claimed in claim 1, it is characterised in that other test vectors described are clock
Vectorial with arranging pin.
7. chip port frequency test method as claimed in claim 1, it is characterised in that the test vector of described output pin
For clock and arrange pin vector.
8. chip port frequency test method as claimed in claim 1, it is characterised in that run institute by different test items
State test vector and other test vectors of output pin.
9. chip port frequency test method as claimed in claim 1, it is characterised in that the test of described automatic testing equipment
Frequency is this automatic testing equipment frequency under frequency test pattern.
10. chip port frequency test method as claimed in claim 1, it is characterised in that described automatic testing equipment is being surveyed
Frequency under die trial formula is less than the highest frequency of its test vector supported in the normal mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610615663.3A CN106291099B (en) | 2016-07-29 | 2016-07-29 | Chip port frequency test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610615663.3A CN106291099B (en) | 2016-07-29 | 2016-07-29 | Chip port frequency test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106291099A true CN106291099A (en) | 2017-01-04 |
| CN106291099B CN106291099B (en) | 2019-10-25 |
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ID=57663176
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| CN201610615663.3A Active CN106291099B (en) | 2016-07-29 | 2016-07-29 | Chip port frequency test method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143026A (en) * | 2018-07-12 | 2019-01-04 | 上海航天信息研究所 | A kind of digital test method and system |
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| Publication number | Publication date |
|---|---|
| CN106291099B (en) | 2019-10-25 |
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