CN108181570A - Chip ground pin continuity testing method and device, readable storage medium storing program for executing - Google Patents
Chip ground pin continuity testing method and device, readable storage medium storing program for executing Download PDFInfo
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- CN108181570A CN108181570A CN201711383209.0A CN201711383209A CN108181570A CN 108181570 A CN108181570 A CN 108181570A CN 201711383209 A CN201711383209 A CN 201711383209A CN 108181570 A CN108181570 A CN 108181570A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
Abstract
A kind of chip ground pin continuity testing method and device, readable storage medium storing program for executing, the test method include：To the tested grounding pin output driving current of the chip, and other pins of the chip in addition to the tested grounding pin is controlled to be coupled with preset ground channel or outside 0V voltage channels；The voltage on the tested grounding pin is obtained, and combines preset clamp voltage, determines whether connectivity is bad for the tested grounding pin.Said program can improve the coverage of chip testing.
Description
Technical field
The present invention relates to chip testing field more particularly to a kind of chip ground pin continuity testing method and device,
Readable storage medium storing program for executing.
Background technology
Continuity testing, also known as open circuit and short-circuit test, for test integrated circuit (Integrated Circuit,
IC) whether all useful signal pins of chip exterior with internal circuit complete basic electric connection, include whether exist
A certain signal pins and other signal pins, power pins or ground pin short circuit, if there are a certain signals
Or there is the phenomenon that open circuit etc. in grounding pin.
Traditional chip detecting method is only tested between all input/output (I/O) pin and VDD and arbitrary grounding pin
Connectivity.When IC chip is there are during two or more grounding pins, traditional chip detecting method is by two grounding pins
Short circuit is simultaneously uniformly connected to the ground on test board (GND) channel.
However, when to being tested there are the IC chip of two even more grounding pins, traditional chip testing
Method can not filter out the wherein undesirable bad chip of some grounding pin connectivity, and it is even more impossible to know which specific ground connection
There is the undesirable situation of connectivity in pin, and test coverage is relatively low.
Invention content
The technical issues of embodiment of the present invention solves is how to improve the coverage rate of chip ground pin continuity testing.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of chip ground pin continuity testing method, packet
It includes：To the chip tested grounding pin output driving current and control the chip in addition to the tested grounding pin
Other pins are coupled with preset ground channel or outside 0V voltage channels；The voltage on the tested grounding pin is obtained, and is tied
Preset clamp voltage is closed, determines whether connectivity is bad for the tested grounding pin.
Optionally, whether connectivity is bad for the determining tested grounding pin, including：When the tested grounding pin
On voltage and the difference of the clamp voltage when being less than preset first difference, judge the tested grounding pin connectivity not
It is good；When the voltage on the tested grounding pin is less than preset first voltage and is more than preset second voltage, institute is judged
It is normal to state tested grounding pin connectivity；When the voltage on the tested grounding pin is less than the second voltage, institute is judged
It is normal to state tested grounding pin connectivity；The first voltage is less than the clamp voltage.
Optionally, the built-in chip type has protection diode, and the protection diode is corresponding with all grounding pins
Liner couples；The first voltage is more than the conducting voltage of the protection diode.
Optionally, the tested grounding pin output driving current to the chip, including：Control preset driving electricity
Road is established with the tested grounding pin and is connected, and controls the driving circuit to the tested grounding pin output driving electricity
Stream.
Optionally, the driving circuit is continuous current source.
Optionally, it after determining that the tested grounding pin connectivity is bad, further includes：Output alarm signal, to refer to
Show that the tested grounding pin connectivity is bad.
Optionally, the output alarm signal, including：Output includes the alarm signal of the tested grounding pin mark.
The embodiment of the present invention additionally provides a kind of chip ground pin connectivity testing device, including：Control unit is used for
To the tested grounding pin output driving current of the chip, and control its in addition to the tested grounding pin of the chip
He couples pin with preset ground channel or outside 0V voltage channels；Acquiring unit, for obtaining the tested grounding pin
Voltage；Identifying unit for according to the voltage on the tested grounding pin, and combines preset clamp voltage, determines institute
Stating tested grounding pin, whether connectivity is bad.
Optionally, the identifying unit, is used for：When the voltage and the difference of the clamp voltage on the tested grounding pin
During less than preset first difference, judge that the tested grounding pin connectivity is bad；Electricity on the tested grounding pin
When pressure is less than preset first voltage and is more than preset second voltage, judge that the tested grounding pin connectivity is normal；When
When voltage on the tested grounding pin is less than the second voltage, judge that the tested grounding pin connectivity is normal；Institute
First voltage is stated less than the clamp voltage.
Optionally, the built-in chip type has protection diode, and the protection diode is corresponding with all grounding pins
Liner couples；The first voltage is more than the conducting voltage of the protection diode.
Optionally, described control unit, the tested grounding pin for controlling preset driving circuit and the chip are built
Vertical connection, and the driving circuit is controlled to the tested grounding pin output driving current.
Optionally, the driving circuit is continuous current source.
Optionally, the chip ground pin connectivity testing device further includes：Output unit, for exporting alarm signal
Number, to indicate that the tested grounding pin connectivity is bad.
Optionally, the output unit, for exporting the alarm signal for including the tested grounding pin mark.
The embodiment of the present invention additionally provides a kind of computer readable storage medium, is stored thereon with computer instruction, described
The step of computer instruction performs the chip ground pin continuity testing method described in any of the above-described kind when running.
The embodiment of the present invention additionally provides a kind of chip ground pin connectivity testing device, including memory and processing
Device, is stored with computer instruction on the memory, and when computer instruction operation performs the chip described in any of the above-described kind
The step of grounding pin continuity testing method.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
When the grounding pin to chip carries out continuity testing, the tested grounding pin of selection is simultaneously electric to its output driving
Stream, remaining pin are coupled with ground channel or outside 0V voltage channels.By the voltage on the tested grounding pin that gets with
And default clamp voltage, you can knowing tested grounding pin, whether connectivity is bad, therefore can effectively improve chip ground and draw
The coverage of foot continuity testing.
Further, after detecting that tested grounding pin connectivity is bad, output alarm signal, to indicate tester
There are the undesirable grounding pins of connectivity for current chip, are sorted out convenient for tester in the presence of abnormal chip.
Description of the drawings
Fig. 1 is a kind of flow chart of chip ground pin continuity testing method in the embodiment of the present invention；
Fig. 2 is a kind of structure diagram of chip ground pin continuity testing system in the embodiment of the present invention；
Fig. 3 is a kind of structure diagram of chip ground pin connectivity testing device in the embodiment of the present invention.
Specific embodiment
In the prior art, there may be two even more grounding pins for some IC chips.It is surveyed using traditional chip
When method for testing tests IC chip, typically multiple grounding pins are shorted together, and are uniformly connected on test board
Ground channel.However, when grounding pin undesirable there are connectivity in multiple grounding pins, due to normal there are connectivity
Grounding pin is normally connect, therefore traditional chip detecting method can judge the equal connectivity of all grounding pins just with ground channel
Often namely traditional chip detecting method can not know which grounding pin is bad there are connectivity, therefore there are error detections
Situation, the problem of causing chip ground pin continuity testing accuracy relatively low.
In embodiments of the present invention, when the grounding pin to chip carries out continuity testing, tested grounding pin is selected
And to its output driving current, remaining pin is coupled with ground channel or outside 0V voltage channels.It tested is connect by what is got
Voltage and default clamp voltage on ground pin, you can knowing tested grounding pin, whether connectivity is bad, therefore can have
Effect avoids the appearance of error detection situation, therefore effectively improves accuracy and the coverage of chip ground pin continuity testing.
It is understandable for above-mentioned purpose, feature and advantageous effect of the invention is enable to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
An embodiment of the present invention provides a kind of chip ground pin continuity testing method, with reference to Fig. 1, below by way of specific
Step is described in detail.
In specific implementation, can be drawn by preset tester table to perform the chip ground provided in the embodiment of the present invention
Foot continuity testing method is connected by other test systems to perform the chip ground pin provided in the embodiment of the present invention
General character test method.
In embodiments of the present invention, the continuity testing of chip ground pin can refer between multiple grounding pins of chip
Continuity testing is carried out, whether the connectivity between multiple grounding pins of test chip is normal.In practical applications it is found that core
The connectivity of the grounding pin of piece is：Connecting line and chip between the corresponding liner of the grounding pin of chip it is each
Connectivity between the corresponding liner of a grounding pin.Therefore, whether the connectivity of the grounding pin of test chip is normal, essence
On be test chip the corresponding liner of grounding pin between connecting line whether connect normally；When the grounding pin of chip
When connecting line connection between corresponding liner is normal, which connect normally with other grounding pins.
Step S101 to the tested grounding pin output driving current of the chip, and controls the chip to remove the quilt
Other pins surveyed except grounding pin are coupled with preset ground channel or outside 0V voltage channels.
In specific implementation, the chip for carrying out pin continuity testing can include two or more grounding pins.
When testing the grounding pin of chip, a grounding pin can be first chosen as tested grounding pin, and chip is removed
Other pins except selected tested grounding pin are coupled with preset ground channel or outside 0V voltage channels.
In practical applications, other pins of chip other than selected tested grounding pin can include：Except quilt
Survey other grounding pins, all power pins and all input/output pins except grounding pin.
It in specific implementation, can be first by a grounding lead of chip before the grounding pin to chip is tested
Foot is coupled with preset driving circuit, and other grounding pins are coupled with the ground channel output end on preset test board.For just
In description, the embodiment of the present invention, the referred to as tested grounding pin of the grounding pin that connect will be established with driving circuit, it will be with survey
The grounding pin that test plate (panel) establishes connection is referred to as other grounding pins.
For example, chip includes three grounding pins, it is followed successively by grounding pin VSS1, grounding pin VSS2, grounding pin
VSS3.When the grounding pin VSS1 to chip is tested, will be established between the grounding pin VSS1 and driving circuit of chip
Connection couples the ground channel output end on the grounding pin VSS2 of chip, grounding pin VSS3 and preset test board.This
When, grounding pin VSS1 is referred to as tested grounding pin, and grounding pin VSS2, grounding pin VSS3 are referred to as other grounding leads
Foot.
When the grounding pin to chip is tested, control driving circuit to tested grounding pin output driving current,
Namely to grounding pin VSS1 output driving currents；The ground channel on test board is controlled to be coupled with other grounding pins.
In specific implementation, driving circuit can be continuous current source, or other can export constant current
Device can be not repeated herein as long as meeting to grounding pin output driving current.
For example, driving circuit is continuous current source, and the output current in continuous current source is 100 μ A.
Step S102 obtains the voltage on the tested grounding pin, and combines preset clamp voltage, determines the quilt
Surveying grounding pin, whether connectivity is bad.
In specific implementation, it can be tested in advance, some the grounding pin connectivity for obtaining chip is bad and defeated
Enter to have voltage V0 during driving current, clamp voltage V1 is set with this, also can V1 be set according to V0.Complete clamper
After the setting of voltage, you can according to the voltage on grounding pin, to judge grounding pin, whether connectivity is bad.
In embodiments of the present invention, set clamp voltage V1 can be closer to V0, for example, V1=can be set
V0 can also set V1 to be slightly less than V0 slightly larger than V0 or setting V1.The difference of V1 and V0 may be in a certain range, can
The absolute value of the difference between the two to be set to be less than the first difference.First difference can be configured according to practical application scenarios.Example
Such as, the first difference is set as 0.2V or the first difference is set as 0.5V.
In an embodiment of the present invention, test learns that the grounding pin VSS1 connectivity of chip is bad in advance, and drives electricity
During road direction grounding pin VSS1 output driving currents, the voltage on grounding pin VSS1 is 1.9V, then clamp voltage is set as
2.0V。
It is understood that clamp voltage may be set to be other values.For example, when the voltage on grounding pin VSS1 is
1.9V, then clamp voltage could be provided as 1.8V.
In specific implementation, when the voltage on tested grounding pin and the difference of clamp voltage are less than preset first difference
When, it is possible to determine that tested grounding pin connectivity is bad.At this point, the undesirable principle of the tested grounding pin connectivity of judgement is as follows：
When tested grounding pin connectivity is bad, it is meant that the corresponding liner bad connection of tested grounding pin,
Therefore, it is impossible to corresponding liner forming circuit；Under the action of driving current, the charge being tested on grounding pin is constantly tired
Product, until the quantity of electric charge tends to balance, at this point, the voltage on tested grounding pin is V0, therefore, it is possible to determine that tested grounding pin
Connectivity is bad, is determined as open circuit.
In specific implementation, when the voltage on tested grounding pin is less than first voltage, but is greater than second voltage, then
It can be determined that tested grounding pin connectivity is normal, but other grounding pins may connectivity be bad or tested grounding pin
Between corresponding with other grounding pins liner of corresponding liner may connectivity it is bad.
In practical applications, chip can include protection diode.First voltage can be according to the conducting of protection diode
Voltage is configured, and set first voltage is less than clamp voltage and more than the conducting voltage of protection diode.Second voltage
The value being closer to 0V is could be provided as, for example, second voltage is 0.1V or 0.2V.Second voltage may be arranged as other
As long as value less than first voltage and more than 0V, is not repeated herein.
For example, chip is provided with protection diode, and the first end of protection diode is corresponding with each grounding pin of chip
Liner electrical connection, second end is electrically connected with other I/O ports of chip.The conducting voltage of protection diode be 0.7V, clamper
Voltage is 2.0V, then it is 0.9V to set first voltage.It is understood that the value of first voltage can also be other values, as long as
Between conducting voltage and clamp voltage in protection diode, it is not repeated herein.
In specific implementation, when the voltage on tested grounding pin is less than first voltage, but is greater than second voltage, then
It can be determined that the tested normal principle of grounding pin connectivity is as follows：
When the voltage on tested grounding pin is less than first voltage, it is meant that tested grounding pin and protection diode with
And other I/O ports form access, therefore, the connectivity being tested between the corresponding liner of grounding pin is normal.If other
The equal connectivity of grounding pin is normal, and connects between the corresponding liner of tested grounding pin liner corresponding with other grounding pins
The general character is also normal, then is tested grounding pin and other grounding pins form access, therefore the voltage on tested grounding pin should be
Protection diode conducting voltage.
In specific implementation, when the voltage on tested grounding pin is less than second voltage, the tested grounding pin connection of judgement
Property is normal.
This is because：When all grounding pin connectivity of chip are normal, due to the corresponding lining of all grounding pins
Pad is coupled together, and therefore, corresponding pad of all grounding pins forms access between ground channel and driving circuit, this
When, the voltage, the voltage on other grounding pins that are tested on grounding pin are respectively less than second voltage.
In specific implementation, for each grounding pin, step S101~step S102 can be used and carry out connectivity
Test, continuity testing is carried out so as to fulfill all grounding pins to chip.
It can be seen that when the grounding pin to chip carries out continuity testing, the tested grounding pin of selection is simultaneously defeated to its
Go out driving current, remaining pin is coupled with ground channel or outside 0V voltage channels.By on the tested grounding pin that gets
Voltage and clamp voltage, you can knowing tested grounding pin, whether connectivity is bad, thus can effectively improve chip survey
The coverage of examination and accuracy.
It in specific implementation, can be with output alarm signal, with instruction when determining that tested grounding pin connectivity is bad
Tested grounding pin connectivity is bad.
For example, chip is tested by tester table.When detecting that tested grounding pin connectivity is bad, test
Board output alarm signal, to inform that it is bad that tester is currently tested grounding pin connectivity.
In specific implementation, in the alarm signal of output, the undesirable tested grounding lead footnote of connectivity can also be included
Know.In other words, the alarm signal of output is：Alarm signal including being tested grounding pin mark.
For example, during the test, determine that tested grounding pin is bad there are connectivity, and tested grounding pin is：It connects
Ground pin VSS1.In the alarm signal of output, including identifying " 1 ", mark " 1 " corresponds to grounding pin VSS1.According to alarm
Signal, tester would know that grounding pin VSS1 is bad there are connectivity.
Below by taking chip is there are two grounding pins as an example, to the chip ground pin provided in the above embodiment of the present invention
Continuity testing method illustrates.
With reference to Fig. 2, a kind of structure diagram of chip ground pin test system in the embodiment of the present invention, core are given
Piece grounding pin test system includes：Tester table 21, test board 22, continuous current source 23 and chip 24, chip 24 include
Two grounding pins, respectively VSS1 and VSS2, VSS1 correspond to 241, VSS2 of liner and correspond to liner 242, and pad 241 and liner
242 couplings.Protection diode 243, first end and 241 coupling of liner, the protection two of protection diode 243 are further included in chip 24
The second end of pole pipe 243 and 244 coupling of liner.244 are padded as other 245 corresponding liners of I/O ports, other I/O ports 245
It can include multiple ungrounded pins.
Protection diode 246, first end and 242 coupling of liner, the protection two of protection diode 246 are further included in chip 24
The second end of pole pipe 246 and 247 coupling of liner.247 are padded as other 248 corresponding liners of I/O ports, other I/O ports 248
It can include multiple ungrounded pins.
In practical applications, other I/O ports 245 can include identical I/O ports with other I/O ports 248.
Be provided on test board 22 ground tunnel ends, and ground tunnel ends respectively in the ground channel and chip 24 of tester table 21
Grounding pin VSS1 coupling.The output terminal in continuous current source 23 is coupled with the grounding pin VSS2 in chip 24.Clamp voltage
2V is set as, the first difference is 0.5V, first voltage 0.8V, second voltage 0.2V.
Before testing chip 24, other I/O ports 245, other I/O ports 248 voltage be set as 0V.
When testing chip 24, tester table 21 exports control signal to continuous current source 23.Continuous current source
23 upon the reception of control signals, and the driving current of 100 μ A is exported to grounding pin VSS2.
With reference to Fig. 2, in the embodiment of the present invention, continuity testing is carried out to the grounding pin of chip, as tests grounding lead
Whether connectivity between foot VSS1 and liner 241 normal, the connectivity between test grounding pin VSS2 and liner 242 whether
Normally.
When the voltage on grounding pin VSS2 is more than 1.9V, the difference between clamp voltage is less than 0.1V, the difference
Value is less than the first difference, therefore, judges that the connectivity between grounding pin VSS2 and liner 242 is bad, this is because：Work as ground connection
Voltage on pin VSS2 is more than 1.9V, it is meant that does not form access between grounding pin VSS2 and liner 242.
When the voltage on VSS2 is 0.7V, less than first voltage, therefore, judgement grounding pin VSS2 and liner 242 it
Between connectivity it is normal, grounding pin VSS1 and liner 241 between connection sexual abnormality, this is because：
When the voltage on grounding pin VSS2 is 0.7V, it is meant that protection diode 243 is connected, therefore, grounding pin
Connectivity between VSS2 and liner 242 is normal.If the connectivity between grounding pin VSS1 and liner 241 is normal, it is grounded
Pin VSS2, liner 242, liner 241, grounding pin VSS1 and ground tunnel ends forming circuit, therefore, on grounding pin VSS2
Voltage should be less than 0.2V rather than 0.7V；If the connectivity between grounding pin VSS1 and liner 241 is bad, grounding pin
VSS2 forms access with protection diode 243.
When the voltage on grounding pin VSS2 is less than 0.1V, and the voltage on grounding pin VSS1 is 0V, it is meant that connect
Ground pin VSS2, liner 242, grounding pin VSS1, liner 241 and ground tunnel ends forming circuit, therefore, judge grounding lead
Connectivity between foot VSS2 and liner 242 is normal, and the connectivity between grounding pin VSS1 and liner 241 is normal.
With reference to Fig. 3, a kind of chip ground pin connectivity testing device 30 in the embodiment of the present invention is given, including：
Control unit 301, acquiring unit 302 and identifying unit 303, wherein：
Control unit 301 for the tested grounding pin output driving current of the chip, and controls the chip to remove
Other pins except the tested grounding pin are coupled with ground channel or outside 0V voltage channels；
Acquiring unit 302, for obtaining the voltage on the tested grounding pin；
Identifying unit 303 for according to the voltage on the tested grounding pin, and combines preset clamp voltage, really
Whether connectivity is bad for the fixed tested grounding pin.
In specific implementation, the identifying unit 303, can be used for：When the voltage on the tested grounding pin and institute
When stating the difference of clamp voltage less than preset first difference, judge that the tested grounding pin connectivity is bad；When described tested
When voltage on grounding pin is less than preset first voltage and is more than preset second voltage, the tested grounding pin is judged
Connectivity is normal；When the voltage on the tested grounding pin is less than the second voltage, the judgement tested grounding pin connects
The general character is normal；The first voltage is less than the clamp voltage.
In specific implementation, the built-in chip type has protection diode, and the protection diode and all ground connection
The corresponding liner of pin couples；The first voltage is more than the conducting voltage of the protection diode.
In specific implementation, described control unit 301 can be used for controlling the quilt of preset driving circuit and the chip
It surveys grounding pin and establishes connection, and control the driving circuit to the tested grounding pin output driving current.
In specific implementation, the driving circuit can be continuous current source.
In specific implementation, the chip ground pin connectivity testing device 30 can also include：Output unit 304,
For output alarm signal, to indicate that the tested grounding pin connectivity is bad.
In specific implementation, the output unit 304 can be used for the report that output includes the tested grounding pin mark
Alert signal.
The embodiment of the present invention additionally provides a kind of computer readable storage medium, and computer readable storage medium is non-volatile
Property storage medium or non-transitory storage media, be stored thereon with computer instruction, when computer instruction operation performs this hair
It the step of chip ground pin continuity testing method provided in bright any of the above-described embodiment, is not repeated herein.
The embodiment of the present invention additionally provides another chip ground pin connectivity testing device, including memory and processing
Device, is stored with computer instruction on the memory, and when computer instruction operation performs any of the above-described embodiment of the present invention
It the step of chip ground pin continuity testing method of middle offer, is not repeated herein.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
It is completed with indicating relevant hardware by program, which can be stored in a computer readable storage medium, storage
Medium can include：ROM, RAM, disk or CD etc..
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (16)
- A kind of 1. chip ground pin continuity testing method, which is characterized in that including：To the tested grounding pin output driving current of the chip, and the chip is controlled in addition to the tested grounding pin Other pins and preset ground channel or the coupling of outside 0V voltage channels；The voltage on the tested grounding pin is obtained, and combines preset clamp voltage, determines that the tested grounding pin is No connectivity is bad.
- 2. chip ground pin continuity testing method as described in claim 1, which is characterized in that described to determine described be tested Whether connectivity is bad for grounding pin, including：When the voltage on the tested grounding pin and the difference of the clamp voltage are less than preset first difference, described in judgement Tested grounding pin connectivity is bad；When the voltage on the tested grounding pin is less than preset first voltage and is more than preset second voltage, institute is judged It is normal to state tested grounding pin connectivity；When the voltage on the tested grounding pin is less than the second voltage, the judgement tested grounding pin connectivity is just Often；The first voltage is less than the clamp voltage.
- 3. chip ground pin continuity testing method as claimed in claim 2, which is characterized in that the built-in chip type has guarantor Diode is protected, and protection diode liner corresponding with all grounding pins couples；The first voltage is more than described The conducting voltage of protection diode.
- 4. chip ground pin continuity testing method as described in claim 1, which is characterized in that described to the chip Tested grounding pin output driving current, including：Preset driving circuit is controlled to establish with the tested grounding pin to connect, and the driving circuit is controlled to be tested to described Grounding pin output driving current.
- 5. chip ground pin continuity testing method as claimed in claim 4, which is characterized in that the driving circuit is perseverance Flow current source.
- 6. chip ground pin continuity testing method as described in claim 1, which is characterized in that determining described tested connect After ground pin connectivity is bad, further include：Output alarm signal, to indicate that the tested grounding pin connectivity is bad.
- 7. chip ground pin continuity testing method as claimed in claim 6, which is characterized in that the output alarm signal Number, including：Output includes the alarm signal of the tested grounding pin mark.
- 8. a kind of chip ground pin connectivity testing device, which is characterized in that including：Control unit for the tested grounding pin output driving current of the chip, and controls the chip to remove the quilt Other pins surveyed except grounding pin are coupled with preset ground channel or outside 0V voltage channels；Acquiring unit, for obtaining the voltage on the tested grounding pin；Identifying unit for according to the voltage on the tested grounding pin, and combines preset clamp voltage, determines the quilt Surveying grounding pin, whether connectivity is bad.
- 9. chip ground pin connectivity testing device as claimed in claim 8, which is characterized in that the identifying unit is used In：When the voltage on the tested grounding pin and the difference of the clamp voltage are less than preset first difference, described in judgement Tested grounding pin connectivity is bad；When the voltage on the tested grounding pin is less than preset first voltage and is more than preset second voltage, institute is judged It is normal to state tested grounding pin connectivity；When the voltage on the tested grounding pin is less than the second voltage, the judgement tested grounding pin connectivity is just Often；The first voltage is less than the clamp voltage.
- 10. chip ground pin connectivity testing device as claimed in claim 9, which is characterized in that the built-in chip type has Protection diode, and protection diode liner corresponding with all grounding pins couples；The first voltage is more than institute State the conducting voltage of protection diode.
- 11. chip ground pin connectivity testing device as claimed in claim 8, which is characterized in that described control unit is used It is connected in the tested grounding pin of preset driving circuit with the chip is controlled to establish, and controls the driving circuit to described Tested grounding pin output driving current.
- 12. chip ground pin connectivity testing device as claimed in claim 11, which is characterized in that the driving circuit is Continuous current source.
- 13. chip ground pin connectivity testing device as claimed in claim 8, which is characterized in that further include：Output is single Member, for output alarm signal, to indicate that the tested grounding pin connectivity is bad.
- 14. chip ground pin connectivity testing device as claimed in claim 13, which is characterized in that the output unit, For exporting the alarm signal for including the tested grounding pin mark.
- 15. a kind of computer readable storage medium, is stored thereon with computer instruction, which is characterized in that the computer instruction Perform claim requires the step of 1~7 any one of them chip ground pin continuity testing method during operation.
- 16. a kind of chip ground pin connectivity testing device including memory and processor, is stored with meter on the memory Calculation machine instructs, which is characterized in that perform claim requires 1~7 any one of them chip ground during the computer instruction operation The step of pin continuity testing method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711383209.0A CN108181570B (en) | 2017-12-20 | 2017-12-20 | Chip grounding pin connectivity test method and device and readable storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711383209.0A CN108181570B (en) | 2017-12-20 | 2017-12-20 | Chip grounding pin connectivity test method and device and readable storage medium |
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| CN108181570B CN108181570B (en) | 2020-07-03 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020006749A1 (en) * | 2018-07-06 | 2020-01-09 | 深圳市汇顶科技股份有限公司 | Chip impedance testing method and system |
| CN110763981A (en) * | 2019-11-13 | 2020-02-07 | 苏州华兴源创科技股份有限公司 | Detection system and method for integrated circuit chip |
| CN113064041A (en) * | 2019-12-31 | 2021-07-02 | 圣邦微电子（北京）股份有限公司 | Method and device for measuring on-resistance of field effect transistor |
| CN113687218A (en) * | 2021-08-31 | 2021-11-23 | 上海威固信息技术股份有限公司 | Method for testing connectivity of power supply and ground pin of integrated circuit |
| CN116165519A (en) * | 2023-03-03 | 2023-05-26 | 深圳市鼎芯科技电子有限公司 | Chip ground pin connectivity testing device |
| CN116298802A (en) * | 2023-03-22 | 2023-06-23 | 镇江矽佳测试技术有限公司 | System and method for detecting quality of test board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1530662A (en) * | 2003-03-10 | 2004-09-22 | 盛群半导体股份有限公司 | Detecting method for integrated circuit |
| KR20050118767A (en) * | 2004-06-15 | 2005-12-20 | 박용수 | A measuring method for pin-to-pin defect of ic |
| CN103969544A (en) * | 2014-03-04 | 2014-08-06 | 东莞博用电子科技有限公司 | Integrated circuit high-voltage pin connectivity testing method |
| CN205608123U (en) * | 2016-03-17 | 2016-09-28 | 杭州长川科技股份有限公司 | A control module circuit for having more pin chip division short -circuit test |
| CN107192963A (en) * | 2017-06-22 | 2017-09-22 | 天津七六四通信导航技术有限公司 | A kind of circuit and implementation method that function is detected with short interruption |
-
2017
- 2017-12-20 CN CN201711383209.0A patent/CN108181570B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1530662A (en) * | 2003-03-10 | 2004-09-22 | 盛群半导体股份有限公司 | Detecting method for integrated circuit |
| KR20050118767A (en) * | 2004-06-15 | 2005-12-20 | 박용수 | A measuring method for pin-to-pin defect of ic |
| CN103969544A (en) * | 2014-03-04 | 2014-08-06 | 东莞博用电子科技有限公司 | Integrated circuit high-voltage pin connectivity testing method |
| CN205608123U (en) * | 2016-03-17 | 2016-09-28 | 杭州长川科技股份有限公司 | A control module circuit for having more pin chip division short -circuit test |
| CN107192963A (en) * | 2017-06-22 | 2017-09-22 | 天津七六四通信导航技术有限公司 | A kind of circuit and implementation method that function is detected with short interruption |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020006749A1 (en) * | 2018-07-06 | 2020-01-09 | 深圳市汇顶科技股份有限公司 | Chip impedance testing method and system |
| CN110763981A (en) * | 2019-11-13 | 2020-02-07 | 苏州华兴源创科技股份有限公司 | Detection system and method for integrated circuit chip |
| CN113064041A (en) * | 2019-12-31 | 2021-07-02 | 圣邦微电子（北京）股份有限公司 | Method and device for measuring on-resistance of field effect transistor |
| CN113064041B (en) * | 2019-12-31 | 2023-12-15 | 圣邦微电子（北京）股份有限公司 | Method and device for measuring on-resistance of field effect transistor |
| CN113687218A (en) * | 2021-08-31 | 2021-11-23 | 上海威固信息技术股份有限公司 | Method for testing connectivity of power supply and ground pin of integrated circuit |
| CN116165519A (en) * | 2023-03-03 | 2023-05-26 | 深圳市鼎芯科技电子有限公司 | Chip ground pin connectivity testing device |
| CN116165519B (en) * | 2023-03-03 | 2023-11-17 | 深圳市鼎芯科技电子有限公司 | Chip ground pin connectivity testing device |
| CN116298802A (en) * | 2023-03-22 | 2023-06-23 | 镇江矽佳测试技术有限公司 | System and method for detecting quality of test board |
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