WO2020006749A1 - Chip impedance testing method and system - Google Patents

Abstract

Provided are a chip impedance testing system and method, the chip impedance testing system comprising: a tester (20), the tester (20) comprising a device power supply, and the device power supply being connected to a ground pin of a chip to be tested (10) and an I/O port. By means of the device power supply, the tester (20) adjusts a voltage value at the ground pin, enabling the voltage value at the ground pin to be identical to a voltage value at a ground terminal of the tester (20). The tester (20) outputs, by means of the device power supply, a test current to the I/O port, measures a voltage value at the I/O port, and determines, according to the voltage value at the I/O port, the voltage value at the ground pin, and a value of the test current, a resistance value between the I/O port and the ground pin. The chip impedance testing system can accurately measure an internal impedance of a chip.

Description

Chip impedance test method and system Technical field

The embodiments of the present application relate to the technical field of electronic devices, and in particular, to a chip impedance test method and system.

Background technique

In the field of IC chip (Integrated Circuit) testing, Rdson (on-resistance equivalent to the equivalent on-resistance when the mos tube in the chip is on) and other impedances are often tested. In the existing test process, the accuracy of the impedance test in the IC chip is not high due to the influence of the impedance of the wire, the on-resistance of the relay, the contact impedance of the pin card, and the impedance due to contact and dirt.

Therefore, how to avoid the influence of environmental factors on testing has become an urgent problem.

Summary of the invention

In view of this, one of the technical problems solved by the embodiments of the present application is to provide a chip impedance test method and system to overcome the problem that the impedance test within a chip in the prior art is affected by external factors and has poor accuracy.

An embodiment of the present application provides a chip impedance test system, including: a tester, the tester includes a device power source, the device power source is connected to a ground pin and an I / O port of a chip to be tested, and the tester adjusts the ground pin through the device power source. The voltage value, so that the voltage value of the ground pin is the same as the voltage value of the ground terminal of the test machine; the test machine outputs a test current to the I / O port through the device power supply, and tests the voltage value at the I / O port, according to the I / O port The voltage value at, the voltage value at the ground pin, and the current value of the test current determine the resistance value between the I / O port and the ground pin.

Optionally, the test system further includes a LB board for testing, and a ground pin of the chip to be tested is connected to a ground terminal of the test machine through a first connection path of the LB board for testing.

Optionally, the voltage of the ground pin and the ground terminal of the tester is 0V.

Optionally, the device power supply includes a first power supply unit, and the first power supply unit is configured to be connected to a ground pin of a chip to be tested.

Optionally, the first power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal. Both the positive output terminal and the positive test terminal are connected to the ground pin, and the negative output terminal and the negative test terminal are both connected to the test machine. Ground connection.

Optionally, the device power supply includes a second power supply unit, and the second power supply unit is configured to be connected to the I / O port of the chip under test.

Optionally, the second power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal. Both the positive output terminal and the positive test terminal are connected to the I / O port, and the negative output terminal and the negative test terminal are connected to the test machine. The ground terminal is connected.

According to another aspect of the present application, a test method for a chip under test is provided. The tester adjusts the voltage value of the ground pin of the chip under test through the power supply of the device, so that the voltage value of the ground pin and the voltage value of the ground terminal in the test machine Equal; the tester outputs the test current from the I / O port of the chip to be tested through the power supply of the device, and tests the voltage value at the I / O port; the tester is based on the current value of the test current, the voltage value at the I / O port, and the test The voltage value of the ground pin of the chip determines the resistance value between the I / O port of the chip under test and the ground pin.

Optionally, the tester includes a first power supply unit, and the tester adjusts the voltage value of the ground pin of the chip under test through the device power supply, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the test machine, including: The first power supply unit supplies power to the ground pin of the chip under test, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the tester.

Optionally, the tester includes a second power supply unit, and the tester outputs a test current through an equipment power supply to the I / O port of the chip to be tested, and tests the voltage value at the I / O port, including: the second power supply unit of the tester passes The I / O port outputs a test current to the chip under test and tests the voltage value at the I / O port.

As can be seen from the above technical solutions, in the chip impedance test system of the embodiment of the present application, the voltage value of the ground pin of the chip under test is adjusted by using the equipment power in the test machine to make the voltage between the ground pin of the test machine and the ground terminal of the test machine The values are consistent, so that during the test, there is no voltage drop between the ground pin of the chip under test and the ground terminal of the test machine, thereby avoiding the ground pin of the chip under test and the ground terminal of the test machine in the prior art. After the connection, the voltage of the ground pin of the chip under test is not an ideal value due to the existence of the environmental resistance between the two, and the internal resistance test of the chip under test is inaccurate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely These are some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative labor.

1 is a schematic structural diagram of a chip impedance test system according to an embodiment of the present application;

FIG. 2 is a schematic flowchart of a chip impedance test method according to an embodiment of the present application.

Reference sign description:

10. Chip to be tested; 20. Test machine; 30. LB board for testing.

detailed description

In order to make the objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, The described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the embodiments of the present application.

The specific implementation of the embodiment of the present application will be further described below with reference to the accompanying drawings of the embodiment of the present application.

As shown in FIG. 1, according to an embodiment of the present application, a chip impedance test system includes: a tester 20, the tester 20 includes a device power source, and the device power source and a ground pin of the chip under test 10 (the test target shown in FIG. 1) GND at the chip 10) and I / O port connection, the tester 20 adjusts the voltage of the ground pin GND through the device power supply, so that the voltage of the ground pin GND is the same as the voltage of the ground terminal of the tester 20; the tester 20 Output the test current to the I / O port through the device power supply, and test the voltage value at the I / O port. Determine the I / O based on the voltage value at the I / O port, the voltage value at the ground pin GND, and the current value of the test current. The resistance value between the O port and the ground pin GND.

In the chip impedance test system, the equipment power of the testing machine 20 is used to force adjust the voltage value of the ground pin GND of the chip under test 10 so that the voltage value is equal to the voltage value of the ground terminal of the testing machine 20, so as to ensure that the chip is tested. During the test, there is no voltage difference between the ground pin GND of the chip under test 10 and the ground terminal of the test machine 20, thereby invalidating the environmental resistance between the ground pin GND and the ground terminal of the chip under test 10, and further The accuracy of the internal resistance test of the chip 10 to be tested is guaranteed. Use the equipment power supply to supply power to the I / O port of the chip under test 10, and control the passed current value as the test current to ensure the accuracy of the current during the test, thereby ensuring the accuracy of the test, and avoiding the impact of environmental resistance on the test accuracy .

In this embodiment, the test system further includes a test LB board 30, and the chip under test 10 and the tester 20 are connected through the test LB board 30 to improve the convenience of the connection and further improve the test efficiency.

For example, the ground pin GND of the chip under test 10 passes the first connection path of the LB board 30 for testing (ie, the path formed from point J to point I shown in FIG. 1), and the environmental resistance on it is equivalent to the resistances RG1 and The resistor RG2) is connected to the ground terminal of the tester 20.

The ground pin GND of the chip under test 10 passes through the second connection path of the test LB (Load Board) board 30 (that is, the path formed by the points A to E and B to F shown in FIG. 1, A The environmental resistance between point E and point E is equivalent to resistance RA1 and resistance RA2, and the environmental resistance between point B and point F is equivalent to RB1 and resistance RB2) and is connected to the equipment power supply of the tester 20. The second connection path is used to enable the power source of the device to supply power to the ground pin GND of the chip under test 10 to adjust its voltage value.

The I / O port of the chip under test 10 passes through the third connection path of the test LB board 30 (that is, the path formed from point C to point G and point D to point H shown in FIG. 1, where point C to point G The environmental resistance is equivalent to the resistance RC1 and the resistance RC2, and the environmental resistance from point D to the point H is equivalent to the resistance RD1 and the resistance RD2) and is connected to the equipment power source of the testing machine 20. The third connection path is used for powering the device power supply to the I / O port of the chip under test 10 to output a test current.

Optionally, in this embodiment, the power supply of the device includes a first power supply unit (ie, DPS1 shown in FIG. 1), and the first power supply unit DPS1 is configured to be connected to the ground pin GND of the chip under test 10 to adjust the ground The voltage value of pin GND.

Specifically, the first power supply unit includes a positive output terminal (the F + port of DPS1 shown in FIG. 1, that is, the positive output terminal of the device power supply), and a negative output terminal (the F- port of DPS1 shown in FIG. 1, that is, The negative output terminal of the device power supply), the positive test terminal (the S + port of DPS1 shown in Figure 1, that is, the positive sampling terminal of the device power supply), and the negative test terminal (the S-port of DPS1 shown in Figure 1) , That is, the negative sampling terminal of the device power supply), the positive output terminal F + and the positive test terminal S + are connected to the ground pin GND, and the negative output terminal F- and the negative test terminal S- are connected to the ground terminal of the tester 20.

Since the negative output terminal F- and the negative test terminal S- of the first power supply unit DSP1 are both connected to the ground terminal of the testing machine 20, its potential value is equal to the potential value of the ground terminal of the testing machine 20. Generally, the potential value of the ground terminal of the testing machine 20 is 0V. Therefore, in this embodiment, the potential value of the ground terminal is 0V for example, that is, the first power supply unit DPS1 adjusts the voltage value of the ground pin GND to 0V. Of course, in other embodiments, the potential value may be other values.

Through the positive output terminal F + of the first power supply unit DPS1, the ground pin GND output of the chip 10 to be tested can be adjusted to 0V, so that the voltage value of the ground pin GND is equal to the voltage value of the ground terminal, thereby ensuring that During the test, there was no voltage drop between the two, thereby shielding the environmental resistance between the ground pin GND and the ground terminal (resistors RG1 and RG2 shown in Figure 1).

The positive test terminal S + of the first power supply unit DPS1 is used to accurately test the voltage value of the ground pin GND, so as to provide feedback data for the testing machine 20 so that it can adjust the positive output terminal F + of the first power supply unit DPS1 through the feedback data. Output. For example, the testing machine further includes a control unit, which is connected to the first power supply unit DPS1 and adjusts the output of the positive output terminal F + according to the voltage value detected by the positive test terminal S +.

In this embodiment, the device power supply includes a second power supply unit DPS2, and the second power supply unit DPS2 is used to connect to the I / O port of the chip under test 10 to output a test current to the I / O port and measure the I / O port The voltage value.

Specifically, the second power supply unit DPS2 includes a positive output terminal F +, a negative output terminal F-, a positive test terminal S +, and a negative test terminal S-. The positive output terminal F + and the positive test terminal S + are connected to the I / O port, and the negative output terminal. Both F- and the negative test terminal S- are connected to the ground terminal of the tester 20.

Similar to the negative output terminal and the negative test terminal of the first power supply unit DPS1, the negative output terminal and the negative test terminal of the second power supply unit DPS2 are also connected to the ground terminal of the testing machine 20. Its function is similar to the negative output terminal and the negative test terminal of the first power supply unit DPS1, which will not be repeated here.

The positive output terminal F + of the second power supply unit DPS2 is used to output a test current to the I / O port. The positive test terminal S + of the second power supply unit DPS2 is used to test the voltage value of the I / O port. Because the internal resistance of the positive test terminal S + is close to infinite, the positive test terminal S + and the I / O port are further increased. The environmental resistance value does not affect the test of the voltage value of the I / O port, thereby avoiding the impact of the environmental resistance on the I / O port side on the test accuracy.

The tester can be an ATE (Automatic Test Equipment) tester. The device power supply can be a self-provided power supply (DPS, device power supply) inside the ATE tester.

The chip impedance test system uses the DPS resources of the ATE tester to accurately measure Rdson (internal resistance) or other impedance methods. Compared with the previous impedance test, this application uses a Kelvin four wire formed between the DPS that comes with the test machine and the ground pin of the chip under test 10 instead of the original one-way (F +, S +) solution. This makes it possible to accurately measure impedances such as Rdson without adding external resources.

The test is performed by using the positive output terminal and the positive test terminal of the two power supply units in the equipment power supply. The existing negative output terminal and negative test terminal of the power supply unit are used to connect to the ground terminal of the test machine, so the environment of the ground terminal cannot be offset. Problems with impedance.

Using this system, even a low-profile ATE tester can accurately measure the internal resistance (Rdson) or other impedances with its own equipment power supply. It solves the problem that in the prior art, as the configuration of the test machine becomes higher, the test cost becomes higher. If the resource-rich test machine is replaced simply because of an on-resistance test requirement, the cost will become very high.

Use the DPS unit of the tester to connect to the ground pin GND of the chip under test 10 to make it correct the potential difference between the ground pin GND of the chip under test 10 and the ground terminal of the test machine so that the potential difference is 0. In order to achieve the purpose of accurate measurement of internal resistance (Rdson).

As shown in FIG. 2, according to another aspect of the present application, a method for testing a chip under test is provided, which includes the following steps:

Step S102: The testing machine 20 adjusts the voltage value of the ground pin GND of the chip under test 10 through the device power source, so that the voltage value of the ground pin GND is equal to the voltage value of the ground terminal in the testing machine 20.

For example, in a feasible way, by connecting the device power to the ground pin GND of the chip under test 10, the device power is output to the ground pin GND to forcibly adjust its voltage value to be equal to the voltage of the ground terminal.

Optionally, the tester 20 includes a first power supply unit. In step 102, the first power supply unit is connected to the ground pin GND, and power is supplied to the ground pin GND of the chip 10 to be tested through the first power supply unit, so that the ground lead The voltage value of the pin GND is equal to the voltage value of the ground terminal in the testing machine 20.

Step S104: The tester 20 outputs a test current to the I / O port of the chip under test 10 through the device power source, and tests the voltage value at the I / O port.

For example, in a feasible manner, an I / O port of the chip under test 10 outputs a current of 10 mA through a device power source. Of course, the current value may be any appropriate current value, and is not limited to the exemplified 10 mA.

Optionally, the tester 20 includes a second power supply unit. In step S104, the second power supply unit is connected to the I / O port. The second power supply unit outputs a test current to the chip under test 10 through the I / O port, and tests. The voltage value at the I / O port.

Step S106: Determine the distance between the I / O port of the chip under test 10 and the ground pin GND according to the current value of the test current, the voltage value at the I / O port, and the voltage value of the ground pin GND of the chip under test 10. resistance.

The internal resistance value between the I / O port of the chip under test and the ground pin GND (denoted as R) is equal to the voltage value of the I / O port minus the voltage value of the ground pin GND, divided by the test current. Current value.

In this method, the voltage value of the ground pin GND is forcibly adjusted by the power supply of the device, so that there is no voltage difference between the ground pin and the ground terminal, thereby ensuring that the environmental resistance between the ground pin and the ground terminal of the test machine is not. Will affect the test of the internal resistance R. Use the equipment power supply to detect the voltage value at the I / O port and calculate the internal resistance R based on the voltage value to ensure that the environmental resistance between the I / O port and the tester will not affect the test of the internal resistance R, thereby ensuring the internal resistance Test accuracy.

By this method, the environmental resistance existing in the existing testing process is avoided, for example, the resistance on the LB board 30 for testing, the impedance of the wire (including the on-resistance of the relay on the line, etc.), The contact impedance and the like, and the wiring or contact impedance and the like between the test LB board 30 and the tester. The voltage across the internal resistance R and the current through the internal resistance R can be accurately obtained through the second power supply unit, so that the impedance of the internal resistance R can be accurately calculated.

The specific process of this test is:

As shown in FIG. 1, the voltage value of the first power supply unit DPS1 is forcibly output (Force) 0V, that is, the potential of the point A in FIG. 1 is 0V through the first power supply unit DPS1. The ground terminal of the testing machine 20 is connected to the negative output terminal F-, the negative test terminal S- of the first power supply unit DPS1, the negative output terminal F- and the negative test terminal S- of the second power supply unit DPS2. Therefore, when the first power supply unit DPS1 makes the voltage value of point A 0V, its positive output terminal F + will make the E potential point lower than that of the ground terminal of the testing machine, so that the current flows back from the positive output terminal F + path of the first power supply unit DPS1. . At this time, the ground terminal of the testing machine, the negative output terminal F- of the first power supply unit DPS1, the negative output terminal F- of the second power supply unit DPS2, and the ground pin GND of the chip under test 10 are at the same potential point.

The second power supply unit DPS2 forcibly outputs (Force) 10 mA (denoted as I1) (specifically adjusted according to the actual situation), and the second power supply unit DPS2 can measure the voltage at point D (denoted as V1).

Internal resistance R = V1 / I1 Calculate the resistance value of internal resistance R. In this case, the ground pin GND is equal to 0V.

By using this method, when the test machine does not have DPS-, the potential point of the ground pin GND of the chip under test 10 is accurately adjusted by DPS +, so that the measurement impedance is more accurate, and it is not necessary to replace the high-end test machine, and the circuit is simple to implement.

Below is an example of a prior art measurement method to compare effects.

In the prior art, the ground pin of the chip under test 10 is directly connected to the ground terminal of the test machine, and then the I / O port of the chip under test is output and an internal resistance test is performed. In this process, the voltage value of the default ground pin is equal to the voltage value of the ground terminal, which is 0V.

In this case, when calculating the impedance R: the device power supply DPS forced output (Force) 10mA (recorded as I2), the potential at point D (recorded as V2), then the R value is actually V2 / I2, because The calculated R = R0 (the actual internal resistance of the chip under test) + RG1 + RG2 calculated by the presence of the environmental resistance. There is a certain error between the calculated result R and the actual internal resistance R0.

Assumptions: Actual internal resistance R0 = 5, RG = 6, RA = 7, RB = 8, RC = 9, RD = 10, unit (ohm). RG is RG1 + RG2, and RA, RB, RC, and RD are the same.

In the prior art scheme: DPS forced output (Force) 10mA, then the ground terminal potential point of the test bench is 0V, the potential at point J is RG * 10mA = 60mV, the voltage at point D is measured as 110mV, and the calculated internal resistance R is: 110mV divided At 10 mA = 11 ohms.

The solution of this application: Forced output (Force) 0V from the first power supply unit DPS1, Forced output (Force) 10mA from the second power supply unit DPS2, the potential point of the ground terminal of the testing machine is 0V, and the ground pin GND of the chip 10 to be tested is also It is 0V and the potential at point E is -70mV. Measure the voltage at point D as 50mV, and calculate the internal resistance R as 50mV divided by 10mA = 5 ohms. It can be seen that the scheme measurement of the present application is more accurate.

Finally, it should be noted that the above embodiments are only used to describe the technical solutions of the embodiments of the present application, and are not limited thereto. Although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand : It can still modify the technical solutions described in the foregoing embodiments, or replace some of the technical features equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions separate from the technical solutions of the embodiments of the present application. Spirit and scope.

Claims (10)

A chip impedance test system includes a tester, the tester includes a device power source, the device power source is connected to a ground pin and an I / O port of a chip to be tested, Adjusting the voltage value of the ground pin by the testing machine through the power supply of the device, so that the voltage value of the ground pin is the same as the voltage value of the ground terminal of the testing machine; The tester outputs a test current to the I / O port through the power supply of the device, and tests a voltage value at the I / O port, according to the voltage value at the I / O port, the ground pin The voltage value at and the current value of the test current determine a resistance value between the I / O port and the ground pin. The chip open-short test device according to claim 1, wherein the test system further comprises a test LB board, and a ground pin of the chip under test is connected to the test LB board through a first connection path of the test LB board. The ground terminal of the tester is connected. The chip impedance test system according to claim 1 or 2, wherein a voltage value of the ground pin and a ground terminal of the tester is 0V. The chip impedance test system according to claim 1, wherein the device power supply comprises a first power supply unit, and the first power supply unit is configured to be connected to a ground pin of the chip under test. The chip impedance test system according to claim 4, wherein the first power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal, and the positive output terminal and the positive test terminal are both The ground pin is connected, and the negative output terminal and the negative test terminal are both connected to the ground terminal of the tester. The chip impedance test system according to any one of claims 1-5, wherein the device power supply includes a second power supply unit, and the second power supply unit is used for I / O with the chip to be tested Port connection. The chip impedance test system according to claim 6, wherein the second power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal, and the positive output terminal and the positive test terminal are both The I / O port is connected, and the negative output terminal and the negative test terminal are both connected to the ground terminal of the tester. A test method for a chip to be tested is characterized in that: The testing machine adjusts the voltage value of the ground pin of the chip under test through the power supply of the device, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the testing machine; The tester outputs a test current to an I / O port of the chip under test through a device power source, and tests a voltage value at the I / O port; The tester determines the I / O port of the chip under test and the voltage of the chip under test according to the current value of the test current, the voltage value at the I / O port, and the voltage value of the ground pin of the chip under test. The resistance value between the ground pins is described. The method according to claim 8, characterized in that the testing machine comprises a first power supply unit, and the testing machine adjusts the voltage value of the ground pin of the chip under test through a device power source so that the ground pin The voltage value is equal to the voltage value of the ground terminal in the tester, including: Power is supplied to the ground pin of the chip under test through the first power supply unit, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the tester. The method according to claim 8, wherein the tester comprises a second power supply unit, and the tester outputs a test current to an I / O port of the chip under test through a device power supply, and tests the I / O port voltage value, including: The second power supply unit of the testing machine outputs a test current to the chip under test through the I / O port, and tests a voltage value at the I / O port.

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