CN113687218A - Method for testing connectivity of power supply and ground pin of integrated circuit - Google Patents

Method for testing connectivity of power supply and ground pin of integrated circuit Download PDF

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Publication number
CN113687218A
CN113687218A CN202111013227.6A CN202111013227A CN113687218A CN 113687218 A CN113687218 A CN 113687218A CN 202111013227 A CN202111013227 A CN 202111013227A CN 113687218 A CN113687218 A CN 113687218A
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integrated circuit
tested
current
power supply
pin
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CN113687218B (en
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吴佳
李礼
吴叶楠
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Shanghai V&g Information Technology Co ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52Testing for short-circuits, leakage current or ground faults
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54Testing for continuity

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a method for testing the connectivity of a power supply pin and a ground pin of an integrated circuit, which is used for building a test system, connecting a certain power supply pin and a ground pin in the integrated circuit to be tested in turn with a current and voltage measurement module of the test system, respectively testing the current values of the power supply pin and the ground pin introduced into the test system, and judging whether the connectivity is qualified according to the test result. The invention can eliminate the hidden trouble of the failure of the power supply pin or the ground pin of the part of the tested integrated circuit and the test system by a step-by-step distinguishing and comparing method.

Description

Method for testing connectivity of power supply and ground pin of integrated circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for testing the connectivity of a power supply pin and a ground pin of an integrated circuit.
Background
In the field of integrated circuits, the yield limits limit, and a certain proportion of the integrated circuits which are just produced are invalid. Therefore, the integrated circuit needs to be connected with a test system for testing after the production is completed. And the product can be supplied only when the test is qualified. If the pin of the integrated circuit to be tested is disconnected with the test system or the pin of the integrated circuit to be tested is short-circuited when the test system is connected, the test of the integrated circuit to be tested cannot be completed. Therefore, when testing an integrated circuit, it is necessary to test the connectivity between the integrated circuit under test and the test system.
The earliest connectivity test method was to visually observe whether the ic under test is normally connected to the test system, which is slow and inefficient, and not only consumes manpower and material resources.
The conventional test method for the connectivity of the power supply pin and the ground pin of the integrated circuit at present comprises the following steps: the connectivity is automatically tested using the characteristic of lower resistance between the power pin and ground. The ground pin of the tested integrated circuit is grounded, the input and output pins are suspended or grounded, and then the power supply pin is applied with a voltage of 50 millivolts to 200 millivolts. If the power supply pin and ground pin are normally connected to the test system, the current between the power supply pin and ground is typically greater than 1 microampere and less than the standby current of the integrated circuit. If the current between the power supply pin and the ground is less than 1 microampere, the power supply pin or the ground pin is judged to be disconnected with the test system; and if the current between the power pin and the ground is larger than the standby current of the integrated circuit, judging that a short circuit occurs inside the integrated circuit to be tested or between the power pin and the ground pin.
The traditional method can find the open circuit between the power supply pin or the ground pin and the test system, and can also find the short circuit in the integrated circuit to be tested or between the power supply pin and the ground pin. However, as the power consumption of an integrated circuit increases, the power supply pin and the ground pin of the integrated circuit are often more than one. When the tested integrated circuit has a plurality of power supply pins and ground pins, the existing method cannot find the disconnection of part of the power supply pins or the ground pins and the test system, so that the failure report of the event of connectivity failure occurs. When part of the power supply pins or the ground pins and the test system are disconnected, power supply may be insufficient, certain functional tests may be unqualified, and the unqualified function tests of the integrated circuit are mistakenly reported. Therefore, the traditional method for testing the connectivity of the power supply pin and the ground pin of the integrated circuit has the hidden danger of missing the disconnection between the power supply pin or the ground pin of the tested integrated circuit and the test system.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the method for testing the connectivity of the power supply and the ground pin of the integrated circuit, which has the advantages of simple principle, easy realization and wide application range.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for testing the connectivity of power and ground pins of an integrated circuit, comprising the steps of:
step S100: building a test system; connecting all pins of the integrated circuit to be tested with a test system, connecting all ground pins of the integrated circuit to be tested with ground by the test system, and suspending all the rest pins;
step S200: connecting a certain power supply pin in the integrated circuit to be tested with a current and voltage measuring module of the test system; the port A of the current-voltage measuring module of the test system outputs a voltage V1, the current-voltage measuring module of the test system judges whether a current I1 passing through the port A is larger than a threshold current Ith1 and smaller than a threshold current Ith2, if I1 is larger than Ith1 and smaller than Ith2, the step S300 is executed, otherwise, the step S700 is executed;
step S300: repeating the step S200 for the next power pin in the integrated circuit to be tested until the test of all the power pins is completed; step S400 is executed;
step S400: the testing system connects all power supply pins of the integrated circuit to be tested to the ground, one of the pins of the integrated circuit to be tested is connected with the current and voltage measuring module of the testing system, the rest pins are suspended, the port A of the current and voltage measuring module of the testing system outputs the voltage V2, the current and voltage measuring module of the testing system judges whether the current I2 passing through the port A is larger than the threshold current Ith3 and smaller than the threshold current Ith4, if I2 is larger than Ith3 and smaller than Ith4, the step S500 is executed, otherwise, the step S700 is executed;
step S500: repeating the step S400 for the next ground pin in the integrated circuit to be tested until all the ground pins are tested; step S600 is executed;
step S600: the connectivity of the power supply pin and the ground pin of the tested integrated circuit is tested to be qualified;
step S700: and the tested integrated circuit power supply pin and the ground pin are unqualified in connectivity test.
The V1 and V2 are voltage excitations applied by the test system.
As a further improvement of the invention: the V1 is greater than 0.1V and less than VDD, which is the recommended operating voltage for the power pin.
As a further improvement of the invention: the Ith1 and Ith2 were determined by a blinding test.
As a further improvement of the invention: the V2 is less than-0.1V and greater than-VDD.
As a further improvement of the invention: the Ith3 and Ith4 were determined by a blinding test.
Compared with the prior art, the invention has the advantages that:
the method for testing the connectivity of the power supply pin and the ground pin of the integrated circuit is simple in principle and easy to realize, does not need to change the existing integrated circuit testing system in a large amount, can be suitable for various application scenes, and can eliminate the hidden trouble of missing report of the disconnection of the power supply pin or the ground pin of the tested integrated circuit and the testing system by a step-by-step comparison method.
Drawings
FIG. 1 is a schematic flow diagram of the process of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in FIG. 1, the method for testing the connectivity of the power and ground pins of the integrated circuit of the present invention comprises the following steps:
step S100: building a test system; connecting all pins of the integrated circuit to be tested with a test system, connecting all ground pins of the integrated circuit to be tested with ground by the test system, and suspending all the rest pins;
step S200: connecting a certain power supply pin in the integrated circuit to be tested with a current and voltage measuring module of the test system; the port A of the current-voltage measuring module of the test system outputs a voltage V1, the current-voltage measuring module of the test system judges whether a current I1 passing through the port A is larger than a threshold current Ith1 and smaller than a threshold current Ith2, if I1 is larger than Ith1 and smaller than Ith2, the step S300 is executed, otherwise, the step S700 is executed;
step S300: repeating the step S200 for the next power pin in the integrated circuit to be tested until the test of all the power pins is completed; step S400 is executed;
step S400: the testing system connects all power supply pins of the integrated circuit to be tested to the ground, one of the pins of the integrated circuit to be tested is connected with the current and voltage measuring module of the testing system, the rest pins are suspended, the port A of the current and voltage measuring module of the testing system outputs the voltage V2, the current and voltage measuring module of the testing system judges whether the current I2 passing through the port A is larger than the threshold current Ith3 and smaller than the threshold current Ith4, if I2 is larger than Ith3 and smaller than Ith4, the step S500 is executed, otherwise, the step S700 is executed;
step S500: repeating the step S400 for the next ground pin in the integrated circuit to be tested until all the ground pins are tested; step S600 is executed;
step S600: the connectivity of the power supply pin and the ground pin of the tested integrated circuit is tested to be qualified;
step S700: and the tested integrated circuit power supply pin and the ground pin are unqualified in connectivity test.
The V1 and V2 are voltage excitations applied by the test system.
In a specific application example, V1 is greater than 0.1V and less than VDD, which is the recommended operating voltage for the power pin.
In a specific application example, the Ith1 and Ith2 are determined by a thorough test.
In a specific application example, the V2 is less than-0.1V and greater than-VDD.
In a specific application example, the Ith3 and Ith4 are determined by a thorough test.
In a specific application example, the detailed steps of the invention comprise:
step S1: connecting all pins of an integrated circuit to be tested with a test system, wherein the integrated circuit to be tested has M power supply pins and N ground pins;
step S2: the test system connects all ground pins of the tested integrated circuit to ground, and all the other pins are suspended, and i is set to be 0;
step S3: if the i is equal to M, go to step S8, otherwise go to step S4;
step S4: connecting the ith power supply pin with a current and voltage measuring module of a test system;
step S5: port a of the current voltage measurement module of the test system outputs a voltage V1. V1 is greater than 0.1V and less than VDD. VDD is the recommended operating voltage of the ith power pin;
step S6: the current-voltage measuring module of the test system determines whether the current I1 passing through the port A is greater than the threshold current Ith1 and less than the threshold current Ith2, and goes to step S7 if I1 is greater than Ith1 and less than Ith2, otherwise goes to step S15. Preferably, Ith1 and Ith2 are determined by empirical testing;
step S7: suspending the ith power supply pin, i being i +1, and turning to step S3;
step S8: the test system connects all power supply pins of the tested integrated circuit to ground, and all the other pins are suspended, and j is set to be 0;
step S9: if j is equal to N, go to step S14, otherwise go to step S10;
step S10: connecting the jth ground pin with a current and voltage measuring module of the test system;
step S11: port a of the current voltage measurement module of the test system outputs a voltage V2. V2 is less than-0.1V and greater than-VDD;
step S12: the current-voltage measuring module of the test system determines whether the current I2 passing through the port A is greater than the threshold current Ith3 and less than the threshold current Ith4, and goes to step S13 if I2 is greater than Ith3 and less than Ith4, otherwise goes to step S15. Preferably, Ith3 and Ith4 are determined by empirical testing;
step S13: suspending the jth ground pin, j being j +1, and turning to step S9;
step S14: the connectivity of the power supply pin and the ground pin of the tested integrated circuit is tested to be qualified;
step S15: the connectivity test of the power supply pin and the ground pin of the tested integrated circuit is unqualified;
the above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims (3)

1. A method for testing the connectivity of power and ground pins of an integrated circuit, comprising the steps of:
step S100: building a test system; connecting all pins of the integrated circuit to be tested with a test system, connecting all ground pins of the integrated circuit to be tested with ground by the test system, and suspending all the rest pins;
step S200: connecting a certain power supply pin in the integrated circuit to be tested with a current and voltage measuring module of the test system; the port A of the current-voltage measuring module of the test system outputs a voltage V1, the current-voltage measuring module of the test system judges whether a current I1 passing through the port A is larger than a threshold current Ith1 and smaller than a threshold current Ith2, if I1 is larger than Ith1 and smaller than Ith2, the step S300 is executed, otherwise, the step S700 is executed;
step S300: repeating the step S200 for the next power pin in the integrated circuit to be tested until the test of all the power pins is completed; step S400 is executed;
step S400: the testing system connects all power supply pins of the integrated circuit to be tested to the ground, one of the pins of the integrated circuit to be tested is connected with the current and voltage measuring module of the testing system, the rest pins are suspended, the port A of the current and voltage measuring module of the testing system outputs the voltage V2, the current and voltage measuring module of the testing system judges whether the current I2 passing through the port A is larger than the threshold current Ith3 and smaller than the threshold current Ith4, if I2 is larger than Ith3 and smaller than Ith4, the step S500 is executed, otherwise, the step S700 is executed;
step S500: repeating the step S400 for the next ground pin in the integrated circuit to be tested until all the ground pins are tested; step S600 is executed;
step S600: the connectivity of the power supply pin and the ground pin of the tested integrated circuit is tested to be qualified;
step S700: and the tested integrated circuit power supply pin and the ground pin are unqualified in connectivity test.
2. The method of claim 1, wherein V1 is greater than 0.1V and less than VDD.
3. The method of claim 1, wherein V2 is less than-0.1V and greater than-VDD.
CN202111013227.6A 2021-08-31 2021-08-31 Method for testing connectivity of power supply and ground pins of integrated circuit Active CN113687218B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114325341A (en) * 2021-12-31 2022-04-12 北京小马智行科技有限公司 Test equipment and test system of circuit board

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003524190A (en) * 2000-02-23 2003-08-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Integrated circuit with test interface
US20080030217A1 (en) * 2006-08-02 2008-02-07 Texas Instruments Incorporated Systems and Methods for Continuity Testing Using a Functional Pattern
CN101315409A (en) * 2007-05-28 2008-12-03 比亚迪股份有限公司 Mobile phone circuit board testing method
CN103698654A (en) * 2013-12-28 2014-04-02 珠海全志科技股份有限公司 Open circuit short circuit test device and test method of chip base pin
US20140285229A1 (en) * 2013-03-22 2014-09-25 Texas Instruments Incorporated Testing Integrated Circuit Packaging for Shorts
CN104965165A (en) * 2015-07-13 2015-10-07 江苏杰进微电子科技有限公司 Small and micro-sized integrated circuit reliability tester and test method thereof
US20150362550A1 (en) * 2014-06-11 2015-12-17 Allegro Microsystems, Llc Circuits and Techniques for Detecting an Open Pin Condition of an Integrated Circuit
CN108181570A (en) * 2017-12-20 2018-06-19 上海东软载波微电子有限公司 Chip ground pin continuity testing method and device, readable storage medium storing program for executing
CN207601213U (en) * 2017-12-07 2018-07-10 英业达科技有限公司 Multiple power supplys of central processing unit slot and grounding leg position conduction detecting system
CN109901001A (en) * 2017-12-07 2019-06-18 英业达科技有限公司 The multiple power supplys and grounding leg position conduction detecting system and its method of central processing unit slot
CN110244174A (en) * 2019-06-26 2019-09-17 上海闻泰信息技术有限公司 The test circuit of data-interface
CN112130089A (en) * 2020-08-27 2020-12-25 深圳市广和通无线股份有限公司 Module pin connectivity testing device and system
CN113049946A (en) * 2021-03-24 2021-06-29 山东英信计算机技术有限公司 Board card test system

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003524190A (en) * 2000-02-23 2003-08-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Integrated circuit with test interface
US20080030217A1 (en) * 2006-08-02 2008-02-07 Texas Instruments Incorporated Systems and Methods for Continuity Testing Using a Functional Pattern
CN101315409A (en) * 2007-05-28 2008-12-03 比亚迪股份有限公司 Mobile phone circuit board testing method
US20140285229A1 (en) * 2013-03-22 2014-09-25 Texas Instruments Incorporated Testing Integrated Circuit Packaging for Shorts
CN103698654A (en) * 2013-12-28 2014-04-02 珠海全志科技股份有限公司 Open circuit short circuit test device and test method of chip base pin
US20150362550A1 (en) * 2014-06-11 2015-12-17 Allegro Microsystems, Llc Circuits and Techniques for Detecting an Open Pin Condition of an Integrated Circuit
CN104965165A (en) * 2015-07-13 2015-10-07 江苏杰进微电子科技有限公司 Small and micro-sized integrated circuit reliability tester and test method thereof
CN207601213U (en) * 2017-12-07 2018-07-10 英业达科技有限公司 Multiple power supplys of central processing unit slot and grounding leg position conduction detecting system
CN109901001A (en) * 2017-12-07 2019-06-18 英业达科技有限公司 The multiple power supplys and grounding leg position conduction detecting system and its method of central processing unit slot
CN108181570A (en) * 2017-12-20 2018-06-19 上海东软载波微电子有限公司 Chip ground pin continuity testing method and device, readable storage medium storing program for executing
CN110244174A (en) * 2019-06-26 2019-09-17 上海闻泰信息技术有限公司 The test circuit of data-interface
CN112130089A (en) * 2020-08-27 2020-12-25 深圳市广和通无线股份有限公司 Module pin connectivity testing device and system
CN113049946A (en) * 2021-03-24 2021-06-29 山东英信计算机技术有限公司 Board card test system

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
任致程;: "JEC-2型集成电路业余测试方法", 电气时代, no. 09, 16 September 1985 (1985-09-16), pages 15 - 17 *
任致程;: "JEC-2型集成电路业余测试方法", 电气时代, no. 09, pages 15 - 17 *
朱贤文;肖勇;田阳;王子衡;谷建成;颜湘武;何佳;: "电动汽车直流充电互操作性测试方法研究", 电测与仪表, no. 04, 25 February 2020 (2020-02-25), pages 22 - 29 *
朱贤文;肖勇;田阳;王子衡;谷建成;颜湘武;何佳;: "电动汽车直流充电互操作性测试方法研究", 电测与仪表, no. 04, pages 22 - 29 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114325341A (en) * 2021-12-31 2022-04-12 北京小马智行科技有限公司 Test equipment and test system of circuit board
CN114325341B (en) * 2021-12-31 2023-12-15 北京小马智行科技有限公司 Test equipment and test system of circuit board

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Application publication date: 20211123

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Denomination of invention: A testing method for power and ground pin connectivity of integrated circuits

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