CN101196556A - SOC for parallel test judgement and its implementing method - Google Patents
SOC for parallel test judgement and its implementing method Download PDFInfo
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- CN101196556A CN101196556A CNA2006101192841A CN200610119284A CN101196556A CN 101196556 A CN101196556 A CN 101196556A CN A2006101192841 A CNA2006101192841 A CN A2006101192841A CN 200610119284 A CN200610119284 A CN 200610119284A CN 101196556 A CN101196556 A CN 101196556A
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Abstract
The invention relates to a mensurability integrated circuit device and discloses an SOC for judging the parallel test, which comprises the test interface and at least two NVM, and also comprises a test controlling module, used for receiving the finished signal of each NVM and output to the test interface after the logical decision; an erasing/writing controlling module, used for receiving the test vector exerted the above test interface and then transmit the test vector to each NVM; reading controlling module, used for receiving the read command vector exerted by the above test interface, read the data out from each NVM and output to the test interface for comparison after logical processing on the data. The invention also discloses a judging method for realizing the parallel test by SOC. The SOC conducting the judgment on the parallel test in the invention can save much time of mass production test and effectively reduce the test cost.
Description
Technical field
The present invention relates to the measurability integrated circuit (IC) apparatus, relate in particular to a kind of SOC (System on Chip, integrated system single-chip) and its implementation of carrying out parallel test judgement.
Background technology
When among the SOC during embedded polylith NVM (non-volatility memorizer) since NVM wipe/to write the time long, often selects timesharing to save the test duration with survey.For the timesharing that realizes polylith NVM with surveying, typically use the multiplexing method of a cover test interface, come the time-sharing multiplex pin by judgement, and the control test machine is realized the timesharing test (see figure 1) of polylith NVM to the end signal of each NVM.Though such scheme has solved the measurability of polylith NVM by pin multiplexing, but because each NVM concluding time is unfixing, to just can carry out the action that next step wiped/write test according to judging whether execution of a last NVM respectively, providing after the end signal.And when reading when action, each NVM timesharing reads then and is compared respectively by the peripheral test machine.The most of serial of this class testing is carried out, and the wiping of NVM/write the time is the formation main body of chip testing time often, should existing method test duration be doubly taking advantage of of polylith NVM therefore, the testing cost height.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of SOC that carries out parallel test judgement, can effectively save the test duration, reduces testing cost.For this reason, the present invention also will provide a kind of this SOC to realize the method for parallel test judgement.
In order to solve the problems of the technologies described above, the SOC that the present invention carries out parallel test judgement comprises test interface and at least two NVM, also comprises:
Testing control module, with test interface, NVM, wiping/write control module with read control module and be connected, be used to receive the end signal of each NVM, and this end signal is exported to test interface after logic decision, or wipe/write control module or read control module according to this end signal control;
Wipe/write control module, be connected, be used to receive the test vector that described test interface applies, and this test vector is transferred to each NVM with NVM, testing control module;
Read control module, be connected with NVM, testing control module, after being used to accept read command vector that described test interface applies, sense data from each NVM, and after these data are carried out logical process, export the test interface place to and test machine is made comparisons with the form of one group of data, do not match if find, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
A kind of above-mentioned SOC realizes the method for parallel test judgement, comprises the steps:
(1) on the test interface of chip, applies test vector, described wiping/write control module again this test vector to be transferred to each NVM to wiping/write control module;
(2) testing control module is judged the end signal of each NVM, wipes/write test to determine whether that all NVM finish;
(3) testing control module exports the end signal through logic decision to test interface, and by this next step test of test interface control carrying out;
(4) apply the read command vector to reading control module on test interface, this is read after control module accepts the read command vector, sense data from each NVM;
(5) testing control module is judged the end signal of each NVM, finishes read test to determine whether all NVM;
(6) read after control module carries out logical process to the data of reading among each NVM, export the test interface place to and test machine is made comparisons with the form of one group of data, if find not match, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
SOC and its implementation of carrying out parallel test judgement of the present invention can be saved the substantive test time, and test can reduce testing cost greatly for scale of mass production.Because test duration of NVM mainly spends on wipings/write operation, so be example with the SOC of embedded 3 NVM, the test duration of the present invention almost can be reduced to original 1/3.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the existing synoptic diagram that the SOC realization timesharing that comprises polylith NVM is surveyed together;
Fig. 2 is the circuit theory synoptic diagram that carries out the SOC of parallel test judgement of the present invention.
Embodiment
When among the SOC during embedded polylith NVM, be to save the test duration, the present invention design following three module (see figure 2)s in SOC, with realization to polylith NVM parallel test judgement:
1. testing control module
With test interface, NVM, wiping/write control module with read control module and be connected, be used for the end signal of parallel each NVM of judgement, and output to the test interface place after doing certain logical process, to determine whether entire circuit can enter next step test.Described testing control module also can directly be controlled according to end signal and wipe/write control module or read control module.
2. wipe/write control module
Because the method for testing to each piece NVM of the same type is identical with flow process in test process, for wiping and write action, they use identical test vector excitation.Therefore by wiping/write control module, make chip enter the wiping of polylith NVM/write operation simultaneously, polylith NVM interface is connected on the test pin of chip simultaneously like this.In test, wiping/write control module is connected with NVM, testing control module, be used for the test vector that the acceptance test interface applies, and this test vector is transferred to polylith NVM simultaneously, described polylith NVM is transferred to end signal the testing control module judge again, wipes/write test to determine whether that all NVM finish.
3. read control module
Because the method for testing to each piece NVM of the same type is identical with flow process in test process, for reading action, they also use identical test vector excitation.Therefore by reading control module, make chip finish polylith NVM timesharing and read the operation of judging simultaneously.In test, described control module and the NVM of reading, testing control module is connected, after being used to accept read command vector that test interface applies, sense data is read in the control module to this from each NVM, described each NVM is transferred to end signal the testing control module judge again, to determine whether that all NVM finish read test, follow described reading after control module carries out logical process to the data of reading among each NVM, export the test interface place to and test machine is made comparisons with the form of one group of data, do not match if find, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
SOC of the present invention realizes the method for parallel test judgement, and is as described below:
In test, when wiping/writing the test of project, the wiping of selection polylith NVM/write operation simultaneously applies test vector to wiping/write control module on the test interface of chip, judge end signal by testing control module then, wipe/write test event to determine whether that all NVM finish.Testing control module exports the end signal through logic decision to test interface then, and by this next step test of test interface control carrying out.
When needs carry out read test to NVM, on test interface, apply the read command vector to reading control module, in the lump the data on the appropriate address position among the polylith NVM are read into then and read in the control module, walk abreast by testing control module and to judge end signal, to determine whether that all NVM finish one and read action, again by reading after control module carries out logical process to the data of reading among each NVM, export the test interface place to and test machine is made comparisons with the form of one group of data, do not match if find, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
Claims (3)
1. a SOC who carries out parallel test judgement comprises test interface and at least two NVM, it is characterized in that, also comprises:
Testing control module, with test interface, NVM, wiping/write control module with read control module and be connected, be used to receive the end signal of each NVM, and this end signal is exported to test interface after logic decision, or wipe/write control module or read control module according to this end signal control;
Wipe/write control module, be connected, be used to receive the test vector that described test interface applies, and this test vector is transferred to each NVM with NVM, testing control module;
Read control module, be connected with NVM, testing control module, after being used to accept read command vector that described test interface applies, sense data from each NVM, and after these data are carried out logical process, export the test interface place to and test machine is made comparisons with the form of one group of data, do not match if find, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
2. SOC as claimed in claim 1 is characterized in that, described wiping/write control module the test vector that receives is transferred to each NVM simultaneously.
3. the method for the described SOC realization of claim 1 parallel test judgement is characterized in that, comprises the steps:
(1) on the test interface of chip, applies test vector, described wiping/write control module again this test vector to be transferred to each NVM to wiping/write control module;
(2) testing control module is judged the end signal of each NVM, wipes/write test to determine whether that all NVM finish;
(3) testing control module exports the end signal through logic decision to test interface, and by this next step test of test interface control carrying out;
(4) apply the read command vector to reading control module on test interface, this is read after control module accepts the read command vector, sense data from each NVM;
(5) testing control module is judged the end signal of each NVM, finishes read test to determine whether all NVM;
(6) read after control module carries out logical process to the data of reading among each NVM, export the test interface place to and test machine is made comparisons with the form of one group of data, if find not match, illustrate that having one among a plurality of NVM at least exists defective, test promptly changes the test result treatment state over to.
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| CNA2006101192841A CN101196556A (en) | 2006-12-07 | 2006-12-07 | SOC for parallel test judgement and its implementing method |
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| CNA2006101192841A CN101196556A (en) | 2006-12-07 | 2006-12-07 | SOC for parallel test judgement and its implementing method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262207A (en) * | 2010-05-27 | 2011-11-30 | 上海华虹Nec电子有限公司 | Method for rapidly judging test result of SOC (System-On-a-Chip) chip |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN102592679A (en) * | 2011-01-13 | 2012-07-18 | 北京兆易创新科技有限公司 | Flash memory chip and testing method thereof |
| CN105446843A (en) * | 2014-05-30 | 2016-03-30 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| CN106291099A (en) * | 2016-07-29 | 2017-01-04 | 上海华岭集成电路技术股份有限公司 | Chip port frequency test method |
| CN110376503A (en) * | 2019-06-27 | 2019-10-25 | 福州数据技术研究院有限公司 | A kind of AI accelerates chip performance test method and its device |
| CN111413612A (en) * | 2020-03-25 | 2020-07-14 | 北京中电华大电子设计有限责任公司 | Test structure for improving chip test efficiency |
-
2006
- 2006-12-07 CN CNA2006101192841A patent/CN101196556A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262207A (en) * | 2010-05-27 | 2011-11-30 | 上海华虹Nec电子有限公司 | Method for rapidly judging test result of SOC (System-On-a-Chip) chip |
| CN102592679A (en) * | 2011-01-13 | 2012-07-18 | 北京兆易创新科技有限公司 | Flash memory chip and testing method thereof |
| CN102592679B (en) * | 2011-01-13 | 2015-01-07 | 北京兆易创新科技股份有限公司 | Flash memory chip and testing method thereof |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN105446843A (en) * | 2014-05-30 | 2016-03-30 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| CN105446843B (en) * | 2014-05-30 | 2019-02-15 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| CN106291099A (en) * | 2016-07-29 | 2017-01-04 | 上海华岭集成电路技术股份有限公司 | Chip port frequency test method |
| CN106291099B (en) * | 2016-07-29 | 2019-10-25 | 上海华岭集成电路技术股份有限公司 | Chip port frequency test method |
| CN110376503A (en) * | 2019-06-27 | 2019-10-25 | 福州数据技术研究院有限公司 | A kind of AI accelerates chip performance test method and its device |
| CN110376503B (en) * | 2019-06-27 | 2021-07-27 | 福州数据技术研究院有限公司 | AI acceleration chip performance test method and device |
| CN111413612A (en) * | 2020-03-25 | 2020-07-14 | 北京中电华大电子设计有限责任公司 | Test structure for improving chip test efficiency |
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Open date: 20080611 |