CN106291099B - Chip port frequency test method - Google Patents
Chip port frequency test method Download PDFInfo
- Publication number
- CN106291099B CN106291099B CN201610615663.3A CN201610615663A CN106291099B CN 106291099 B CN106291099 B CN 106291099B CN 201610615663 A CN201610615663 A CN 201610615663A CN 106291099 B CN106291099 B CN 106291099B
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- Prior art keywords
- test
- frequency
- chip port
- chip
- vector
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Abstract
The present invention provides a kind of chip port frequency test methods, comprising: the frequency for defining the test vector of an output pin of the chip makes the frequency meet the test frequency of automatic testing equipment (ATE)；Run other test vectors；And the test vector of the operation output pin, to carry out the chip port frequency test.The present invention in order to realize test vector frequency beyond institute can provide highest frequency under frequency test mode using ATE in the case where, by being split to test vector, and concurrent test technology realizes the test of chip port output frequency, solving in existing scheme one needs upgrading hardware, the problem of ancillary cost, it solves to need other plug-in test equipments in existing scheme two, the testing time is long, and the problem that hardware connection is inconvenient.The present invention realizes the test of chip port upper frequency using concurrent test technology under conditions of ATE hardware is constant, improves higher chip port output frequency test convenience and testing efficiency.
Description
Technical field
The present invention relates to chip testing field more particularly to a kind of chip port frequency test methods.
Background technique
In chip testing, port frequency test is very important part.It is automatic to test when carrying out port frequency test
Device (ATE) applies input signal to the input port of chip, and circuit is allowed to enter corresponding working state, then the tested output of crawl
Response signal on port, ATE sample the output signal, in a period of time t that calculation procedure limits, output signal
Rising edge number n, the output frequency for obtaining the tested port is f=n/t, by f compared with the desired output frequency values of port, if
It is correct to be unanimously judged as the chip port output frequency, if inconsistent chip port output frequency of being judged as is abnormal.
In the test of existing chip port output frequency, a test vector is generallyd use to complete the test item, is used to
It the input port of setting state and is all placed in this test vector for the output port tested, the following institute of test vector example
Show.The frequency of the test vector generally can not be more than the maximum frequency f that the ATE allows under frequency test mode, such as use ATE
When test frequency, which cannot be less than t=to execute the time cycle tset of every row vector in following test vector
1/f。
When test vector frequency is beyond available highest frequency under used ATE frequency test mode, usually just like
Lower way:
The prior art one: upgrading hardware；
The ATE of greater degree is replaced, but this is often expensive, needs to pay additional very high cost；
The prior art two: directly carrying out chip output mouth frequency test without using ATE, while running test vector,
By the plug-in oscillograph of ATE, output port frequency test is carried out；ATE and the communication of plug-in oscillograph can lengthen the testing time, and outer
It is also inconvenient in hardware connection to hang oscillograph test.
In conclusion with the rapid development of integrated circuit, so that its port frequency is higher and higher, using the prior art,
Or testing cost is improved, or can not expeditiously carry out scale of mass production test.
Summary of the invention
Of the existing technology in order to solve the problems, such as, the present invention provides a kind of chip port frequency test method, comprising:
The frequency for defining the test vector of an output pin of the chip, makes the frequency meet the survey of automatic testing equipment
Try frequency；
Run other test vectors；And
The test vector of the output pin is run, to carry out the chip port frequency test.
Optionally, the test frequency of the automatic testing equipment is lower than the frequency of other test vectors.
Optionally, the test vector of the output pin and other test vectors are in the different portions of the automatic testing equipment
Partite transport row.
Optionally, the method for carrying out the chip port frequency test is to obtain the output of output pin in a period of time t
The rising edge number n of signal, the output frequency that the tested port is calculated is f=n/t.
Optionally, after the completion of the chip port frequency test, the test vector of the output pin out of service,
He continues to run test vector.
Optionally, other described test vectors are clock and setting pin vector.
Optionally, the test vector of the output pin is clock and setting pin vector.
Optionally, the test vector and other test vectors of the output pin are run by different test items.
Optionally, the test frequency of the automatic testing equipment is frequency of the automatic testing equipment under frequency test mode
Rate.
Optionally, the frequency of the automatic testing equipment in test mode is lower than its test supported in the normal mode
The highest frequency of vector.
The present invention provides a kind of chip port frequency test methods, comprising: defines an output pin of the chip
The frequency of test vector makes the frequency meet the test frequency of automatic testing equipment (ATE)；Run other test vectors；And
The test vector of the output pin is run, to carry out the chip port frequency test.The present invention in order to realize test to
In the case that amount frequency can provide highest frequency under frequency test mode using ATE beyond institute, by being carried out to test vector
Fractionation and concurrent test technology realize the test of chip port output frequency, and solving in existing scheme one needs upgrading hardware,
The problem of ancillary cost, solves to need other plug-in test equipments in existing scheme two, and the testing time is long, and hardware connection is inconvenient
The problem of.The present invention realizes the survey of chip port upper frequency using concurrent test technology under conditions of ATE hardware is constant
Examination improves higher chip port output frequency test convenience and testing efficiency.
Detailed description of the invention
Fig. 1 is the flow chart of chip port frequency test method described in one embodiment of the invention；
Fig. 2 is the specific implementation schematic diagram of chip port frequency test method described in one embodiment of the invention.
Specific embodiment
When being tested for chip port output frequency, it usually needs first run test vector, chip is made to enter test institute
The working condition needed grabs the signal and is analyzed, obtained in a period of time t at this point, there is rate-adaptive pacemaker in tested port, exports
The rising edge number n of signal, the output frequency that the tested port is calculated is f=n/t.
When the frequency of test vector exceeds automatic testing equipment (ATE) available highest frequency under frequency test mode
When fc, ATE does not support the test port output frequency directly in the same test item.As existing automatic testing equipment itself props up
Holding test vector highest frequency is fo=400MHz, but only supports that test vector highest frequency is fc=under frequency test mode
200MHz, it is now desired to the port output frequency that desired value is 350MHz is tested, using the frequency test mould of automatic testing equipment
Formula can not be directly realized by.
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A kind of chip port frequency test method of the invention, as shown in Figure 1, comprising:
The frequency for defining the test vector of an output pin of the chip, makes the frequency meet automatic testing equipment
(ATE) test frequency；
Run other test vectors；And
The test vector of the output pin is run, to carry out the chip port frequency test.
In general, the test frequency of the automatic testing equipment is lower than the frequency of other test vectors.Above-mentioned automatic survey
The test frequency that trial assembly is set is the frequency of automatic testing equipment (ATE) in test mode, which supports to survey lower than it
Try the highest frequency of vector.
In the present embodiment, the test vector for carrying out port frequency test can be directly divided into the test vector of output pin
It is two parts in the present embodiment with other test vectors.Wherein, former test vector " pat_0 " as follows, wherein executing every
The time cycle of row vector is tset=1/350MHz；
Pat_0:
It is divided into the test vector of other test vectors and output pin.The test vector of output pin is " pat_fcp ",
Other test vectors are clock and setting pin vector " pat_clk_set ", and difference is as follows:
Pat_clk_set:
The time cycle of wherein each row vector is tset1=1/350MHz；
Pat_fcp:
The time cycle of wherein each row vector is tset2=1/50MHz；
In addition, the different piece of the test vector of the output pin and other test vectors in the automatic testing equipment
Operation, specifically, must to be distributed in automatic testing equipment different for channel resource used in two test vectors of partition
On Engine.
Then setting testing process is as follows, first passes through test item Test_setup come the test vector " pat_ that wins the race
Clk_set " makes chip be tested port output to measured frequency, and the vector is being run always from the background, and clock will not stop, and be tested end
Mouth has always rate-adaptive pacemaker, and second test vector " pat_fcp " is then run by test item Test_Meas, is tested herein
Chip port output frequency is measured according to automatic testing equipment frequency test method in.
It is as follows to test source code:
Publ ic Funct ion BackGround_test_setup()As Long
Dim test_setup_PAT As String (defines setting test vector)
Test_setup_PAT=" patterns pat_clk_set.PAT "
If (TheExec.Flow.IsTestBPStart=True) Then
If (opcode is " TestBPStart " in test flow, is arranged by test vector " pat_clk_set "
Chip enters corresponding working state, and the test vector is allowed to run always, and clock will not stop, and tested port has always frequency defeated
Out)
If (opcode is " TestBPEnd " in test flow, and " pat_clk_set " test vector is stopped, and is tested
Terminate)
A kind of chip port frequency test method of the present embodiment is specifically as shown in Figure 2, comprising:
1. chip is powered on, apply defined voltage to the power supply of chip；
2. setting chip enters corresponding working state by running test vector " pat_clk_set ", chip is tested port and opens
There is rate-adaptive pacemaker in beginning, and setting vector " pat_clk_set " is run on backstage always；
3. carrying out chip port frequency test by test item " Test_Meas "；
4. judgement tests whether to complete, continue to test if not completing, if completed, stops test vector " pat_
clk_set"；
5. test terminates.
The technical scheme is that in order to realize in test vector frequency beyond used ATE under frequency test mode
In the case where can provide highest frequency, by test vector is split and concurrent test technology realize chip port it is defeated
The problem of test of frequency out, solving needs upgrading hardware in existing scheme one, ancillary cost solves to need in existing scheme two outer
Other test equipments are hung, the testing time is long, and the problem that hardware connection is inconvenient.The present invention under conditions of ATE hardware is constant,
It is convenient to improve higher chip port output frequency test for the test that chip port upper frequency is realized using concurrent test technology
Property and testing efficiency.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the invention is also intended to include including these modification and variations.
Claims (8)
1. a kind of chip port frequency test method characterized by comprising
The expectation test frequency of chip is defined, under the expectation test frequency, the chip port has an output frequency；
The frequency for defining the test vector of an output pin of the chip makes the frequency meet the test frequency of automatic testing equipment
Rate, the test frequency of the automatic testing equipment are frequency of the automatic testing equipment under frequency test mode；
Other test vectors are run, the chip port is made to export the output frequency；And
The test vector of the output pin is run, to carry out the chip port frequency test.
2. chip port frequency test method as described in claim 1, which is characterized in that the test of the automatic testing equipment
Frequency is lower than the frequency of other test vectors.
3. chip port frequency test method as described in claim 1, which is characterized in that the test vector of the output pin
Different piece with other test vectors in the automatic testing equipment is run.
4. chip port frequency test method as described in claim 1, which is characterized in that carry out the chip port frequency and survey
The method of examination is to obtain the rising edge number n of the output signal of output pin in a period of time t, and the tested port is calculated
Output frequency be f=n/t.
5. chip port frequency test method as described in claim 1, which is characterized in that in the chip port frequency test
After the completion, the test vector of the output pin out of service, other test vectors continue to run.
6. chip port frequency test method as described in claim 1, which is characterized in that other described test vectors are clock
With setting pin vector.
7. chip port frequency test method as described in claim 1, which is characterized in that run institute by different test items
State the test vector and other test vectors of output pin.
8. chip port frequency test method as described in claim 1, which is characterized in that the automatic testing equipment is in frequency
Frequency under test pattern is lower than the highest frequency of its test vector supported in the normal mode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610615663.3A CN106291099B (en) | 2016-07-29 | 2016-07-29 | Chip port frequency test method |
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|---|---|---|---|
| CN201610615663.3A CN106291099B (en) | 2016-07-29 | 2016-07-29 | Chip port frequency test method |
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| CN106291099B true CN106291099B (en) | 2019-10-25 |
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| CN109143026A (en) * | 2018-07-12 | 2019-01-04 | 上海航天信息研究所 | A kind of digital test method and system |
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