CN107301880B - Built-in self-test structure of on-chip embedded Flash - Google Patents
Built-in self-test structure of on-chip embedded Flash Download PDFInfo
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- CN107301880B CN107301880B CN201710454746.3A CN201710454746A CN107301880B CN 107301880 B CN107301880 B CN 107301880B CN 201710454746 A CN201710454746 A CN 201710454746A CN 107301880 B CN107301880 B CN 107301880B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Abstract
The invention provides a built-in self-test structure of an on-chip embedded Flash, which comprises a user-defined control module, an FBIST controller, an ERASE module and a BYPASS module, wherein when the FBIST controller is enabled, the FBIST controller initiates operation, realizes sequence operation and erasure switching of address and read-write of the FBIST controller according to the mutual cooperation of an internal controller state machine, the user-defined control module and the ERASE module, compares a read result with a test result of an on-chip comparator, outputs a result characterization signal, and finishes the jump of a test identifier when the test is finished; the internal access and test result comparison of the FLASH are realized, only one test starting signal and a controller clock signal are needed outside, the test result is represented by the test completion flag bit and the test failure flag bit after the test is finished, the failure address, the algorithm execution state, the read-write state and the output data information of the FLASH can be mastered, so that a basis is provided for further fault location, and the built-in self-test of the chip-level or system-level embedded FLASH is realized.
Description
[ technical field ] A method for producing a semiconductor device
The invention belongs to the technical field of testability design of embedded Flash of super-large-scale integrated circuits such as SoC (system on chip), DSP (digital signal processor) and the like, and relates to a built-in self-test structure of on-chip embedded Flash.
[ background of the invention ]
With the integrated circuit manufacturing process stepping into the ultra-deep submicron stage, the proportion of the embedded memory occupied in the SOC system-on-chip is larger and larger, and the area of the embedded memory on the chip occupies more than 95% of the area of the complex SOC chip by 2016.
FLASH, as a non-volatile memory based on floating gate technology, has its own unique advantages: non-volatile, low cost and high density, and can be electrically erased and repeatedly programmed without special external high voltage. Based on the above characteristics, FLASH is increasingly applied to embedded systems. However, as the feature size of semiconductor devices is continuously reduced, embedded memories including FLASH memories have more and more defect types. How to carry out simple and effective high-coverage test on the test result is a key problem to be solved urgently in the testability design of the very large scale integrated circuit.
At present, the conventional functional test method for testing FLASH mainly has the defects of low test coverage, long test time, difficult test generation, low test efficiency and the like. However, depending on the EDA tool, the built-in self-test technology for the on-chip embedded memory has become the mainstream test technology for the memory, but in view of the characteristics of reading, writing, erasing, programming and the like of Flash, the EDA tool cannot effectively support the built-in self-test technology for Flash.
Currently, there are some achievements on the research of built-in self test of FLASH, "built-in self test design of SOC embedded FLASH memory" (microelectronic and computer 2005, volume 22, phase 4), which is a hardware built-in self test scheme for memory introduced in this document, and it uses a special ROM memory to store the test algorithm and test process information required by FBIST controller, the memory BIST wrapper adopts a cut IEEE1500 structure, and all test commands and results are input and output serially through WSI/WSO. The structure has high hardware cost, the execution of the test instruction needs to depend on an IEEE1500 structure, and the test control is complex; especially for embedded multi-group FLASH memories, the method needs larger hardware overhead, and the method connects the system bus with the FBIST controller through the bus interface module, depends on the functions of the processor and the support of software to a certain extent, and still does not get rid of the scope of functional test.
[ summary of the invention ]
The built-in self-test structure of the on-chip embedded Flash is independent in structure and simple in test control, and the built-in self-test of the chip-level or system-level embedded Flash is completely realized.
In order to achieve the purpose, the invention adopts the following technical scheme:
a built-in self-test structure of an on-chip embedded Flash comprises a user-defined control module, an FBIST controller, an ERASE module and a BYPASS module;
the user-defined control module is used for controlling and scheduling states of erasing operation and reading and writing operation;
the FBIST controller is an algorithm implementation circuit of read-write operation, read data of FLASH is automatically compared with an expected value through an internal comparator of the FBIST controller, the execution of the read-write operation of the FBIST controller is controlled by a user-defined control module, and the execution of the algorithm and the execution of the erasing operation are realized by the control of a test flow;
the ERASE module is in charge of controlling the erasing operation of the FLASH under the scheduling of the user-defined control module;
the BYPASS module is used for realizing a FLASH BYPASS function in a circuit full-scan test mode;
when the FBIST controller is enabled, the FBIST controller initiates operation, sequence operation and erasure switching of address and read-write of the FBIST controller are achieved according to the mutual matching of the internal controller state machine, the user-defined control module and the ERASE module, the read result is compared with the test result of the on-chip comparator, a result characterization signal is output, and when the test is finished, the test finishes identification jumping.
Furthermore, if the test fails in the test process, the failure data is collected by the diagnosis module.
Furthermore, the diagnosis module is composed of a diagnosis control state machine and a diagnosis scanning state machine and a holding control module, the diagnosis control state machine realizes the control of the whole diagnosis process, and the diagnosis scanning state machine is used for controlling the serial output of the diagnosis data.
Further, the diagnosis module and the FBIST controller realize the whole self-test and diagnosis work in a signal handshake mode.
Further, when the expected value is not matched with the actual output, the test failure signal of the FBIST controller jumps and interacts with the diagnosis state machine through the failure signal, the internal diagnosis module is enabled to enter a diagnosis mode, the maintenance and recovery of the algorithm of the BIST circuit in the failure diagnosis stage are controlled through the maintenance control module, the diagnosis module collects related data in failure in parallel through the monitor port and outputs the information to the outside of the chip in series through the dout port, the FBIST controller starts again after the failure information is shifted, and the subsequent test algorithm operation is continued.
The built-in self-test structure of the on-chip embedded Flash comprises a self-defined control module, an FBIST controller, an ERASE module and a BYPASS module, realizes internal access and test result comparison of the FLASH, only needs one test starting signal and a controller clock signal outside, represents a test result through a test completion flag bit and a test failure flag bit after the test is finished, and can master failure addresses, algorithm execution states, read-write states and output data information of the FLASH through analysis of a diagnosis serial output result, thereby providing a basis for further fault location and realizing built-in self test of the chip-level or system-level embedded FLASH.
Compared with the prior art, the invention also has the following beneficial effects:
(1) the invention has simple test control, and can realize the sequence operations of reading, writing, erasing and the like of FLASH through the internal state machine operation and algorithm control by externally triggering only one test starting signal, thereby further completing the on-chip self-test.
(2) The invention has independent structure, avoids dependence on a function processor and software, and can directly represent the correctness of the Flash IP.
(3) The test algorithm generation, test execution and test comparison of the invention are all completed by the internal self-test circuit, thereby greatly reducing the difficulty of FLASH test.
(4) The built-in self-test structure of the FLASH can be matched with various mainstream FLASH test algorithms, and hardware algorithm generation can be realized by depending on a self-defined algorithm model, so that the fault coverage aiming at the FLASH is effectively improved.
[ description of the drawings ]
FIG. 1 is a schematic diagram of an embedded FLASH self-test structure
FIG. 2 is a schematic diagram of an embedded FLASH self-test diagnostic module
FIG. 3 is a schematic diagram of an application example of an on-chip embedded FBIST structure
[ detailed description ] embodiments
The invention is described in further detail below with reference to the figures and the examples, but without limiting the invention.
The invention realizes built-in self test aiming at FLASH IP by constructing an FBIST controller and other control circuits of the on-chip FLASH and customizing an algorithm on the basis of referencing the design of BIST of a memory.
As shown in fig. 1, the entire self-test structure includes: a self-defined control module, an FBIST (FLASH BIST) controller, an ERASE control module, a BYPASS module and the like. The user-defined control module is used for controlling and scheduling states of erasing operation and reading and writing operation; the FBIST controller is an algorithm implementation circuit for read-write operation. The read data of FLASH is compared with the expected value automatically by the internal comparator of FBIST controller. Different from the BIST circuit of the common memory, the execution of the read-write operation is controlled by the user-defined control module, and the receiving of the control signal, the stop or the execution of the wake-up algorithm and the execution of the erasing operation are realized through the control of the test flow; the ERASE module is in charge of controlling the erasing operation of the FLASH under the scheduling of the self-defined control module. The BYPASS module is used for realizing a FLASH BYPASS function in a circuit full scan test mode so as to ensure the scan test coverage of the FBIST controller.
And when the FBIST controller is enabled, the FBIST controller initiates operation, realizes sequence operation and erasure switching of address and read-write according to the mutual matching of the internal controller state machine, the user-defined control module and the erasure module, compares the read result with the test result of the on-chip comparator, outputs a result characterization signal, and finishes the test and marks the jump. If there is a failure in the test, the diagnostic module can be relied upon to collect failure data.
The diagnostic module consists of two state machines, diagnostic control, diagnostic scan, and hold control modules, as shown in FIG. 2. The diagnosis control state machine realizes the control of the whole diagnosis process; the diagnostic scan state machine is used to control the serial output of diagnostic data. The diagnosis module and the FBIST controller realize the whole self-test and diagnosis work in a signal handshake mode. When the expected value is not matched with the actual output, the test failure signal of the FBIST controller jumps and interacts with a diagnosis state machine through a failure signal, an internal diagnosis module is enabled to enter a diagnosis mode, the maintenance and recovery of the algorithm of the FBIST controller at a failure diagnosis stage are controlled through a maintenance control module, the diagnosis module collects related data in failure in parallel through a monitor port, and the information is serially output to the outside of the chip through a dout port. And after the displacement of the information to be failed is finished, the FBIST controller is started again, and the subsequent test algorithm operation is continued.
Examples
On a certain 0.18um process super large scale SOC chip, four FLASH IPs with 128K capacity are integrated, the IP supports macro erase and page erase, the time consumption of functional test access is long, the control is complex, in order to realize the high-efficiency test of the embedded FLASH IP in the circuit, the testability design is carried out, the on-chip embedded FLASH built-in self-test structure is adopted, and the interface logic is shown in figure 3.
In the design, the parallel test technology is adopted in consideration of the scale and the test time of FLASH, the parallel test is realized on four 128K FLASH blocks under the support of the built-in self-test structure of the invention, and the test control is uniformly carried out by one FBIST controller. When the FBIST circuit is enabled, the controller generates test data, addresses and control signals according to the algorithm sequence under the control of the state machine operation and the custom module, and realizes the receiving of the control signals, the stopping or awakening of algorithm execution and the execution of erasing operation through the control of the test flow; the switching and operation of two erasing modes (macro erasing and page erasing) of FLASH are carried out under the control of ERASE module. The automatic comparison of FLASH read data is realized through an FBIST internal comparator; when the test fails, the diagnostic control circuit serially outputs a failure address, data and a read-write state from the port according to the execution state of the controller algorithm.
In order to realize the high coverage test of the FLASH, modeling is designed according to the internal working time sequence of the FLASH, and fault models such as write gate interference, erase gate failure, write drain interference, erase drain interference, read interference, overerasion failure, bridging failure and the like are covered by adopting Cocktail-March and March-FT algorithms which are approved in the industry and have high coverage for the FLASH test. A Cocktail-march algorithm is adopted for a FLASH main storage space, and the algorithm steps are as follows:
{e}↑R1,↑W0R0,↑R0,{e}↓R1,↓W0R0,↓R0
{e}↑W(1100)R(1100),{e}↓W(1100)R(1100)
{e}↑W(0011)R(0011),{e}↓W(0011)R(0011)
{e}↑W(1010)R(1010),{e}↓W(1010)R(1010)
{e}↑W(0101)R(0101),{e}↓W(0101)R(0101)
the Cocktail-MARCH algorithm adopts the data background of the classic MARCH algorithm similar to the common memory, and adds a corresponding erasing process ({ e } is an erasing operation) according to the operation requirement of the FLASH, thereby realizing the detection of various faults of the FLASH.
The erasing operation of the FLASH is divided into macro erasing { me } and page erasing { pe }, and in order to detect the page erasing interference fault, an improved March-FT-page algorithm is used, and the steps are as follows:
{me}W0
↑PR0,{pe},↑PR1PW0PR0
↓PR0,{pe},↓PR1PW0PR0
R0
and writing 0 to the full address after the full erase, then respectively executing read operation and erase and read-write read operation of the current page according to the page in ascending order and descending order, and finally performing the full address read 0 operation so as to detect the page erase interference type fault.
The FLASH used in the circuit also comprises a 256-byte information storage array, when the built-in self-test design is carried out, a special information storage array gating signal is added in a test sequence, and after an information module is selected, the test of the part of the storage space is realized by applying an algorithm.
In order to simplify the control logic, the built-in self-test structure of the FLASH and the built-in self-test of other memories are controlled and started through an external JTAG port, and result observation can be carried out through the JTAG, so that the built-in self-test of the FLASH and the testability design of the whole circuit are highly fused. Based on the structure, the test of the FlashIP is successfully realized on the V93K test platform, the test time is effectively shortened, and the test efficiency is improved.
While the invention has been described in further detail with reference to specific preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (3)
1. A built-in self-test structure of an on-chip embedded Flash is characterized in that: the system comprises a user-defined control module, an FBIST controller, an ERASE module and a BYPASS module;
the user-defined control module is used for controlling and scheduling states of erasing operation and reading and writing operation;
the FBIST controller is an algorithm implementation circuit of read-write operation, read data of FLASH is automatically compared with an expected value through an internal comparator of the FBIST controller, the execution of the read-write operation of the FBIST controller is controlled by a user-defined control module, and the execution of the algorithm and the execution of the erasing operation are realized by the control of a test flow;
the ERASE module is in charge of controlling the erasing operation of the FLASH under the scheduling of the user-defined control module;
the BYPASS module is used for realizing a FLASH BYPASS function in a circuit full-scan test mode;
when the FBIST controller is enabled, the FBIST controller initiates operation, sequence operation and erasure switching of address and read-write of the FBIST controller are realized according to the mutual matching of an internal controller state machine, a user-defined control module and an ERASE module, a read result is compared with a test result of an on-chip comparator, a result characterization signal is output, and when the test is finished, the test finishes identification jump;
if the test is invalid in the test process, the failure data is collected by the diagnosis module;
the diagnosis module consists of a diagnosis control state machine and a diagnosis scanning state machine and a holding control module, the diagnosis control state machine realizes the control of the whole diagnosis process, and the diagnosis scanning state machine is used for controlling the serial output of diagnosis data.
2. The built-in self-test structure of an on-chip embedded Flash of claim 1, wherein: the diagnosis module and the FBIST controller realize the whole self-test and diagnosis work in a signal handshake mode.
3. The built-in self-test structure of an on-chip embedded Flash of claim 1, wherein: when the expected value is not matched with the actual output, the test failure signal of the FBIST controller jumps, interacts with the diagnosis control state machine and the diagnosis scanning state machine through the failure signal, enables the diagnosis module to enter a diagnosis mode, controls the BIST circuit to maintain and recover the algorithm in the failure diagnosis stage through the maintenance control module, parallelly collects the related data during failure through the monitor port by the diagnosis module, serially outputs the related data during failure to the outside of the chip through the dout port, finishes the shift of the information to be failed, restarts the FBIST controller, and continues the subsequent test algorithm operation.
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