CN106874577A - A kind of memory compiler - Google Patents
A kind of memory compiler Download PDFInfo
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- CN106874577A CN106874577A CN201710049229.8A CN201710049229A CN106874577A CN 106874577 A CN106874577 A CN 106874577A CN 201710049229 A CN201710049229 A CN 201710049229A CN 106874577 A CN106874577 A CN 106874577A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
- G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The present invention relates to memory technology field, more particularly to a kind of memory compiler, the design data generated using the memory compiler is not only included the memory macro unit that current memory compiler is generated, also at least includes a microcontroller；The microcontroller can not only realize traditional reading and write operation to memory, the selftest to memory, self-optimization can also be realized and used as optional microprocessor core in an on-chip system, so as to improve the reliability and performance of memory.
Description
Technical field
The present invention relates to memory technology field, more particularly to a kind of memory compiler.
Background technology
Memory (Memory) is for protecting stored memory device in modern information technologies.All believe in computer
Breath, including the initial data, computer program, middle operation result and the final operation result that are input into all are preserved in memory.
The position that it is specified according to Memory Controller is stored in and taking-up information.There is memory, computer just has memory function, ability
Ensure normal work.Since being come out from First computer in the world, the memory of computer also updates in constantly development, from
Hg delay line at the beginning, tape, magnetic drum, magnetic core, semiconductor memory till now, disk, CD, nanometer storing etc.；From
The 10um processing procedures of 1971, to the 0.18um processing procedures of 1999, then 14nm processing procedures by now, technological development is also very fast.
In-line memory as most popular one kind in embedded module, because of the characteristic of its own function, and with comparing group under homalographic
Combinational logic block advantage low in energy consumption, is increasingly favored in the system-on-chip designs of deep-submicron by designer.Its application
Popularity is suitable with standard block and input-output unit.The generation of standard block and input-output unit is, it is necessary to arrange
All regular sizes are lifted, all modules are generalized into cell library, the solution of memory then can not be by enumerating all specifications
To realize.No matter slave module quantity, in data volume, or human resources be all unpractical, be at this moment accomplished by an instrument energy
Automatically generating for all size memory is enough realized, here it is memory compiler.
Flow currently with memory compiler generation reservoir designs data is as shown in Figure 1:1) client proposes first
Detailed design requirement, specifically includes capacity, area and power consumption of memory etc.；2) memory company/engineer obtains visitor
The design requirement at family, these demands are input in memory compiler, and memory compiler is started working；3) after a period of time
The design data of the memory that the generation of memory compiler is met customer need.The design data for obtaining generally memory macro list
Unit, its data/address bus, controlling bus and address bus for mainly including certain bit wide, data/address bus is used to transmit data letter
Breath, such as when write operation is performed, transmission will write the data of memory, and when read operation is performed, transmission is read from memory
The data for going out；Controlling bus are used to transmit control command, such as write operation order and read operation order；Address bus is used to transmit
The address information of memory.
Memory block compiler can also produce a state machine (Finite State while memory macro unit is generated
Machine, FSM) for the operation of control memory.State machine is made up of status register and combinational logic circuit, Neng Gougen
State transfer is carried out according to state set in advance according to control signal, is to coordinate coherent signal action, complete the control of specific operation
Center processed.
However, with the development of semiconductor technology, particularly deep-submicron (40nm and following) is reached in semiconductor technology
After, the density of memory cells of one side in-line memory will become very big (such as storage density is more than 16Mb), another
The fluctuation of aspect technique can also become big.These situations will all cause state machine it is difficult to precise control in-line memory it is every
One BIT data so that the reliability and performance of memory will be determined by the worst bit of performance (tail bit).Finally, this will
The yields of memory is caused to decline, so that extreme influence economic benefit, this is that those skilled in the art are hated the sight of.
The content of the invention
For above-mentioned problem, the invention discloses a kind of memory compiler, the memory compiler generation
Memory design data include memory macro unit and microcontroller (Micro controller Unit, MCU)；
The microcontroller is for controlling the memory read, write, selftest and self-optimization are operated.
Above-mentioned memory compiler, wherein, the memory macro unit includes memory plate, the memory plate bag
Include：
Storage array, for data storage；
Memory peripheral hardware, is connected with the storage array, for being read to the storage array, write operation.
Above-mentioned memory compiler, wherein, the memory of the memory compiler generation at least includes：
Controlling bus, for transmission of control signals；
Data/address bus, for transmitting data；
Address bus, for transmitting address；
Program entry bus, for recording program；
Bus, the expanding function for realizing the memory are expanded in outside.
Above-mentioned memory compiler, wherein, the controlling bus include：
Write-in enables bus, for transmitting write enable signal；
Read and enable bus, read to enable signal for transmitting.
Above-mentioned memory compiler, wherein, the design data of the memory of the memory compiler generation also includes
Crystal oscillator and the first memory space and/or the second memory space.
Above-mentioned memory compiler, wherein, first memory space is nonvolatile memory.
Above-mentioned memory compiler, wherein, write operation when institute is carried out to the memory using the microcontroller
The module of use includes the memory macro unit, the microcontroller, the crystal oscillator and first memory space；
The bus used when carrying out write operation to the memory using the microcontroller writes enable described in including
Bus, the address bus and the data/address bus.
Above-mentioned memory compiler, wherein, said write operation is carried out to the memory using the microcontroller
The step of include：
The write enable signal for writing enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, the ground of data to be written in first memory space is read
Location, and the data to be written position to be stored in storage array is determined by row, column decoder；
The data to be written are write the position to be stored by memory peripheral hardware described in the microprocessor control.
Above-mentioned memory compiler, wherein, read operation when institute is carried out to the memory using the microcontroller
The module of use includes the memory macro unit, the microcontroller and the crystal oscillator；
The bus used when carrying out read operation to the memory using the microcontroller includes that the reading is enabled
Bus, the address bus and the data/address bus.
Above-mentioned memory compiler, wherein, the read operation is carried out to the memory using the microcontroller
The step of include：
The reading enable signal for reading to enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, reading is read out the address information of data, and by row, column
Decoder is read out data position to be stored in the storage array described in determining；
Memory peripheral hardware described in the microprocessor control is read out data described in reading.
Above-mentioned memory compiler, wherein, using the microcontroller memory is carried out selftest and from
I optimizes the module used during operation includes the memory macro unit, the microcontroller, the crystal oscillator and the second storage
Space；
The bus used when selftest and self-optimization operation are carried out to the memory using the microcontroller
Including described program typing bus.
Above-mentioned memory compiler, wherein, the selftest is carried out to the memory using the microcontroller
The step of being operated with self-optimization includes：
By described program typing bus by self-test, optimization program entry to second memory space；
The microcontroller performs the self testing procedure in second memory space, and selftest is carried out to memory,
And obtain test result；
The microcontroller performs the self-optimizing program in second memory space, and according to the test result to institute
Memory is stated to optimize.
Above-mentioned memory compiler, wherein, first memory space and second memory space are deposited for identical
Storage space.
Above-mentioned memory compiler, wherein, second memory space is nonvolatile memory.
Above-mentioned memory compiler, wherein, the expanding function of the memory is that the microcontroller is on-chip system
In an optional microprocessor core.
Above-mentioned memory compiler, wherein, the memory is flash memory, phase transition storage, resistance-variable storing device, magnetic storage
Device or ferroelectric memory.
Above-mentioned memory compiler, wherein, the microcontroller is the microcontroller of ARM or MIPS frameworks.
Foregoing invention has the following advantages that or beneficial effect：
The invention discloses a kind of memory compiler, the design data generated using the memory compiler is not only included
The memory macro unit of current memory compiler generation, also at least includes a microcontroller；The microcontroller can not only be realized
Traditional reading and write operation to memory, moreover it is possible to realize to the selftest of memory, self-optimization and as one
Optional microprocessor core is used in individual on-chip system (System on Chip, SOC), so as to improve the reliability of memory
And performance.
Brief description of the drawings
By reading with reference to the detailed description made to non-limiting example with figure below, the present invention and its feature, profile
Be will become more apparent with advantage.Identical mark indicates identical part in whole figures.Can not paint proportionally
Drawing, it is preferred that emphasis is show purport of the invention.
Fig. 1 is the schematic diagram of the flow using memory compiler generation reservoir designs data in conventional art；
Fig. 2 is the schematic diagram of the flow using memory compiler proposed by the present invention generation reservoir designs data；
Fig. 3 is the schematic diagram for performing part needed for write operation；
Fig. 4 is the schematic diagram of the specific steps that microcontroller performs write operation；
Fig. 5 is the schematic diagram of the timing diagram of write operation；
Fig. 6 is the schematic diagram for performing part needed for read operation；
Fig. 7 is the schematic diagram of the specific steps that microcontroller performs read operation；
Fig. 8 is the schematic diagram of the timing diagram of read operation；
Fig. 9 is the schematic diagram of part needed for selftest and self-optimization；
Figure 10 is the schematic diagram for performing selftest and self-optimization step；
Figure 11 is the schematic diagram of part needed for expanding function；
Figure 12 a~12d is write operation, read operation, self-optimizing of testing oneself, expand respectively needed for bus schematic diagram；
Figure 13 is the schematic diagram of the compiler framework of concrete application generation memory of the present invention；
Figure 14 is the schematic diagram of the flow of concrete application generation reservoir designs data of the present invention；
Figure 15 is the structural representation of the design data of concrete application generation of the present invention；
Figure 16 is the schematic diagram that concrete application of the present invention performs part needed for write operation；
Figure 17 is the schematic diagram that concrete application of the present invention performs write operation specific steps；
Figure 18 is the schematic diagram of the timing diagram that concrete application of the present invention performs write operation；
Figure 19 is the schematic diagram that concrete application of the present invention performs part needed for read operation；
Figure 20 is the schematic diagram that concrete application of the present invention performs read operation specific steps；
Figure 21 is the schematic diagram of the timing diagram that concrete application of the present invention performs read operation；
Figure 22 is that concrete application of the present invention performs selftest, the schematic diagram of part needed for self-optimization；
Figure 23 is the schematic diagram that concrete application of the present invention performs the step of selftest, self-optimization；
Figure 24 is the schematic diagram that concrete application of the present invention performs outside expanding function；
Figure 25 a~25d be concrete application of the present invention perform write operation, read operation, self-optimizing of testing oneself, expand respectively needed for it is total
The schematic diagram of line.
Specific embodiment
The invention discloses a kind of memory compiler, the design data of the memory of memory compiler generation includes
Memory macro unit and microcontroller；Wherein, microprocessor read for control memory, write, selftest and from
I optimizes operation.
In a preferred embodiment of the invention, above-mentioned memory macro unit includes memory plate, the memory plate
Including the storage array for data storage；It is connected with storage array, operation is read and write to storage array deposits for performing
Reservoir peripheral hardware.
In a preferred embodiment of the invention, the memory of above-mentioned memory compiler generation is at least included for passing
The controlling bus of defeated control signal, the data/address bus for transmitting data, the address bus for transmitting address, for typing journey
The program entry bus of sequence, the outside expansion bus for realizing expanding function.
In a preferred embodiment of the invention, above-mentioned controlling bus include that the write-in for transmitting write enable signal makes
Can bus and the reading enable bus for transmitting reading enable signal.
In a preferred embodiment of the invention, the design data of the memory of memory compiler generation also includes crystalline substance
Shake and the first memory space and/or the second memory space.
In a preferred embodiment of the invention, the first memory space is nonvolatile memory.
In a preferred embodiment of the invention, used when carrying out write operation to memory using microcontroller
Module includes memory macro unit, microcontroller, crystal oscillator and the first memory space；Memory is write using microcontroller
The bus used during operation includes writing enable bus, address bus and data/address bus.
In a preferred embodiment of the invention, bag the step of carry out write operation to memory using microcontroller
Include：
Writing the write enable signal of enable bus transfer makes crystal oscillator produce clock signal；
After microcontroller receives clock signal, read the first memory space in data to be written address, and by row,
Column decoder determines the data to be written position to be stored in storage array；
Microprocessor control memory peripheral hardware is written into data and writes position to be stored.
In a preferred embodiment of the invention, used when carrying out read operation to memory using microcontroller
Module includes memory macro unit, microcontroller and crystal oscillator；Used when carrying out read operation to memory using microcontroller
Bus include reading to enable bus, address bus and data/address bus.
In a preferred embodiment of the invention, bag the step of carry out read operation to memory using microcontroller
Include：
The reading enable signal for reading to enable bus transfer makes crystal oscillator produce clock signal；
After microcontroller receives clock signal, reading is read out the address information of data, and true by row, column decoder
Surely it is read out data position to be stored in storage array；
Microprocessor control memory peripheral hardware reads and is read out data.
In a preferred embodiment of the invention, selftest and self-optimization are carried out to memory using microcontroller
The module used during operation includes memory macro unit, microcontroller, crystal oscillator and the second memory space；Using microcontroller pair
The bus that memory used when selftest and self-optimization operation includes program entry bus.
In a preferred embodiment of the invention, selftest and self-optimization are carried out to memory using microcontroller
The step of operation, includes：
By program entry bus by self-test, optimization program entry to the second memory space；
Microcontroller performs the self testing procedure in the second memory space, selftest is carried out to memory, and obtain survey
Test result；
Microcontroller performs the self-optimizing program in the second memory space, and memory is carried out according to test result excellent
Change.
In a preferred embodiment of the invention, the first memory space and the second memory space are that identical stores sky
Between.
In a preferred embodiment of the invention, the second memory space is nonvolatile memory.
In a preferred embodiment of the invention, the expanding function of memory is that microcontroller is in on-chip system
Individual optional microprocessor core.
In a preferred embodiment of the invention, memory is flash memory, phase transition storage, resistance-variable storing device, magnetic storage
Device or ferroelectric memory.
In a preferred embodiment of the invention, microcontroller is the microcontroller of ARM or MIPS frameworks.
Memory compiler of the present invention is further described with specific embodiment with reference to figure：
The present embodiment is related to a kind of memory compiler, compared with the design data of legacy memory compiler generation, this
The design data of the memory compiler generation that embodiment is proposed not only includes the memory macro of current memory compiler generation
Unit, also at least includes the microcontroller of the frameworks such as a microcontroller, such as ARM, MIPS.Generated using the memory compiler
The flow of reservoir designs data is as shown in Figure 2：1) client proposes detailed design requirement first, specifically includes the appearance of memory
Amount, area and power consumption etc.；2) memory company/engineer obtains the design requirement of client and these requirements is input into storage
In device compiler, memory compiler is started working；3) what the generation of a period of time background storage compiler was met customer need deposits
The design data of reservoir.The structure of the memory macro unit generated using novel memory devices compiler proposed by the present invention is compared to biography
The structure of the memory macro unit of the memory compiler generation of system not only contains all constituents of in-line memory,
Also at least include a microcontroller.Using novel memory devices compiler proposed by the present invention generate memory structure at least by
Following two parts composition：1) memory macro unit, mainly includes memory plate 2_1, mainly (is used for including storage array 2_1_1
Data storage, the part of maximum area in memory) and the peripheral hardware 2_1_2 of memory (for example drive, decoder, sensitive amplification
Device etc.), the operation such as read and write to storage array for performing, such as the ranks decoder used when reading data, sensitive put
Big device etc.；2) microcontroller 2_2 (microcontroller of the framework such as such as ARM, MIPS etc.), read for control memory,
Write-in, selftest, self-optimization etc. are operated.
Specifically, the microcontroller of this novel memory devices compiler generation should at least include following functions：
Write operation：Perform write operation when, as shown in figure 3, novel memory devices compiler proposed by the present invention except
Produce outside above-mentioned basic part, crystal oscillator 2_3 (producing clock signal, make microcontroller normal work) is also produced to I haven't seen you for ages, the
One memory space 2_4 (will write the data of memory for storing), and first memory space 2_4 can be volatile memory
Or nonvolatile memory, optimal, first memory space 2_4 is nonvolatile memory.Performing write operation needs
The participation of following bus, respectively writes enable bus, data/address bus and address bus, writes enable bus and writes enable letter for transmission
Number, data/address bus is used to transmit data, and address bus is used to transmit address.In addition, microcontroller performs memory write operation
Specific steps it is as shown in Figure 4：1) write control signal (write enable signal) makes crystal oscillator 2_3 start working, and produces clock signal；
2) microcontroller 2_2 reads the address for needing to write data, by row, column decoder, determines data in storage array 2_1_1
The position that will be deposited；3) the peripheral hardware 2_1_2 of microcontroller 2_2 control memories writes the data in the first memory space 2_4
Enter to need the position of storage.The timing diagram of write operation is as shown in Figure 5 (assuming that now crystal oscillator is in running order), it is assumed that
Effectively, step is as follows for write enable signal high level：1) when rising edge clock arrives, microcontroller 2_2 receives write enable signal；
2) when write enable signal is changed into low level from high level, microcontroller 2_2 reads the address signal ADDR_ for needing to write data
1, by row, column decoder, determine the position that data will be deposited in storage array；3) microcontroller 2_2 controls peripheral hardware will
Data DATA_1 write-ins in first memory space 2_4 need the position of storage.
Read operation：The module carried out to memory using microcontroller 2_2 used in read operation is as shown in Figure 6.Perform
Read operation needs the participation of following bus, respectively reads to enable bus, data/address bus and address bus, and reading enable bus is used for
Transmission reads to enable signal, and data/address bus is used to transmit data, and address bus is used to transmit address.Microcontroller 2_2 performs reading and deposits
The specific steps of reservoir operation are as shown in fig. 7, specific as follows：1) microcontroller 2_2 receives reading and enables signal；2) microcontroller 2_
2 read the address signal for needing to read data, by row, column decoder, determine that data will be deposited in storage array 2_1_1
Position；3) microcontroller 2_2 control peripheral hardware 2_1_2 by the digital independent of relevant position out.The timing diagram of read operation is such as
Shown in Fig. 8, it is assumed that read to enable signal high level effectively, step is as follows：1) when rising edge clock arrives, microcontroller 2_2 is received
Signal is enabled to reading；2) when read enable signal is non-be changed into low level from high level when, microcontroller 2_2 read need read data
Address signal ADDR_2, by row, column decoder, determine position of the data in storage array；3) microcontroller 2_2 controls
Peripheral hardware 2_1_2 reads the data DATA_2 in storage array 2_1_1, is gone out to outside memory by data bus transmission.
Selftest and self-optimization：In traditional memory test, generally by ATE to storage
Device is tested, but this method of testing is larger to the degree of dependence of ATE, therefore is surveyed to reduce memory
The degree of dependence to automatic equipment is tried, at present by built-in detecting circuit in memory, by certain testing algorithm, to depositing
The storage array of reservoir carries out a series of test, such as behaviour is written and read to memory using memory built test circuit
Make, so that whether the problems such as having in finding storage array because of short circuit, open circuit, mutual interference influences asking for the functions such as reading and writing of memory
Topic.And the self-optimization of memory is the result that memory is obtained according to selftest, the parameter to memory is optimized, and is made
It can select a kind of optimal programme of work, improve the yield of Memory Storage Unit.Novel memory devices proposed by the present invention
The microcontroller of compiler generation can enter selftest and the self-optimization of line storage, without specific self-built test
Circuit.Module used in selftest and self-optimization is carried out to memory as shown in figure 9, in figure using microcontroller 2_2
The second memory space 2_5 be used to storing the code of selftest or/and self-optimization, the second memory space 2_5 is with described the
One memory space 2_4 can be same memory space, or different memory spaces, and the second memory space 2_5 can be
Nonvolatile memory or volatile memory, optimal, second memory space 2_5 is nonvolatile memory.Due to
Needed in download program to the second memory space 2_5 when selftest and self-optimization is carried out, it is therefore desirable to the second storage
The participation of space 2_5 and program entry bus.It is as shown in Figure 10 that memory carries out the step of selftest and self-optimization：1) lead to
Program entry bus is crossed by self-test, optimization program entry to the second memory space 2_5；2) microcontroller 2_2 performs second
Self testing procedure in memory space 2_5, selftest is carried out to memory；3) microcontroller 2_2 performs the second memory space
Self-optimizing program in 2_5, according to the result that selftest is obtained, optimizes to memory.
Expand：In the memory macro unit of legacy memory compiler generation, circuit usually uses DFT (Design
For Testability, Testability Design), will some special circuits the design phase implantation chip in (for example implantation sweep
Retouch chain etc., memory self-test circuit), to be tested memory after the completion of designing.But after the completion of test, deposit
The circuit as test being implanted into reservoir will become dark silicon (dark silicon, the transistor being stopped), cause core
The waste of piece area.In the present invention, the self test program of memory is performed by microcontroller 2_2, when having tested
After, microcontroller 2_2 can turn into an optional microprocessor core in on-chip system, without as dark silicon.Storage
The expanding function of device needs microcontroller 2_2 and outside bus of expanding to participate in.As shown in figure 11, optional microprocessor core is by outer
Portion expands bus and is connected to on-chip system bus, reconnects the other parts on on-chip system, such as external memory interface 2_7
(being used for external memorizer), other microprocessor cores 2_6 (the such as microprocessor of ARM, MIPS framework, and it is micro- in the present invention
Processor 2_2 constitutes multi-core microprocessor framework, such as the big.LITTLE frameworks of ARM companies), the 3rd memory 2_8 is (such as
Other memories of on-chip system), (peripheral hardware for connecting on-chip system, such as general input/output port is fixed for bridger 2_9
When device, digital analog converter, analog-digital converter, USB etc.).
In order to realize function above, the memory of this memory compiler generation should at least include following bus：1) control
Bus (Control Bus, CB), including storage write-in enables bus, storage reading and enables bus.2) data/address bus (Data
Bus, DB), carry out input, the output of data.3) the program entry bus needed for selftest, self-optimization.4) by microcontroller
Bus, such as AMBA buses etc. are expanded in outside needed for device 2_2 is expanded into optional microprocessor core.Additionally, also including that address is total
Line (Address Bus, AB).As figure 12 a shows, the related bus of write operation includes：Write enable bus, address bus, data
Bus；As shown in Figure 12b, the related bus of read operation includes：Read to enable bus, address bus, data/address bus；Such as Figure 12 c institutes
Show, self-test, self-optimizing associated bus lines include：Program entry bus；As shown in figure 12d, expanding associated bus lines includes：Open up outside
Exhibition bus.
As shown in figure 13, conventional compiler is only included for producing columns-decoders, storage core, sense amplifier, filling
The basic module of circuit etc. and the bank modules for combining these basic modules and control logic (control_
logic).In order to realize function above, memory compiler framework and legacy memory compiler frame that the present embodiment is proposed
Structure is compared：1) the Arm modules for realizing Arm functions are added, selected by mode identificating circuit Arm work four kinds of patterns-
Write mode, readout mode, selftest and self-optimization pattern, mode of extension.2) OSC modules are added for realizing crystal oscillator
Produce the function of clock signal.3) Code_Mem modules are added for realizing storage memory selftest and self-optimization generation
The function of code.4) Data_Mem modules are added for storing the initialization data parameter of each bank module, and self is surveyed
The Optimal Parameters produced after examination and self-optimization are as new data storage in Data_Mem.
Specifically should for novel memory devices compiler proposed by the present invention will be described in detail by a specific example below
With.
Memory compiler proposed by the present invention is applied to the generation of all of in-line memory macroelement, such as phase transformation
Memory, resistance-variable storing device, magnetic memory and ferroelectric memory etc..In the present embodiment, we come by taking phase transition storage as an example
Explanation.Flow using New-type phase change memory compiler generation reservoir designs data is as shown in figure 14：1) client carries first
Go out detailed design requirement, specifically include capacity (128Mb), area and power consumption of memory etc.；2) memory company/engineering
Teacher obtains the design requirement of client and these requirements is input in memory compiler, and memory compiler is started working；3)
The design data of the memory that the generation of a period of time background storage compiler is met customer need.Design data mainly includes
128Mb embedded phase change rams macroelement and the corresponding bus of function of the present invention is realized, i.e. data/address bus, control
Bus, address bus, program entry bus and expansion bus, data/address bus are used for transmitting data information, and controlling bus are used for
Transmission control command, address bus be used for transmission memory address information, program entry bus be used for memory selftest,
The typing of self-optimization program, bus is expanded in outside to be used to expand the optional microprocessor core in an on-chip system.
Figure 15 is the embedded phase change ram macroelement and an ARM of the 128Mb of novel memory devices compiler generation
The microcontroller of framework.It includes an embedded phase change storage array 3_1, the peripheral hardware 3_ required for storage array of 128Mb
The microcontroller 3_3 of 2, ARM frameworks, crystal oscillator 3_4, the first memory space 3_6 needed for write-in data (are deposited with non-volatile here
As a example by reservoir), the second memory space 3_7 (here by taking static RAM SRAM as an example)；Bus includes write-in data
Required writes enable bus, data/address bus, address bus, and the reading needed for reading data enables bus, data-out bus, address
Bus, program entry bus needed for selftest, self-optimization, and it is the optional microprocessor core institute on on-chip system to expand
The outside expansion bus for needing.
Novel memory devices compiler generation microcontroller proposed by the present invention has following functions：
Write operation：As shown in figure 16, write operation needs 128Mb embedded phase changes storage array 3_1, peripheral hardware 3_2,
The subparticipations such as the microprocessor 3_3 of ARM frameworks, crystal oscillator 3_4, the first memory space 3_5 are, it is necessary to write enable bus, data are total
Line and address bus are participated in.Write step is as shown in figure 17, specific as follows：1) write enable signal enables crystal oscillator 3_4 and starts working,
Produce clock signal；2) the microcontroller 3_3 of ARM frameworks reads the address signal for needing to write data, is decoded by row, column
Device, determines the position that data will be deposited in phase change memory array 3_1；3) the microcontroller 3_3 of ARM frameworks believes according to clock
Number, control peripheral hardware 3_2 is by the data write-in embedded phase change ram 3_1 in the first memory space 3_5.Write operation when
Sequence figure is as shown in figure 18 (assuming that crystal oscillator is in running order), it is assumed that effectively, step is as follows for write enable signal high level：1)
When rising edge clock arrives, ARM microcontroller 3_3 receives write enable signal, becomes from high level for write enable signal is non-herein
It is low level；2) when write enable signal is non-is changed into low level from high level, ARM microcontroller 3_3 reads to be needed to write data
Address signal ADDR_1, by row, column decoder, determine the position that data will be deposited in phase change memory array；3)ARM
Microcontroller 3_3 deposits the data DATA_1 write-in needs in the first memory space 3_5 according to clock signal, control peripheral hardware 3_2
The position put.
Read operation：Read operation needs 128Mb embedded phase changes storage array 3_1, peripheral hardware 3_2, ARM microcontroller 3_
3, the subparticipation such as crystal oscillator 3_4 are, it is necessary to read to enable bus, data/address bus and address bus are participated in, specific as shown in figure 19, read to make
Energy bus is used to transmit to be read to enable signal, and data/address bus is used to transmit address for transmitting data, address bus.Read operation
Step is as shown in figure 20, specific as follows：1) ARM microcontroller 3_3 receives reading and enables signal；2) ARM microcontroller 3_3 reads needs
The address signal of data is read, by row, column decoder, determines that data are deposited in 128Mb embedded phase change storage arrays 3_1
The position put；3) ARM microcontroller 3_3 is according to clock signal, control peripheral hardware 3_2 by the digital independent of relevant position out.Read
The timing diagram for going out operation is as shown in figure 21, it is assumed that read to enable signal high level effectively, step is as follows：1) arrived in rising edge clock
When, ARM microcontroller 3_3 receives reading and enables signal, and for reading is enabled, signal is non-to be changed into low level from high level herein；2) when reading makes
Can signal it is non-from high level be changed into low level when, ARM microcontroller 3_3 read need read data address signal ADDR_2,
By row, column decoder, position of the data in storage array 3_1 is determined；3) ARM microcontroller 3_3 is according to clock signal, control
Peripheral hardware 3_2 processed reads the data DATA_2 in 128Mb embedded phase change rams, is gone out to memory by data bus transmission
It is outside.
3) selftest and self-optimization：Selftest and self-optimization need 128Mb embedded phase change storage arrays
Join the part such as 3_1, peripheral hardware 3_2, ARM microprocessor 3_3, crystal oscillator 3_4, second memory space 3_7 (here by taking SRAM as an example)
With, needed in selftest and self-optimization download program to SRAM 3_7 when selftest and self-optimization is carried out, this
When need the participation of program entry bus, it is specific as shown in figure 22.In this example, using JTAG (Joint Test Action
Group, joint test working group) interface tested memory chip, and the jtag interface of standard is 4 lines：TMS、TCK、
TDI, TDO, respectively model selection, clock, data input and DOL Data Output Line, by jtag interface by program used for test typing
To in SRAM 3_7.The step of selftest and self-optimization, is as shown in figure 23, specific as follows：1) will by program entry bus
In self-test, optimization program entry to SRAM 3_7；2) ARM microcontroller 3_3 performs the selftest stored in SRAM 3_7
Program, carries out selftest, for example, all memory cell one writings are read with all units of checking again, and all memory cell are write
Whether " 0 " reads all units of checking again, to check short circuit, the open circuit problem of each unit, and has adjacent cells short circuit
Problem；For example to first memory cell write-in " 1 ", second memory cell writes " 0 ", by that analogy, until last
Memory cell, then reads all units of checking again, then opposite data are write to each unit, then reads all units of checking,
To detect that memory cell disturbs (can cause the change of state of memory cells around when reading and writing certain memory cell)；3) ARM is micro-
Controller 3_3 performs the self-optimization program in SRAM 3_7, self-optimization is carried out, according to the test result of memory, to depositing
The parameter of reservoir is optimized, and can select a kind of optimal programme of work, improves the yield of Memory Storage Unit.
4) expand：Expanding function needs ARM microprocessor 3_3, it is necessary to outside expansion bus participation, uses ARM in this example
The AMBA buses (Advanced Micro controller Bus Architecture) of company's research and development are expanded, and 2.0
Version AMBA standards define three groups of buses：(the Advanced High-performance Bus, AMBA high-performance is total for AHB
Line), ASB (the Advanced System Bus, AMBA system bus) and APB (the Advanced Peripheral
Bus, AMBA peripheral bus).Optional microprocessor core connects the other parts on on-chip system by AMBA buses, such as passes through
AHB or ASB connections high bandwidth external memory interface 3_10, high-performance arm processor 3_7, RAM 3_8, bridge on high-performance piece
Device 3_9 etc. is met, bridger passes through APB connection universals input/output port 3_11, USB 3_12 and timer 3_13
Deng specific as shown in figure 24.
In order to realize function above, the 128Mb phase transition storages macroelement of this memory compiler generation should at least be included
Following bus：1) controlling bus, including storage writes enable bus, storage and reads to enable bus.2) data/address bus.3) selftest,
Program entry bus (JTAG) needed for self-optimization.4) ARM microcontroller is expanded into opening up needed for optional microprocessor core
Exhibition bus (AMBA).Additionally, also including address bus.As shown in Figure 25 a, the related bus of write operation includes：Write enable bus,
Address bus, data/address bus；The related bus of read operation includes：As shown in figure 25b, enable bus, address bus, data are read total
Line；Shown in Figure 25 c, such as selftest, self-optimization associated bus lines include：Program entry bus；As shown in Figure 25 d, phase is expanded
Closing bus includes：Bus is expanded in outside.
To sum up, the design data of memory compiler generation disclosed by the invention is not only given birth to including current memory compiler
Into memory macro unit, also at least include a microcontroller.The microcontroller can not only realize traditional reading to memory
Write operation, moreover it is possible to realize to the selftest of memory, self-optimization and as optional microprocessor in an on-chip system
Device core is used.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
Change case is realized, be will not be described here.Such change case has no effect on substance of the invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (11)
1. a kind of memory compiler, it is characterised in that the design data of the memory of the memory compiler generation includes
Memory macro unit and microcontroller；
The microcontroller is for controlling the memory read, write, selftest and self-optimization are operated.
2. memory compiler as claimed in claim 1, it is characterised in that the memory macro unit includes memory plate,
The memory plate includes：
Storage array, for data storage；
Memory peripheral hardware, is connected with the storage array, for being read to the storage array, write operation.
3. memory compiler as claimed in claim 2, it is characterised in that the memory of the memory compiler generation is extremely
Include less：
Controlling bus, for transmission of control signals；
Data/address bus, for transmitting data；
Address bus, for transmitting address；
Program entry bus, for recording program；
Bus, the expanding function for realizing the memory are expanded in outside.
4. memory compiler as claimed in claim 3, it is characterised in that the controlling bus include：
Write-in enables bus, for transmitting write enable signal；
Read and enable bus, read to enable signal for transmitting.
5. memory compiler as claimed in claim 4, it is characterised in that the memory of the memory compiler generation
Design data also includes crystal oscillator and the first memory space and/or the second memory space.
6. memory compiler as claimed in claim 5, it is characterised in that first memory space is non-volatile memories
Device.
7. memory compiler as claimed in claim 5, it is characterised in that entered to the memory using the microcontroller
The module used during row write operation includes the memory macro unit, the microcontroller, the crystal oscillator and described first
Memory space；
The bus used when carrying out write operation to the memory using the microcontroller include it is described write enable bus,
The address bus and the data/address bus.
8. memory compiler as claimed in claim 7, it is characterised in that entered to the memory using the microcontroller
The step of row said write is operated includes：
The write enable signal for writing enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, the address of data to be written in first memory space is read,
And the data to be written position to be stored in storage array is determined by row, column decoder；
The data to be written are write the position to be stored by memory peripheral hardware described in the microprocessor control.
9. memory compiler as claimed in claim 5, it is characterised in that entered to the memory using the microcontroller
The module used during row read operation includes the memory macro unit, the microcontroller and the crystal oscillator；
The bus used when carrying out read operation to the memory using the microcontroller include it is described read enable bus,
The address bus and the data/address bus.
10. memory compiler as claimed in claim 9, it is characterised in that using the microcontroller to the memory
The step of carrying out the read operation includes：
The reading enable signal for reading to enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, reading is read out the address information of data, and is decoded by row, column
Device is read out data position to be stored in the storage array described in determining；
Memory peripheral hardware described in the microprocessor control is read out data described in reading.
11. memory compilers as claimed in claim 5, it is characterised in that using the microcontroller to the memory
The module for used when selftest and self-optimization operation includes the memory macro unit, the microcontroller, institute
State crystal oscillator and the second memory space；When selftest and self-optimization operation are carried out to the memory using the microcontroller
The bus for being used includes described program typing bus.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257646A (en) * | 2018-03-29 | 2018-07-06 | 榆林学院 | SRAM read-write indirectly testing device and methods based on LabVIEW |
| CN116700795A (en) * | 2023-08-01 | 2023-09-05 | 广州中基国威电子科技有限公司 | Bit operation control system and control method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1703674A (en) * | 2002-04-15 | 2005-11-30 | 德国捷德有限公司 | Optimisation of a compiler generated program code |
| US7062738B1 (en) * | 2002-07-25 | 2006-06-13 | Taiwan Semiconductor Manufacturing Company | Flash memory compiler with flexible configurations |
| CN102880497A (en) * | 2012-09-28 | 2013-01-16 | 无锡江南计算技术研究所 | Complier and method for reusing and optimizing software management memory |
| CN103314378A (en) * | 2010-08-23 | 2013-09-18 | 回忆系统公司 | Intelligent memory system compiler |
| EP3067795A1 (en) * | 2015-03-10 | 2016-09-14 | Gemalto Sa | A method for generating an embedded system derivable into a plurality of personalized embedded system |
-
2017
- 2017-01-20 CN CN201710049229.8A patent/CN106874577A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1703674A (en) * | 2002-04-15 | 2005-11-30 | 德国捷德有限公司 | Optimisation of a compiler generated program code |
| US7062738B1 (en) * | 2002-07-25 | 2006-06-13 | Taiwan Semiconductor Manufacturing Company | Flash memory compiler with flexible configurations |
| CN103314378A (en) * | 2010-08-23 | 2013-09-18 | 回忆系统公司 | Intelligent memory system compiler |
| CN102880497A (en) * | 2012-09-28 | 2013-01-16 | 无锡江南计算技术研究所 | Complier and method for reusing and optimizing software management memory |
| EP3067795A1 (en) * | 2015-03-10 | 2016-09-14 | Gemalto Sa | A method for generating an embedded system derivable into a plurality of personalized embedded system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257646A (en) * | 2018-03-29 | 2018-07-06 | 榆林学院 | SRAM read-write indirectly testing device and methods based on LabVIEW |
| CN116700795A (en) * | 2023-08-01 | 2023-09-05 | 广州中基国威电子科技有限公司 | Bit operation control system and control method |
| CN116700795B (en) * | 2023-08-01 | 2023-12-01 | 广州中基国威电子科技有限公司 | Bit operation control system and control method |
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