CN100590444C

CN100590444C - Variegated BIST test approach

Info

Publication number: CN100590444C
Application number: CN200610119193A
Authority: CN
Inventors: 陈凯华; 谢晋春; 陈婷; 辛吉升; 桑浚之
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-12-06
Filing date: 2006-12-06
Publication date: 2010-02-17
Anticipated expiration: 2026-12-06
Also published as: CN101196555A

Abstract

The invention relates to a method for chip testing and discloses a diversified test method for BIST, which comprises the following steps: test the NVM through the logic Interface unit; convert the test image to the instruction set in the code form and store in the NVM area; the CPU enabled by the external instructions reads the instruction set in the NVM area and energizes the circuit in the chipaccording to the instruction set; after receiving the response, return the PWL or code on the inport or output; erase the code in the NVM, repeat the above steps and then conduct operation of the nexttest image. The diversified test method for BIST provided in the invention can greatly save the chip area and test channel, increase the concurrent-testing capacity and reduce the dependence to the test hardware.

Description

The BIST method of testing

Technical field

The present invention relates to chip detecting method, relate in particular to a kind of BIST (Built In Self Test, built-in self-test) method of testing.

Background technology

Add excitation by tester from outside seal during chip testing and give chip, meet with a response then and expection is made comparisons, judge whether chip is non-defective unit.

The chip of more complicated needs more pin, and needed passage is drawn also and linked to each other with the passage of test during with test, and is corresponding one by one, the excitation of acceptance test instrument, and return signal judges to tester, but this kind method chips area is too big, and cost is too high.

For saving chip area, can reduce PAD, the minimizing test channel of chip in some design, for reaching same wrong coverage rate, the degree of depth that will inevitably deepen resolution chart.But existing tester or some testing softwares possibly can't satisfy these requirements, because the degree of depth increases, the test duration also increases greatly simultaneously.

Traditional BIST (Built In Self Test, built-in self-test) method is normally carried out BIST for hardware, the circuit of understanding an expense part by the design increase testing algorithm of circuit goes to do this test specially, this part circuit has in actual applications to no avail been wasted the segment chip area after the end of test (EOT).These algorithms are dumb simultaneously, and designs fix can't be changed later, and more wrong coverage rate can't be tested.

Common SOC (System On Chip, the integrated system single-chip) chip design as shown in Figure 1, each module has independently, and PAD (pin) draws from chip, be added in each PAD (pin) signal excitation by seal respectively when test, passing through of each module or failure conditions were judged in the response that obtains separately afterwards.This method of testing is convenient relatively for test, but final encapsulation does not need all PAD are encapsulated when using, and these unnecessary PAD have expended a large amount of useless areas, makes the integral body of chip become big, the single-chip output tails off, and it is big that the single-chip cost becomes.Need each pin allocation for test passage all for identical tester table, have been reduced greatly with surveying number when testing simultaneously.

In order to solve the excessive problem of area and to increase with surveying number, pass through to increase serial port circuit during some SOC design, with all pumping signals by few PAD (pin) as only PADl and PAD2 among Fig. 1, to take into account all test errors coverage rates like this, the degree of depth of pumping signal will certainly increase a lot, test duration increases, and the ability that the hardware graphics of tester produces is challenged.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of BIST method of testing, can greatly save chip area, increases the same survey ability of tester.

In order to solve the problems of the technologies described above, BIST method of testing of the present invention, chip under test comprises Logic Interface Unit, NVM, CPU and other circuit unit, comprises the steps:

(1) by Logic Interface Unit NVM is tested, to guarantee the measurability of NVM;

(2) resolution chart is converted to the instruction set of code format after, deposit in the NVM district;

(3) CPU that activates through external command reads instruction set in the NVM district, and according to the content of this instruction set other circuit unit in the chip is encouraged;

(4) obtain the response of each other circuit unit after, on input/output port, return level or code, with the expression test result;

(5) wipe code in the NVM, repeating step (2) carries out the operation of next resolution chart to (4) again.

BIST method of testing of the present invention by reducing PAD, can greatly be saved chip area, saves test channel, increases with the survey ability; By down operation, can simplify the resolution chart of tester, reduce dependence to testing hardware; Carry out software BIST neatly, and carry out the test of various required resolution charts, remove the permanent circuit of hardware BIST; According to the bus ability of CPU, can carry out multi-path test during test, and can not increase MTD greatly, influence the test duration.

Description of drawings

Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.

Fig. 1 is existing integrated system single chip design may figure;

Fig. 2 is the process flow diagram of BIST method of testing of the present invention.

Embodiment

BIST method of testing of the present invention, utilize the part resource of chip itself, particularly erasable memory source is tested the other parts function of chip, with on the basis that guarantees the test errors coverage rate, reduce test platform and the designing requirement of chip own.

The embedded Flash district of chip is generally used for depositing software code in actual product is used, be used for instruction database that its CPU operates system etc.Utilize these characteristics that the function command of all need tests is deposited in this NVM (Non-Volatile Memory in advance, non-volatility memorizer) in the zone, these instructions of simply instructing activation CPU to go to call and operate this memory block by the outside get final product then.

BIST method of testing of the present invention comprises the minimizing number of pin, also comprises the steps (see figure 2):

(3) CPU that activates through external command reads instruction set in the NVM district, and according to the content of this instruction set the circuit unit in the chip is encouraged;

(4) obtain the response of each circuit unit after, on input/output port, return level or code, with the expression test result;

In one embodiment of the invention, two pin PAD1 only open shown in Figure 1 and PAD2.When carrying out the BIST test, concrete steps are as described below:

(1) be that Logic Interface Unit is read and write NVM and other certain operations is tested by logical order, purpose is in order to guarantee that this storage unit can use, owing to will consider the measurability of NVM during chip design, the interface of NVM must be drawn separately, or by drawing after other logical channel control, but must accomplish and directly to control independently, so that directly the NVM district is carried out independent operation.

(2) NVM is finished test after, the wave file format conversion that will be used to test the traditional test figure of difference in functionality by logic interfacing becomes the programming code form, as in the 0x1 of NVM address, data 0x5A etc., so that directly NVM is carried out programming operation, and this instruction set that converts code format to downloaded to the NVM memory block by logic interfacing.

Simply encourage activation CPU to remove NVM zone reading command collection by the outside when (3) testing, content according to instruction set, by intrasystem bus, other circuit unit such as SRAM (static memory) etc. in the chip encouraged, wherein, outside simple excitation comprises adopts traditional resolution chart, can realize activation to CPU as only adding clock or a string code.

(4) behind the excitation-off of CPU to other circuit, obtain response, finally on PAD1 or PAD2, return particular code or level, to represent the test result of this partial function.

(5) NVM is once wiped, download program code can carry out the operation of next resolution chart again.

Claims

1. BIST method of testing, chip under test comprises Logic Interface Unit, NVM, CPU and other circuit unit, it is characterized in that, comprises the steps:

2. BIST method of testing as claimed in claim 1 is characterized in that, the test in the described step (1) comprises read-write and operational testing.