CN106233463A - 带贯通电极的半导体芯片用粘接膜 - Google Patents

带贯通电极的半导体芯片用粘接膜 Download PDF

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Publication number
CN106233463A
CN106233463A CN201580020776.2A CN201580020776A CN106233463A CN 106233463 A CN106233463 A CN 106233463A CN 201580020776 A CN201580020776 A CN 201580020776A CN 106233463 A CN106233463 A CN 106233463A
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Prior art keywords
electrode
semiconductor chip
band
adhesive film
inorganic filler
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永田麻衣
竹田幸平
江南俊夫
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Sekisui Chemical Co Ltd
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Sekisui Chemical Co Ltd
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Publication of CN106233463A publication Critical patent/CN106233463A/zh
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Abstract

本发明的目的在于，提供一种用于在半导体晶片上层叠多个带贯通电极的半导体芯片的、能够在抑制空隙的同时良好地连接贯通电极且能够抑制在半导体芯片的周围突出的毛刺的长度的带贯通电极的半导体芯片用粘接膜。本发明的带贯通电极的半导体芯片用粘接膜，用于在半导体晶片上层叠多个带贯通电极的半导体芯片，其中，最低熔融粘度为50～2500Pa·s，且140℃的触变指数为8以下。

Description

带贯通电极的半导体芯片用粘接膜
技术领域
本发明涉及用于在半导体晶片上层叠多个带贯通电极的半导体芯片的、能够在抑制空隙的同时对贯通电极良好地进行电极接合且能够抑制在半导体芯片的周围突出的毛刺的长度的带贯通电极的半导体芯片用粘接膜。
背景技术
近年来，使用了具有由焊料等构成的突起电极(凸起)的半导体芯片的倒装式芯片贴装受到关注。
在倒装式芯片贴装中，一般使用在基板上接合半导体芯片之后注入密封树脂的方法。在专利文献1中记载了粘度为50Pa·sec以下(25℃)且注入时的粘度为2Pa·sec以下的密封树脂。
此外，近年来随着半导体芯片的小型化的进展，电极间的间距也变得越来越窄，而且与此相伴地半导体芯片彼此或半导体芯片与基板之间的缝隙也变窄，因此不是在接合后注入密封树脂，而是采用经由预先涂敷在基板上的液状粘接剂来接合半导体芯片的方法。在专利文献2中记载了固化前的触变指数为1.1～4.0且能够以维持形状的状态进行涂敷的液状环氧树脂组合物。
进而，还采用了经由预先粘合在基板或半导体芯片的粘接膜(NCF)来接合半导体芯片的方法。在专利文献3中记载了最小熔融粘度的范围为40PaS～5100PaS的片状粘接剂。此外，在专利文献3记载了如下内容，即，针对由于压接而使片状粘接剂的一部分横向渗出而从半导体元件的侧面蔓延至上表面的问题，专利文献3记载的片状粘接剂是能够很好地抑制粘接剂向侧方渗出而不易产生由多余的渗出造成的不合格品的片状粘接剂。
然而，在这种方法中存在接合时在电极间产生气泡(空隙)的情况，此外，因为通过加热同时进行“电极接合”和“粘接膜的固化”，所以不容易兼顾精度高的电极接合和空隙的抑制。
另一方面，近年来，在倒装式芯片贴装中，层叠多个半导体芯片而使器件飞跃式地高性能化、小型化的使用了TSV(Si贯通过孔/Through Silicon via)的三维层叠技术尤其受到关注。
在TSV层叠技术中，一般在半导体晶片上的划分为格子状的各接合部位经由粘接膜对多个带贯通电极的半导体芯片(TSV芯片)层叠为多层，然后沿着格子状的切割线切割半导体晶片，从而制造多层半导体芯片层叠体。
然而，因为是将大小一致的半导体芯片层叠为多层，所以粘接膜在半导体芯片的周围呈毛刺状突出的情况成为问题。这种毛刺(边缘部、端部)可能在所层叠的半导体芯片间的任一位置产生，当毛刺长时，切割时毛刺会剥落而污染周边造成产品不合格。如果加宽切割线的间隔，则即使毛刺长也不会在切割时剥落，但是从生产性的观点考虑，希望使切割线的间隔变窄。
此外，虽然也可以将例如专利文献3记载的片状粘接剂应用于TSV层叠技术，但是该片状粘接剂不是针对将半导体芯片层叠为多层的情况而设计的，而是以在基板上接合半导体芯片的情况下抑制粘接剂向侧方溢出为目的设计的，因此不能充分抑制毛刺的长度。
在先技术文献
专利文献
专利文献1：国际公开第08/018557号
专利文献2：日本特开2007-51184号公报
专利文献3：日本特开2007-9022号公报
发明内容
发明要解决的课题
本发明的目的在于，提供一种用于在半导体晶片上层叠多个带贯通电极的半导体芯片的、能够在抑制空隙的同时对贯通电极良好地进行电极接合且能够抑制在半导体芯片的周围突出的毛刺的长度的带贯通电极的半导体芯片用粘接膜。
用于解决课题的技术方案
本发明的带贯通电极的半导体芯片用粘接膜，用于在半导体晶片上层叠多个带贯通电极的半导体芯片，其中，最低熔融粘度为50～2500Pa·s，且140℃的触变指数为8以下。
以下，对本发明进行详细说明。
本发明的发明人发现，在用于在半导体晶片上层叠多个带贯通电极的半导体芯片的带贯通电极的半导体芯片用粘接膜中，通过将最低熔融粘度和140℃的触变指数调整为特定的窄范围，从而能够在抑制空隙的同时对贯通电极良好地进行电极接合，进而，能够减少在半导体芯片的周围突出的毛刺的量。进而，本发明的发明人还发现，通过使用这种带贯通电极的半导体芯片用粘接膜，从而不仅毛刺的量本身减少，而且带贯通电极的半导体芯片用粘接膜会与半导体芯片的周围融合而像液滴生长那样一边形成大致半球形一边突出，因此难以产生长的毛刺，从而最终完成了本发明。
本发明的带贯通电极的半导体芯片用粘接膜用于在半导体晶片上层叠多个带贯通电极的半导体芯片。
本发明的带贯通电极的半导体芯片用粘接膜的最低熔融粘度为50～2500Pa·s，并且140℃的触变指数为8以下。通过具有这样窄的范围的最低熔融粘度和140℃的触变指数，从而本发明的带贯通电极的半导体芯片用粘接膜能够在抑制空隙的同时对贯通电极良好地进行电极接合，进而，能够减少在半导体芯片的周围突出的毛刺的量。进而，本发明的带贯通电极的半导体芯片用粘接膜会与半导体芯片的周围融合而像液滴生长那样一边形成大致半球形一边突出，因此难以产生长的毛刺。
当上述最低熔融粘度不足50Pa·s时，在接合带贯通电极的半导体芯片时容易在电极间产生空隙。当上述最低熔融粘度超过2500Pa·s时，容易阻碍贯通电极的电极接合。上述最低熔融粘度的优选的下限为70Pa·s，优选的上限2300Pa·s，更优选的下限为100Pa·s，更优选的上限为2000Pa·s。
另外，最低熔融粘度是指，从常温到焊料熔点的温度区域中的最低复粘度η＊min，能够通过如下方式求出，即，使用流变仪(例如，REOLOGICA公司制造的STRESSTECH)在样品厚度为600μm、应变控制为(1rad)、频率为10Hz、升温速度为20℃/min的条件下在测定温度范围60℃至300℃对带贯通电极的半导体芯片用粘接膜进行测定。
当上述140℃的触变指数超过8时，不能充分地抑制在半导体芯片的周围突出的毛刺的长度，切割时毛刺会剥落而污染周边造成产品不合格。上述140℃的触变指数的优选的上限为7，更优选的上限为6。此外，上述140℃的触变指数的下限没有特别限定，但是从保持膜形状的观点出发，优选的下限为1.5。
另外，140℃的触变指数是指{复粘度η＊(1Hz)}/{复粘度η＊(10Hz)}的值，能够通过如下方式求出，即，使用流变仪(例如，REOLOGICA公司制造的STRESSTECH)在样品厚度为600μm、应变控制为(1rad)、频率为1Hz或10Hz、温度为140℃的条件下对带贯通电极的半导体芯片用粘接膜进行测定。另外，在半导体晶片上层叠多个带贯通电极的半导体芯片时，带贯通电极的半导体芯片用粘接膜在固化之前会暴露在80～160℃左右的温度，会在某种程度上熔融，因此作为该温度范围内的代表性的触变指数而测定140℃的触变指数。
作为将上述最低熔融粘度和上述140℃的触变指数调整为上述范围的方法，例如可举出对优选包含热固化性树脂和热固化剂的本发明的带贯通电极的半导体芯片用粘接膜进一步掺合无机填料的方法。其中，尤其优选调整无机填料的平均粒径和含量的方法或控制无机填料的掺合方法的方法。
作为调整上述无机填料的平均粒径和含量的方法，可举出并用两种以上的平均粒径不同的无机填料的方法。更具体地，例如可举出并用平均粒径为10～100nm的无机填料(A)和平均粒径为150～500nm的无机填料(B)的方法。像这样，通过并用平均粒径比较小的无机填料(A)和平均粒径比较大的无机填料(B)，从而容易将上述140℃的触变指数调整为上述范围，其结果是，在作为一般被认为难以调整熔融时的触变指数的膜状粘接剂的本发明的带贯通电极的半导体芯片用粘接膜中，容易调节熔融时的触变指数。
在制备上述无机填料的平均粒径和含量的方法中，当无机填料(A)的平均粒径不足10nm时，带贯通电极的半导体芯片用粘接膜的流动性会降低，存在不能进行适当的电极接合的情况。当上述无机填料(A)的平均粒径超过100nm时，因为接近上述无机填料(B)的平均粒径，所以存在基本得不到并用两种以上的平均粒径不同的无机填料的效果的情况。上述无机填料(A)的平均粒径的更优选的下限为15nm，更优选的上限为80nm。
另外，无机填料的平均粒径例如能够利用透射电子显微镜、扫描电子显微镜、测定重量平均粒径的动态光散射式测定装置(例如，BECKMANCOULTER公司制造的N4PLUS超微粒子分析装置等)等进行测定。
在制备上述无机填料的平均粒径和含量的方法中，当无机填料(B)的平均粒径不足150nm时，因为接近上述无机填料(A)的平均粒径，所以存在基本得不到并用两种以上的平均粒径不同的无机填料的效果的情况。当上述无机填料(B)的平均粒径超过500nm时，存在上述无机填料(B)夹入到电极间的情况，或者存在带贯通电极的半导体芯片用粘接膜的光透射性降低而无法对准半导体晶片和带贯通电极的半导体芯片的情况。上述无机填料(B)的平均粒径的更优选的下限为200nm，更优选的上限为400nm。
在制备上述无机填料的平均粒径和含量的方法中，优选带贯通电极的半导体芯片用粘接膜中的无机填料(A)的含量为5～40重量％、无机填料(B)的含量为5～50重量％。当这些无机填料的含量脱离上述范围时，存在难以调整上述最低熔融粘度和上述140℃的触变指数的情况。
上述无机填料(A)的含量的更优选的下限为10重量％，更优选的上限为38重量％，进一步优选的下限为15重量％，进一步优选的上限为35重量％。
上述无机填料(B)的含量的更优选的下限为10重量％，更优选的上限为47重量％，进一步优选的下限为15重量％，进一步优选的上限为45重量％。
上述无机填料的原料没有特别限定，例如可举出雾化二氧化硅、胶体二氧化硅等二氧化硅、氧化铝、氮化铝、氮化硼、氮化硅、玻璃粉、玻璃熔料等。
作为控制上述无机填料的掺合方法的方法，可举出如下方法，即，将使无机填料悬浮在溶剂中的无机填料悬浮液分多次添加到混合无机填料以外的成分而得到的混合物，从而制备树脂组合物，并使用该树脂组合物制造带贯通电极的半导体芯片用粘接膜。当一次添加大量的无机填料时，会产生无机填料的凝聚而使分散性变差，难以将140℃的触变指数调整为所期望的范围。通过分多次添加使无机填料悬浮在溶剂中的无机填料悬浮液，从而能够防止无机填料的凝聚而得到具有所期望的触变指数的带贯通电极的半导体芯片用粘接膜。
在控制上述无机填料的掺合方法的方法中使用的无机填料没有特别限定，例如，可以单独使用上述无机填料(A)，也可以单独使用上述无机填料(B)，还可以并用上述无机填料(A)和无机填料(B)。此外，关于上述无机填料(A)和/或无机填料(B)的含量，也能够设为与制备上述无机填料的平均粒径和含量的方法相同的范围。
另外，本发明的带贯通电极的半导体芯片用粘接膜通过含有上述无机填料，从而不仅容易将上述最低熔融粘度和上述140℃的触变指数调整为上述范围，而且带贯通电极的半导体芯片用粘接膜的固化后的线膨胀率会降低，能够良好地防止对半导体芯片等产生应力以及在焊料等导通部分产生裂缝。
上述无机填料整体的含量没有特别限定，相对于后述的热固化性树脂和高分子化合物的合计100重量份，其优选的下限为5重量份，优选的上限为500重量份。当上述无机填料整体的含量不足5重量份时，存在基本得不到添加上述无机填料的效果的情况。当上述无机填料整体的含量超过500重量份时，虽然带贯通电极的半导体芯片用粘接膜的固化后的线膨胀率会降低，但是拉伸弹性率会上升，存在容易对半导体芯片等产生应力以及容易在焊料等导通部分产生裂缝的情况。上述无机填料整体的含量的更优选的下限为10重量份，更优选的上限为400重量份，进一步优选的下限为15重量份，进一步优选的上限为300重量份。
本发明的带贯通电极的半导体芯片用粘接膜优选含有热固化性树脂和热固化剂。
上述热固化性树脂没有特别限定，例如，可举出通过加成缩合、缩聚、聚加成、加成缩合、开环聚合等反应进行固化的化合物。作为上述热固化性树脂，具体可举出例如尿素树脂、三聚氰胺甲醛树脂、酚醛树脂、间苯二酚树脂、环氧树脂、丙烯酸树脂、聚酯树脂、聚酰胺树脂、聚苯并咪唑树脂(ポリベンズイミダゾ一ル樹脂)、邻苯二甲酸二烯丙酯树脂(ジアリルフタレ一ト樹脂)、二甲苯树脂、烷基苯树脂、环氧丙烯酸酯树脂、硅树脂、聚氨酯树脂等。
上述环氧树脂没有特别限定，例如可举出软化点为150℃以下的环氧树脂、常温下为液体或晶体性固体的环氧树脂等。这些环氧树脂可以单独使用，也可以并用两种以上。
在含有上述环氧树脂的情况下，本发明的带贯通电极的半导体芯片用粘接膜还可以含有具有能够与上述环氧树脂反应的官能团的高分子化合物(仅称为高分子化合物)。上述高分子化合物发挥作为造膜成分的作用。此外，通过含有上述高分子化合物，从而带贯通电极的半导体芯片用粘接膜的固化物具有韧性，能够表现出优异的耐冲击性。
上述高分子化合物没有特别限定，例如可举出具有氨基、氨基甲酸乙酯基、酰亚胺基、羟基、羧基、环氧基等的高分子化合物等。其中，尤其优选具有环氧基的高分子化合物。通过含有上述具有环氧基的高分子化合物，从而带贯通电极的半导体芯片用粘接膜的固化物将同时具备来自上述环氧树脂的优异的机械强度、耐热性和耐湿性以及来自上述具有环氧基的高分子化合物的优异的韧性，由此能够表现出高接合可靠性和连接可靠性。
上述具有环氧基的高分子化合物只要是在末端和/或支链(侧位)具有环氧基的高分子化合物即可，没有特别限定，例如可举出含环氧基丙烯酸橡胶、含环氧基丁二烯橡胶、双酚型高分子量环氧树脂、含环氧基苯氧基树脂、含环氧基丙烯酸树脂、含环氧基聚氨酯树脂、含环氧基聚酯树脂等。
上述热固化剂没有特别限定，例如，可举出酚系固化剂、硫醇系固化剂、胺系固化剂、酸酐系固化剂等。
上述热固化剂的含量没有特别限定，相对于上述热固化性树脂和上述高分子化合物的合计100重量份，优选的下限为5重量份，优选的上限为150重量份。当上述热固化剂的含量不足5重量份时，带贯通电极的半导体芯片用粘接膜的固化物会变硬变脆，因此存在接合可靠性变差的情况。当上述热固化剂的含量超过150重量份时，也存在带贯通电极的半导体芯片用粘接膜的接合可靠性降低的情况。上述热固化剂的含量的更优选的下限为10重量份，更优选的上限为140重量份。
本发明的带贯通电极的半导体芯片用粘接膜还可以含有固化促进剂。
上述固化促进剂没有特别限定，优选咪唑化合物。上述咪唑化合物与上述环氧树脂的反应性高，因此通过含有上述环氧树脂和上述咪唑化合物，从而可提高带贯通电极的半导体芯片用粘接膜的快速固化性。
本发明的带贯通电极的半导体芯片用粘接膜可以在不阻碍本发明的效果的范围内含有稀释剂。上述稀释剂没有特别限定，优选导入到带贯通电极的半导体芯片用粘接膜的固化系的反应性稀释剂。其中，为了不使带贯通电极的半导体芯片用粘接膜的接合可靠性变差，更优选在一个分子中具有两个以上的官能团的反应性稀释剂。
上述稀释剂的含量没有特别限定，相对于上述热固化性树脂与上述高分子化合物的合计100重量份，优选的下限为1重量份，优选的上限为300重量份。当上述稀释剂的含量不足1重量份时，存在基本得不到添加上述稀释剂的效果的情况。当上述稀释剂的含量超过300重量份时，带贯通电极的半导体芯片用粘接膜的固化物会变硬、变脆，因此存在接合可靠性变差的情况。上述稀释剂的含量的更优选的下限为5重量份，更优选的上限为200重量份。
本发明的带贯通电极的半导体芯片用粘接膜也可以根据需要而含有无机离子交换体。上述无机离子交换体的含量没有特别限定，本发明的带贯通电极的半导体芯片用粘接膜中的优选的下限为1重量％，优选的上限为10重量％。
本发明的带贯通电极的半导体芯片用粘接膜也可以根据其它需要而含有渗出防止剂、硅烷偶联剂、助熔剂、增粘剂等添加剂。
制造本发明的带贯通电极的半导体芯片用粘接膜的方法没有特别限定，例如可举出如下方法等，即，根据需要掺合规定量的热固化性树脂、热固化剂、固化促进剂、高分子化合物、无机填料、溶剂、其它添加剂等并进行混合，将得到的树脂组合物涂敷在脱模膜上并使其干燥。上述混合的方法没有特别限定，例如可举出使用高速分散机、万能混合机、班伯里混合机、捏合机等的方法。
本发明的带贯通电极的半导体芯片用粘接膜用于在半导体晶片上层叠多个带贯通电极的半导体芯片。
使用本发明的带贯通电极的半导体芯片用粘接膜在半导体晶片上层叠多个带贯通电极的半导体芯片的方法没有特别限定，优选如下方法，该方法包括：在半导体晶片上的接合部位经由本发明的带贯通电极的半导体芯片用粘接膜虚粘接第一带贯通电极的半导体芯片的工序(1)；在上述第一带贯通电极的半导体芯片上经由本发明的带贯通电极的半导体芯片用粘接膜虚粘接第二带贯通电极的半导体芯片的工序(2)；根据需要重复上述工序(2)的工序(3)；以及对得到的虚粘接体进行加热而对贯通电极进行电极接合的工序(4)。
在上述工序(1)中在上述半导体晶片上的接合部位虚粘接上述第一带贯通电极的半导体芯片的方法没有特别限定，例如可举出如下方法等，即，在将本发明的带贯通电极的半导体芯片用粘接膜供给到上述第一带贯通电极的半导体芯片之后，使用倒装芯片焊接机等安装用装置将上述第一带贯通电极的半导体芯片与上述半导体晶片上的接合部位对齐，在规定温度(也称为虚粘接温度)对本发明的带贯通电极的半导体芯片用粘接膜加热规定时间(也称为虚粘接时间)。
将本发明的带贯通电极的半导体芯片用粘接膜供给到上述第一带贯通电极的半导体芯片的方法没有特别限定，例如可举出将本发明的带贯通电极的半导体芯片用粘接膜层压在带贯通电极的半导体芯片的方法、在将本发明的带贯通电极的半导体芯片用粘接膜层压在带贯通电极的半导体晶片之后单片化为带贯通电极的半导体晶片的方法等。
通过控制上述虚粘接温度和上述虚粘接时间，从而能够在不使本发明的带贯通电极的半导体芯片用粘接膜完全固化的情况下在上述半导体晶片上的接合部位以某种程度粘接(即，虚粘接)上述第一带贯通电极的半导体芯片。另外，在这种进行虚粘接的状态下，贯通电极尚未进行电极接合。贯通电极的电极接合将在后述的工序(4)中进行。
上述虚粘接温度没有特别限定，只要采用能够进行虚粘接的温度且比本发明的带贯通电极的半导体芯片用粘接膜的固化温度低的温度即可，与本发明的带贯通电极的半导体芯片用粘接膜的固化温度之差的优选的下限为10℃，优选的上限为200℃，更优选的下限为15℃，更优选的上限为150℃。具体地，上述虚粘接温度优选为40～200℃左右，更优选为60～180℃左右。
上述虚粘接时间优选为0.1～60秒。
在上述工序(2)和上述工序(3)中，只要使用与上述工序(1)同样的方法对带贯通电极的半导体芯片进行虚粘接即可。
通过进行这些工序，从而能够对虚粘接在上述半导体晶片上的多个带贯通电极的半导体芯片统一进行电极接合，与一层一层地重叠带贯通电极的半导体芯片并依次进行电极接合的情况相比，能够提高生产性。进而，通过对上述半导体晶片上的多个虚粘接体统一进行电极接合，从而能够进一步提高生产性。
在上述工序(4)中对上述虚粘接体进行加热而对贯通电极进行电极接合的方法没有特别限定，例如在贯通电极为焊料电极的情况下，可举出如下方法等，即，使用倒装芯片焊接机等安装用装置在60～220℃左右的接触温度(使电极接触的温度)加热0.1～60秒左右，然后在230～300℃左右的焊料熔融温度以上的温度加热0.1～60秒左右。
通过控制加热条件，能够良好地进行电极接合。此外，根据加热条件，也能够使本发明的带贯通电极的半导体芯片用粘接膜完全固化而良好地粘接多个带贯通电极的半导体芯片。
在上述工序(4)中，优选对最上层的带贯通电极的半导体芯片进行按压，进行贯通电极的电极接合，并且将本发明的带贯通电极的半导体芯片用粘接膜填充到密封区域。
进行上述按压时的压力没有特别限定，优选为1～200N。此外，每个电极平均的压力优选为0.0001～1N。当上述每个电极平均的压力不足0.0001N时，存在电极彼此不接触的情况。当上述每个电极平均的压力超过1N时，存在电极过于塌陷而与相邻的电极接触从而短路的情况。
在上述工序(4)中，本发明的带贯通电极的半导体芯片用粘接膜可以完全固化，也可以固化至中间阶段。在进行电极接合时本发明的带贯通电极的半导体芯片用粘接膜未完全固化而固化至中间阶段的情况下，可以在电极接合后进行第二阶段的加热，使本发明的带贯通电极的半导体芯片用粘接膜完全固化。
在上述工序(1)～(4)之后，可以进一步单独进行使本发明的带贯通电极的半导体芯片用粘接膜完全固化的工序(5)。
只要根据需要在电极接合后使本发明的带贯通电极的半导体芯片用粘接膜完全固化即可，无需为了同时进行电极接合和本发明的带贯通电极的半导体芯片用粘接膜的固化而一下子进行加热，因此能够防止由于带贯通电极的半导体芯片的厚度或电极高度的偏差而造成的不能均匀地加热、使成品率降低的问题。
通过进行上述工序(1)～(4)以及根据需要进行上述工序(5)，能够使用本发明的带贯通电极的半导体芯片用粘接膜在半导体晶片上层叠多个带贯通电极的半导体芯片。
图1示出截面示意图，该截面示意图示出通过本发明的带贯通电极的半导体芯片用粘接膜在半导体晶片上层叠有多个带贯通电极的半导体芯片的状态的一个例子。在图1中，通过本发明的带贯通电极的半导体芯片用粘接膜1在半导体晶片3上层叠有多个带贯通电极的半导体芯片2。
通过使用本发明的带贯通电极的半导体芯片用粘接膜1，从而能够抑制在半导体芯片的周围突出的毛刺5的长度。因此，能够抑制在使用切割刀4沿着格子状的切割线切割半导体晶片3时毛刺剥落而污染周边。此外，因为能够抑制毛刺5的长度，所以能够使切割线的间隔变窄，能够进一步提高生产性。
发明效果
根据本发明，能够提供一种用于在半导体晶片上层叠多个带贯通电极的半导体芯片的、能够在抑制空隙的同时对贯通电极良好地进行电极接合且能够抑制在半导体芯片的周围突出的毛刺的长度的带贯通电极的半导体芯片用粘接膜。
附图说明
图1示出截面示意图，该截面示意图示出通过本发明的带贯通电极的半导体芯片用粘接膜在半导体晶片上层叠有多个带贯通电极的半导体芯片的状态的一个例子。
具体实施方式
以下，举出实施例对本发明的方案进行更详细的说明，但是本发明并不只限定于这些实施例。
(实施例1)
(1)粘接膜的制造
(A法)
按照表2、表3记载的组成，将预先使无机填料悬浮在溶剂中的无机填料悬浮液每次各一半地分两次添加到将除无机填料以外的下述以及表1所示的材料添加到溶剂并进行搅拌混合而得到的混合物中，并进行搅拌混合而制备树脂组合物。将得到的树脂组合物涂敷在脱模膜上并使其干燥，从而得到粘接膜。
(B法)
按照表2、表3记载的组成，将下述以及表1所示的材料添加到溶剂中进行搅拌混合而制备树脂组合物。将得到的树脂组合物涂敷在脱模膜上并使其干燥，从而得到粘接膜。
1.热固化性树脂
双酚A固形环氧树脂(1004AF、三菱化学公司制造)
双酚F液状环氧树脂(EXA-830CRP、DIC公司制造)
二环戊二烯型环氧树脂(HP7200HH、DIC公司制造)
缩水甘油胺型环氧树脂(EP-4088L、ADEKA公司制造)
2.高分子化合物
丙烯酸树脂(G-2050M、日油公司制造)
3.热固化剂和固化促进剂
酸酐(YH-309、三菱化学公司制造)
咪唑(2MAOK-PW、四国化成工业公司制造)
4.无机填料
4-1.无机填料(A)
球状二氧化硅(YA010C-SP1、ADMATECHS公司制造、平均粒径为0.01μm)
球状二氧化硅(YA050C-SP1、ADMATECHS公司制造、平均粒径为0.05μm)
球状二氧化硅(YC100C-SP1、ADMATECHS公司制造、平均粒径为0.1μm)
4-2.无机填料(B)
球状二氧化硅(SE1050-SPJ、ADMATECHS公司制造、平均粒径为0.3μm)
球状二氧化硅(SE2050-SPJ、ADMATECHS公司制造、平均粒径为0.5μm)
(2)最低熔融粘度和140℃的触变指数的测定
对于得到的粘接膜，使用流变仪(REOLOGICA公司制造的STRESSTECH)在样品厚度为600μm、应变控制为(1rad)、频率为10Hz、升温速度为20℃/min的条件下，在测定温度范围60℃至300℃进行测定，从而求出从常温至焊料熔点为止的温度区域中的最低复粘度η＊min，将其作为最低熔融粘度。
此外，对于得到的粘接膜，使用流变仪(REOLOGICA公司制造的STRESSTECH)在样品厚度为600μm、应变控制为(1rad)、频率为1Hz或10Hz、温度为140℃的条件下进行测定，从而求出{复粘度η＊(1Hz)}/{复粘度η＊(10Hz)}的值，将其作为140℃的触变指数。
将结果示于表2、表3。
<评价>
对在实施例和比较例中得到的粘接膜进行如下评价。将结果示于表2、表3。
(1)在半导体芯片的周围突出的毛刺的长度的评价
准备硅芯片A1、A2、A3(TSV芯片，厚度为50μmt，在单面形成有φ20μm、高度为10μm的镀Ni/Au的焊盘，在另一面形成有φ20μm、高度为10μm的铜凸起，在铜凸起上形成有厚度为5μm的Sn-3.5Ag焊料层)和硅芯片B(在单面形成有φ20μm、高度为10μm的镀Ni/Au的焊盘且另一面未形成焊盘和(或)凸起的芯片)。
使用真空层压机(ATM-812M、TAKATORI公司制造)在工作台温度为80℃、真空度为100Pa·s的条件下将粘接膜层压在硅芯片A1、A2、A3的形成有具有焊料层的铜凸起的面，然后用切割机将从芯片溢出的多余的粘接膜切断而除去。
通过如下的方法制作10个虚粘接体。
使用倒装芯片焊接机(FC3000S、TORAY ENGINEERING公司制造)以工作台温度60℃、焊头温度(虚粘接温度)100℃且以20N将硅芯片A1的附着有粘接膜的面对硅芯片B进行虚粘接。接着，以相同的条件将硅芯片A2的附着有粘接膜的面对硅芯片A1的未附着粘接膜的面进行虚粘接。进而，以相同的条件将硅芯片A3的附着有粘接膜的面对硅芯片A2的未附着粘接膜的面进行虚粘接。由此，制作了在硅芯片B的形成有焊盘的一面侧经由粘接膜层叠有3层硅芯片A1、A2、A3的虚粘接体。另外，在该时间点每个硅芯片的具有焊料层的铜凸起尚未进行焊料接合。
接下来，在大气压下用以下的温度条件对10个虚粘接体进行加热而对每个硅芯片的具有焊料层的铜凸起进行焊料接合。另外，以20N的荷重进行。然后，在170℃加热30分钟，使粘接膜完全固化，从而得到10个半导体装置。
(温度条件)
1.在100℃加热5秒钟
2.在5秒钟从100℃升温至280℃
3.在280℃维持5秒钟
4.在5秒钟从280℃降温至100℃
用光学显微镜将得到的10个半导体装置放大300倍，对处于观察视野内的半导体装置分别从上开始拍摄照片。注视得到的每张照片，对每个半导体装置选出在硅芯片的周围突出的毛刺的长度最长的部分并测定该长度(毛刺的最大长度)。对10个半导体装置求出毛刺的最大长度的平均值，将平均值为100μm以下的评价为○，将平均值超过100μm的评价为×。另外，在测定毛刺的最大长度时，测定从毛刺延伸的根部的半导体芯片的端部起到毛刺离半导体芯片的端部最远的部分的长度。
(2)贯通电极的接合形状
对在上述(1)中得到的半导体装置进行截面抛光(X-section)，通过扫描型电子显微镜(SEM)(倍率：3000倍)观察抛光面，评价凸起的接合形状。将荷重为20N时接合形状没有缩颈的评价为◎，将荷重为40N时形状没有缩颈的评价为○，将荷重为40N时接合形状存在缩颈的评价为△，将荷重为40N时在凸起间存在间隙的评价为×。
(3)空隙
对在上述(1)中得到的半导体装置进行平面抛光，通过光学显微镜观察抛光面，评价凸起间以及面内的空隙。将无论是凸起间还是面内均没有空隙的评价为○，将凸起间没有空隙但面内存在空隙的评价为△，将无论是凸起间还是面内均存在空隙的评价为×。
[表1]
[表2]
[表3]
产业上的可利用性
根据本发明，能够提供一种用于在半导体晶片上层叠多个带贯通电极的半导体芯片的、能够在抑制空隙的同时良好地连接贯通电极且能够抑制在半导体芯片的周围突出的毛刺的长度的带贯通电极的半导体芯片用粘接膜。
附图标记说明
1：本发明的带贯通电极的半导体芯片用粘接膜；
2：带贯通电极的半导体芯片；
3：半导体晶片；
4：切割刀；
5：毛刺。

Claims (4)

1.一种带贯通电极的半导体芯片用粘接膜，用于在半导体晶片上层叠多个带贯通电极的半导体芯片，该带贯通电极的半导体芯片用粘接膜的特征在于，
最低熔融粘度为50～2500Pa·s，且140℃的触变指数为8以下。
2.根据权利要求1所述的带贯通电极的半导体芯片用粘接膜，其特征在于，
含有平均粒径为10～100nm的无机填料A和平均粒径为150～500nm的无机填料B。
3.根据权利要求2所述的带贯通电极的半导体芯片用粘接膜，其特征在于，
无机填料A的含量为10～40重量％，无机填料B的含量为10～50重量％。
4.根据权利要求1、2或3所述的带贯通电极的半导体芯片用粘接膜，其特征在于，
所述带贯通电极的半导体芯片用粘接膜使用如下的树脂组合物进行制造，该树脂组合物通过将使所述无机填料悬浮在溶剂中的无机填料悬浮液分多次添加到含有平均粒径为10～100nm的无机填料A、平均粒径为150～500nm的无机填料B、或者平均粒径为10～100nm的无机填料A和平均粒径为150～500nm的无机填料B这两者、且混合所述无机填料以外的成分而得到的混合物中的方法而得到。
CN201580020776.2A 2014-04-22 2015-03-25 带贯通电极的半导体芯片用粘接膜 Pending CN106233463A (zh)

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