CN106206612A - 阵列基板的制作方法及显示面板、显示装置 - Google Patents

阵列基板的制作方法及显示面板、显示装置 Download PDF

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CN106206612A
CN106206612A CN201610696449.5A CN201610696449A CN106206612A CN 106206612 A CN106206612 A CN 106206612A CN 201610696449 A CN201610696449 A CN 201610696449A CN 106206612 A CN106206612 A CN 106206612A
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semiconductor layer
dielectric layer
middle dielectric
carried out
plasma bombardment
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陈江博
杜建华
王国英
刘威
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BOE Technology Group Co Ltd
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Priority to US15/737,277 priority patent/US10644162B2/en
Priority to PCT/CN2017/096775 priority patent/WO2018033011A1/zh
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Abstract

本发明提供了阵列基板的制作方法及显示面板、显示装置，用以通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，从而提高了电子载流子的浓度，降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流。所述方法包括：在衬底基板上依次形成半导体层、栅极绝缘层、栅极以及中间介质层；对所述中间介质层进行过孔刻蚀直至露出部分所述半导体层；对所述过孔内露出的部分半导体层进行等离子轰击；在所述中间介质层上形成通过所述过孔与所述半导体层相连的源漏电极。

Description

阵列基板的制作方法及显示面板、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及阵列基板的制作方法及显示面板、显示装置。
背景技术
氧化物晶体管技术作为现阶段的一个技术热点，具有迁移率高、均匀性好等特点。然而，在制作包括氧化物晶体管的阵列基板时，会对中间介质层进行干刻形成用于连接半导体层的过孔，形成通过该过孔与半导体层相连的源漏极。目前改善源漏极与半导体层接触产生的电阻的方式主要有以下几种，其一为改变过孔的大小；其二为改变过孔的形状；其三为增加过孔的数量；其四为在所述半导体层上插入一层过渡层；其五为更换源漏极的材料。
然而，对于阵列基板中过孔的设计方案已确定的情况，均无法通过上述前三种方法改善；插入过渡层的方法不仅将增大良率的风险，也会相应的提高生产成本；更换源漏极的材料的改善方法，对于中大尺寸的AMOLED驱动的显示装置，走线一般选用铝Al或铜Cu，因此可供选择更换的材料非常少。因此，现有技术并无法针对过孔的设计方案与源漏极的材料均已确定的情况下，源漏极与半导体层接触产生的电阻进行改善。
综上所述，现有技术并无法针对过孔的设计方案与源漏极的材料均已确定的情况下，源漏极与半导体层接触产生的电阻进行改善。
发明内容
本发明实施例提供了阵列基板的制作方法及显示面板、显示装置，用以通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流；仅在干刻时进行等离子轰击工艺，操作工艺简单。
本发明实施例提供的一种阵列基板的制作方法，包括：
在衬底基板上依次形成半导体层、栅极绝缘层、栅极以及中间介质层；
对所述中间介质层进行过孔刻蚀直至露出部分所述半导体层；
对所述过孔内露出的部分半导体层进行等离子轰击；
在所述中间介质层上形成通过所述过孔与所述半导体层相连的源漏电极。
本发明实施例中，通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，从而降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流。
较佳地，形成所述半导体层的材料为根据预设的接触电阻确定的，其中，所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。
本发明实施例中，可通过采用含氧量低的材料来形成半导体层，从而进一步实现降低源漏极与半导体层接触产生的电阻。
较佳地，对所述过孔内露出的部分半导体层进行等离子轰击工艺的时间、等离子轰击工艺的流量均与接触电阻呈负相关，其中，所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。
本发明实施例中，可通过延长等离子轰击的时间，增大等离子轰击工艺的流量，增加等离子轰击工艺的强度，从而进一步实现降低源漏极与半导体层接触产生的电阻。
较佳地，所述等离子轰击工艺的气体为氦气、氮气、氨气或氢气。
本发明实施例中，若等离子轰击工艺为氦气等离子轰击，则氦气等离子轰击自由基将不会扩散到沟道区，等离子轰击后等离子轰击自由基在半导体层中的扩散问题会大大减弱，从而进一步实现降低源漏极与半导体层接触产生的电阻。
较佳地，对所述中间介质层进行干刻工艺，包括：通过四氟化碳和氧气对所述中间介质层进行干刻工艺。
较佳地，形成的所述中间介质层的厚度大于或等于100纳米且小于或等于500纳米。
较佳地，在形成栅极之后，在形成中间介质层之前，该方法还包括：对所述半导体层中未被覆盖的区域进行等离子轰击工艺。
本发明实施例提供的一种显示面板，包括：通过上述的方法制作的阵列基板。
本发明实施例中，通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，从而降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流。
本发明实施例提供的一种显示装置，包括：上述的显示面板。
本发明实施例中，通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，从而降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流。
附图说明
图1为本发明实施例提供的一种阵列基板的制作方法的流程示意图；
图2为本发明实施例提供的阵列基板在制备过程中形成栅极金属层后的结构示意图；
图3为本发明实施例提供的阵列基板在制备过程中对中间介质层过刻后的结构示意图；
图4为本发明实施例提供的一种阵列基板的结构示意图。
具体实施方式
本发明实施例提供了阵列基板的制作方法及显示面板、显示装置，用以通过在即将完成对中间介质层进行干刻工艺时，通过过孔对半导体层露出的区域进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流；仅在干刻时进行等离子轰击工艺，操作工艺简单。
下面将结合本发明实施例中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1，本发明实施例提供了一种阵列基板的制作方法，该方法包括：
S101、在衬底基板上依次形成半导体层、栅极绝缘层、栅极以及中间介质层；
S102、对所述中间介质层进行过孔刻蚀直至露出部分所述半导体层；
S103、对所述过孔内露出的部分半导体层进行等离子轰击；
S104、在所述中间介质层上形成通过所述过孔与所述半导体层相连的源漏电极。
具体地，参见图2，步骤S101，包括：
对衬底基板(Glass)201通过标准方法进行清洗，其中，所述衬底基板为玻璃衬底；
在所述衬底基板201上，通过溅镀法(Sputter)或蒸镀法沉积遮光金属层(ShieldLayer)202，并根据需要进行图像化，其中，所述遮光层的厚度为大于或等于50纳米且小于或等于400纳米；
在形成的遮光金属层202上，利用等离子体增强化学气相沉积法(PlasmaEnhanced Chemical Vapor Deposition，PECVD)工艺制备过渡层(Buffer Layer)203，其中，所述过渡层的厚度为大于或等于100纳米且小于或等于500纳米；
在形成的过渡层203上，利用溅镀法(Sputter)工艺沉积半导体层(ActiveLayer)，并根据需要进行图像化，其中，所述半导体层的厚度为大于或等于10纳米且小于或等于100纳米；
在形成的半导体层上，利用等离子体增强化学气相沉积法PECVD工艺制备栅极绝缘层205，其中，所述栅极绝缘层的厚度为大于或等于100纳米且小于或等于500纳米，制备栅极绝缘层的材料为氧化硅SiOx；
在形成的栅极绝缘层205上，通过溅镀法(Sputter)或蒸镀法沉积栅极金属层206，并根据需要进行图像化，其中，所述栅极金属层的厚度为大于或等于50纳米且小于或等于400纳米；
对栅极绝缘层205与栅极金属层206直接进行干法刻蚀工艺，不用另行曝光；并对半导体层的裸露区域进行等离子轰击处理，从而得到等离子轰击后的半导体区域2041和未被等离子轰击的半导体区域2042。
其中，进行半导体层沉积时，氧气的流量与氧气和氩气流量的总和的比值的范围为0％～50％，此时沉积得到的半导体层的厚度范围为2纳米～200纳米。具体地，当氧气的流量与氧气和氩气流量的总和的比值为5％时，沉积得到的半导体层最佳，即沉积得到的半导体层的厚度为40纳米。
此外，沉积得到的半导体层的厚度与沉积成膜的设备的腔体的压强、功率，以及沉积扫描的次数相关。当沉积成膜的设备的腔体的压强为0.63帕(Pa)，设备的功率为4500瓦(W)，且沉积扫描的次数为5次，氩气流量设定为100毫升每分钟(SCCM)，氧气流量设定为0.13毫升每分钟(SCCM)时，半导体层的厚度为40纳米，即最佳厚度。其中，沉积成膜的设备的腔体的压强的范围为0.01帕～100帕，设备的功率的范围为1千瓦～10千瓦，沉积扫描的次数的范围为1次～30次，设定氩气流量的范围为0毫升每分钟～500毫升每分钟，设定氧气流量的范围为0毫升每分钟～500毫升每分钟，且上述参数均与沉积成膜的设备相关。
参见图3，步骤S102，包括：
在所述栅极金属层206上，利用等离子体增强化学气相沉积法PECVD工艺制备形成中间介质层207(Inter-Layer Insulators，ILD)，并根据需要曝光进行图像化，其中，所述中间介质层的厚度为大于或等于100纳米且小于或等于500纳米，制备中间介质层的材料为氧化硅SiOx；
在对中间介质层曝光结束后，采用四氟化碳和氧气对中间介质层进行干刻(DryEtch，D/E)工艺处理，直至露出部分所述半导体层，形成过孔208。
在形成过孔208后，通过所述过孔内露出的部分半导体层进行等离子轰击工艺，即执行步骤S103。其中，所述等离子轰击工艺为氦气(He)等离子轰击或氮气(N2)等离子轰击或氨气(NH3)等离子轰击或氢气(H2)等离子轰击。
然而，由于对中间介质层进行干刻，有可能会对中间介质层207产生过刻，即在形成过孔208的过程中，刻蚀到等离子轰击后的半导体区域2041，即圆圈301处，具体可参见图3。此时，通过过孔208对半导体区域2041的过刻区域301进行等离子轰击工艺。
参见图4，步骤S104，包括：
在中间介质层207上，通过溅镀法(Sputter)沉积得到源漏极209，并根据需要进行图像化，其中，所述源漏极的厚度为大于或等于50纳米且小于或等于400纳米。
在步骤S103之后，该方法还包括：
在源漏极209上，利用等离子体增强化学气相沉积法PECVD工艺制备形成钝化层210(Passivation Layer，PVX)，并根据需要进行图像化，其中，所述钝化层的厚度为大于或等于200纳米且小于或等于400纳米，制备钝化层的材料为氧化硅SiOx或者氮化硅SiNx。
为便于理解，下面将通过实施例进一步对本发明的方案进行解释。
假设用于制备半导体层的材料为非晶体InGaZnO。具体实验数据参见表1；
表1
其中，Plasma treatment为等离子轰击工艺；Different为具体操作条件；Slot为实验编号；Avg.为接触电阻的平均值；Max为接触电阻的最大值；Min为接触电阻的最小值；Uniformity为均一性，用于表示工艺步骤的稳定性；3σ为实验数据的导出值；CF4+O2为采用四氟化碳和氧气对中间介质层进行干刻处理；OE 30s为通过干刻工艺处理30秒；He为采用氦气等离子轰击工艺对过孔内露出的部分半导体层进行处理；InGaZnO 20％10s为对半导体层进行氦气等离子轰击工艺10秒，其中，该半导体层的材料为含氧量为20％的非晶体InGaZnO。
若在对中间介质层曝光结束后，只采用四氟化碳和氧气对中间介质层进行干刻处理30秒，即对半导体区域2041产生过刻，此时源漏极209与过刻区域301的接触电阻大于或等于15570欧姆，且小于或等于16410欧姆；接触电阻的平均值为16064欧姆；
若进行干刻处理30秒后，通过过孔208对过孔内露出的部分半导体进行氦气等离子轰击处理10秒，此时源漏极209与过刻区域301的接触电阻大于或等于1425欧姆，且小于或等于1494欧姆；接触电阻的平均值为1460欧姆。
由此可知，通过对过孔内露出的部分半导体进行氦气等离子轰击处理后的接触电阻相比未处理的接触电阻成数量级的减小，从而增大了晶体管的开态电流。
针对同一的半导体，若通过过孔208对过孔内露出的部分半导体进行氦气等离子轰击处理30秒，此时源漏极209与过刻区域301的接触电阻大于或等于997欧姆，且小于或等于1078欧姆；接触电阻的平均值为1026欧姆；
由此可知，对所述半导体层通过过孔露出的区域进行等离子轰击工艺的时间与接触电阻在一定范围内负相关，其中，等离子轰击工艺的时间的范围为0秒～300秒；所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。当对过孔内露出的部分半导体层进行等离子轰击工艺的时间40秒时等离子轰击工艺的效果最佳，即经过等离子轰击工艺后，源漏极与半导体层接触产生的电阻最小。
若同样采用干刻处理30秒，且同样通过过孔对过孔内露出的部分半导体进行氦气等离子轰击处理30秒，但用于制备半导体层的非晶体InGaZnO的含氧量不同，源漏极209与过刻区域301的接触电阻也将不同；实验证明，当非晶体InGaZnO的含氧量为20％时，接触电阻大于或等于997欧姆，且小于或等于1078欧姆；接触电阻的平均值为1026欧姆；当非晶体InGaZnO的含氧量为10％时，接触电阻大于或等于923.2欧姆，且小于或等于1038欧姆；接触电阻的平均值为963欧姆；当非晶体InGaZnO的含氧量为5％时，接触电阻大于或等于845欧姆，且小于或等于883.7欧姆；接触电阻的平均值为862欧姆。
由此可知，用于制备半导体层的非晶体InGaZnO的含氧量与接触电阻在一定范围内负相关，其中，所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。
接触电阻与等离子轰击工艺的流量在一定范围内负相关，其中，氦气等离子轰击工艺的流量范围为0毫升每分钟～500毫升每分钟。当氦气等离子轰击工艺的流量为200毫升每分钟时，源漏极与半导体层接触产生的电阻最小。
接触电阻与等离子轰击强度在一定范围内也负相关，即在一定范围内随着反应离子刻蚀的设备的腔体的压强、功率的增大，源漏极与半导体层接触产生的电阻将减小。其中，反应离子刻蚀的设备的腔体的压强范围为0毫托～1000毫托，功率范围为0瓦～1000瓦。具体地，反应离子刻蚀的设备的腔体的压强为50毫托，功率为600瓦时等离子轰击工艺的效果最佳，即经过等离子轰击工艺后，源漏极与半导体层接触产生的电阻最小。
综上，由于非晶体InGaZnO为宽禁带氧化物半导体材料，与源漏极接触产生的电阻为肖特基接触，即接触电阻较大。因此，在即将完成对中间介质层进行干刻工艺时，通过干刻产生的过孔对半导体层的过刻区域进行等离子轰击，通过等离子体的原子撞击，将非晶体InGaZnO内部的氧原子轰击出来，形成更多的氧空位缺陷，由于氧化物中氧空位缺陷是施主缺陷，由于氧空位的增多，将提高了电子载流子的浓度，从而降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流。
本发明实施例提供的一种显示面板，包括：通过上述的方法制作的阵列基板。
本发明实施例提供的一种显示装置，包括：上述的显示面板。
综上所述，本发明实施例提供了阵列基板的制作方法及显示面板、显示装置，用以通过在即将完成对中间介质层进行干刻工艺时，通过干刻产生的过孔对过孔内露出的部分半导体层进行等离子轰击，通过等离子体的原子撞击，将半导体层中的氧原子轰击出来，形成更多的氧空位缺陷，从而提高了电子载流子的浓度，降低了源漏极与半导体层接触产生的电阻，也就增大了晶体管的开态电流；仅在干刻时进行等离子轰击工艺，操作工艺简单。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

1.一种阵列基板的制作方法，其特征在于，包括：
在衬底基板上依次形成半导体层、栅极绝缘层、栅极以及中间介质层；
对所述中间介质层进行过孔刻蚀直至露出部分所述半导体层；
对所述过孔内露出的部分半导体层进行等离子轰击；
在所述中间介质层上形成通过所述过孔与所述半导体层相连的源漏电极。
2.根据权利要求1所述的方法，其特征在于，形成所述半导体层的材料为根据预设的接触电阻确定的，其中，所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。
3.根据权利要求1所述的方法，其特征在于，对所述过孔内露出的部分半导体层进行等离子轰击工艺的时间、等离子轰击工艺的流量均与接触电阻呈负相关，其中，所述接触电阻为所述源漏极与所述半导体层接触产生的电阻。
4.根据权利要求1所述的方法，其特征在于，所述等离子轰击工艺的气体为氦气、氮气、氨气或氢气。
5.根据权利要求1所述的方法，其特征在于，对所述中间介质层进行干刻工艺，包括：
通过四氟化碳和氧气对所述中间介质层进行干刻工艺。
6.根据权利要求1所述的方法，其特征在于，形成的所述中间介质层的厚度大于或等于100纳米且小于或等于500纳米。
7.根据权利要求1所述的方法，其特征在于，在形成栅极之后，在形成中间介质层之前，该方法还包括：
对所述半导体层中未被覆盖的区域进行等离子轰击工艺。
8.一种显示面板，其特征在于，包括：通过权利要求1-7任一项所述的方法制作的阵列基板。
9.一种显示装置，其特征在于，包括：权利要求8所述的显示面板。
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