CN106206521B - 打线接合的方法以及封装结构 - Google Patents

打线接合的方法以及封装结构 Download PDF

Info

Publication number
CN106206521B
CN106206521B CN201510287352.4A CN201510287352A CN106206521B CN 106206521 B CN106206521 B CN 106206521B CN 201510287352 A CN201510287352 A CN 201510287352A CN 106206521 B CN106206521 B CN 106206521B
Authority
CN
China
Prior art keywords
conducting wire
metal
connection pad
ball
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510287352.4A
Other languages
English (en)
Other versions
CN106206521A (zh
Inventor
林柏均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN106206521A publication Critical patent/CN106206521A/zh
Application granted granted Critical
Publication of CN106206521B publication Critical patent/CN106206521B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004—Wire welding
    • B23K20/005—Capillary welding
    • B23K20/007—Ball bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
    • B23K20/233—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/08—Non-ferrous metals or alloys
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/08—Non-ferrous metals or alloys
    • B23K2103/12—Copper or alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48481—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball
    • H01L2224/48482—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/78268—Discharge electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种打线接合的方法以及封装结构，该方法包括下列步骤：首先，提供基板；基板包括至少一金属垫；接着，设置第一芯片于基板上，且第一芯片包括至少一第一接垫；接着，形成金属球块于对应的金属垫上；接着，由金属球块形成第一导线至对应的第一接垫；接着，进行放电结球制程以形成第一金属熔球于第一导线上；接着，压合连接第一导线的第一金属熔球于对应的第一接垫上，以使第一导线位于第一金属熔球与对应的第一接垫之间，其制程较为简单且效率较高，且应用此打线接合方法的封装结构可满足低打线高度的需求。

Description

打线接合的方法以及封装结构
技术领域
本发明是有关于一种打线接合的方法以及封装结构。
背景技术
近代电子设备大量依赖这些装设有许多半导体芯片或集成电路(IntegratedCircuits，简称ICs)的电路板。在芯片及基板之间的机械性及电性连接不断地挑战这些芯片设计者。打线接合(wire bonding)是最常用来将集成电路及基板互连的技术之一。
一般来说，打线接合技术包括“正向打线”以及“反向打线”。正向打线是指由集成电路/元件往下打线至基板。详细而言，正向打线制程是先放置一焊球于芯片上，再通过打线装置的瓷嘴由焊球形成针脚式导线(stitch bond)至基板上的焊垫。目前较多的打线接合的应用是采用典型的正向打线，因其相较于反向打线制程所花的时间较短且较能满足细间距的需求。然而，正向打线的导线在焊球上方的颈部区域有弧高的限制，若过度的弯折焊球上方的颈部区域可能会导致颈部区域的断裂，因而导致其可靠性降低。因此，使用正向打线的封装结构较难满足低打线高度的需求。
相反的，反向接合制程是先设置凸块于芯片的接垫上。在形成凸块之后，再设置一焊球于基板上并接着形成针脚式导线至凸块。设置凸块于芯片的接垫上可产生缓冲的作用，防止形成针脚式导线时的高下压力对接垫下方的结构造成破坏。低打线高度的需求促进了反向打线的应用率的成长，然而，反向打线是一种非连续性的制程，其相较于正向打线是属于非常缓慢的制程。因此，如何在维持制程效率的情况下满足低打线高度的需求是目前业界一个非常重要的研究课题。
发明内容
本发明提供一种打线接合的方法以及封装结构。
本发明提供一种打线接合的方法，其制程较为简单且效率较高，且应用此打线接合方法的封装结构可满足低打线高度的需求。
本发明更提供一种封装结构，其可满足低打线高度的需求且制程效率较高。
本发明的打线接合的方法包括下列步骤。首先，提供基板。基板包括至少一金属垫。接着，设置第一芯片于基板上，且第一芯片包括至少一第一接垫。接着，形成金属球块于对应的金属垫上。接着，由金属球块形成第一导线至对应的第一接垫。接着，进行放电结球制程以形成第一金属熔球于第一导线上。接着，压合连接第一导线的第一金属熔球于对应的第一接垫上，以使第一导线位于第一金属熔球与对应的第一接垫之间。
本发明的封装结构包括基板、第一芯片、至少一金属球块、至少一第一导线以及至少一第一金属熔球。基板包括第一表面以及至少一金属垫。金属垫设置于第一表面。第一芯片设置于第一表面且包括第一主动表面以及至少一第一接垫。第一接垫设置于第一主动表面。金属球块分别设置于对应的金属垫上。第一导线分别连接于对应的金属球块以及对应的第一接垫之间。第一金属熔球连接至对应的第一导线且分别设置于对应的第一接垫，以使第一导线位于对应的第一金属熔球以及对应的第一接垫之间。
在本发明的一实施例中，上述的形成第一导线的方法包括将打线装置的瓷嘴由金属球块移动至对应的第一接垫，以形成第一导线。
在本发明的一实施例中，上述的放电结球制程包括将放电棒设置于第一导线，并使预设距离维持于放电棒以及第一导线之间，以于放电棒以及第一导线之间形成电弧。
在本发明的一实施例中，上述的第一导线以及第一金属熔球为一体成型。
在本发明的一实施例中，上述的打线接合的方法还包括堆叠第二芯片于第一芯片上，其中第二芯片暴露第一接垫且包括至少一第二接垫。
在本发明的一实施例中，上述的打线接合的方法还包括下列步骤。在压合连接第一导线的第一金属熔球于对应的第一接垫上之后，由对应的第一接垫形成第二导线至对应的第二接垫。接着，进行放电结球制程以形成第二金属熔球于对应的第二导线上。接着，压合连接第二导线的第二金属熔球于对应的第二接垫上，以使第二导线位于第二金属熔球以及对应的第二接垫之间。
在本发明的一实施例中，上述的形成第二导线的方法包括将打线装置的瓷嘴由对应的第一接垫移动至对应的第二接垫，以形成第二导线。
在本发明的一实施例中，上述的放电结球制程包括将放电棒设置于第二导线，并使预设距离维持于放电棒以及第二导线之间，以于放电棒以及第二导线之间形成电弧。
在本发明的一实施例中，上述的第一金属熔球以及第二导线为连续形成且一体成型。
在本发明的一实施例中，上述的第二导线以及第二金属熔球为一体成型。
在本发明的一实施例中，上述的由第一主动表面至第一导线的最高点的距离介于第一导线的直径至200微米(μm)之间。
在本发明的一实施例中，上述的封装结构还包括第二芯片。第二芯片堆叠于第一芯片的第一主动表面上并暴露第一接垫。第二芯片包括第二主动表面以及至少一第二接垫，第二接垫设置于第二主动表面上。
在本发明的一实施例中，上述的封装结构还包括至少一第二导线以及至少一第二金属熔球。第二导线分别连接于第一接垫以及第二接垫之间。第二金属熔球连接对应的第二导线且设置于对应的第二接垫上，以使第二导线位于对应的第二金属熔球以及对应的第二接垫之间。
在本发明的一实施例中，上述的第一金属熔球以及连接至第一金属熔球的第二导线为连续形成且一体成型。
在本发明的一实施例中，上述的由第二主动表面至第二导线的最高点的距离介于第二导线的直径至200微米之间。
基于上述，金属熔球是通过放电结球制程而形成于导线上，再被压合于芯片的接垫上，以使导线位于金属熔球以及接垫之间。依上述的打线接合制程，封装结构的打线接合可连续进行而不需先置放凸块于芯片的接垫上再设置金属球块于基板的金属垫上，因而可简化封装结构的制作流程，进而可加速封装结构的打线接合制程。
此外，由于导线的最高点紧邻基板的金属垫，本发明的打线接合制程将金属垫设为较低的打线平面，因而可降低打线的整体高度。并且，由于导线是位于金属熔球以及接垫之间，而非设置于金属熔球上，打线的整体高度可进一步降低。因此，打线接合的方法以及应用此打线接合方法封装结构不仅可满足低打线高度的需求，还可增进打线接合制程的效率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1H是依照本发明的一实施例的一种打线接合的制作流程示意图；
图2至图3是依照本发明的一实施例的一种形成金属熔球于导线上的制作流程示意图；
图4是图1F的封装结构的局部放大示意图。
附图标记说明：
10：瓷嘴；
20：放电棒；
100：封装结构；
110：基板；
112：第一表面；
114：金属垫；
120：第一芯片；
122：第一主动表面；
124：第一接垫；
125：黏着材料；
130：金属球块；
140：第一导线；
150：第一金属熔球；
160：第二芯片；
162：第二主动表面；
164：第二接垫；
170：第二导线；
180：第二金属熔球；
190：第三芯片；
192：第三金属熔球；
194：第三接垫；
196：第三导线；
D1：距离。
具体实施方式
有关本发明的前述及其他技术内容、特点与功效，在以下配合附图的各实施例的详细说明中，将可清楚的呈现。以下实施例中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本发明。并且，在下列各实施例中，相同或相似的元件将采用相同或相似的标号。
图1A至图1H是依照本发明的一实施例的一种打线接合的制作流程示意图。在本实施例中，打线接合的方法包括下列步骤。首先，请参照图1A，提供基板110，基板110可包括第一表面112以及至少一金属垫114。须说明的是，本实施例示出了多个金属垫114，但本发明并不限制金属垫114的数量。金属垫114设置于第一表面112上。并且，第一芯片120设置于基板110上。在本实施例中，第一芯片120通过黏着材料125贴附于基板110上，当然，本发明并不以此为限。第一芯片120可包括第一主动表面122以及至少一第一接垫124。须注意的是，本实施例示出了多个第一接垫124，但本发明并不限制第一接垫124的数量。第一接垫124设置于第一主动表面122。当然，本实施例仅用以举例说明，在其他实施例中，其他的芯片可再堆叠于第一芯片120上。本发明并不限制堆叠于基板110上的芯片的数量。
请参照图1B，在本实施例中，堆叠第二芯片160于第一芯片120上，并堆叠第三芯片190于第二芯片160上。第二芯片160暴露第一接垫124并包括第二主动表面162以及至少一第二接垫164。第二接垫164设置于第二主动表面162上。第三芯片190暴露第一接垫124及第二接垫164，并包括至少一第三接垫194。接着，金属球块130设置于基板110的金属垫114的其中之一上。金属球块130可例如通过热能或超音波等方法而接合于金属垫114上。当然，本发明并不以此为限。
请参照图1C以及图1D，从金属球块130形成第一导线140至第一接垫124的其中之一。具体来说，将打线装置的瓷嘴10由金属球块130移动至上述的第一接垫124，以形成第一导线140。接着，进行放电结球制程(electronic flame-off process,简称EFO)以形成第一金属熔球150于第一导线140上。更详细的放电结球的制程将描述如下。
图2至图3是依照本发明的一实施例的一种形成金属熔球于导线上的制作流程示意图。请参照图2以及图3，第一金属熔球150是通过放电结球制程来电离气隙(air gap)而形成。在放电结球的过程中，电热释放会发生在两电极之间，其中，一电极可为第一导线140，其典型的材料可为铜或金(阳极)，而另一电极则可为放电棒20(阴极)。具体而言，第一金属熔球150的形成方法可如图2所示将放电棒20设置于第一导线140，并使预设距离维持在放电棒20以及第一导线140之间，以在放电棒20以及第一导线140之间形成电弧。据此，在放电过程中，放电棒20所产生的热会使第一导线140熔化，而熔融态金属的表面张力会使金属凝聚成球状。当足够量的金属(即，第一导线140)熔化后，放电制程即结束以形成如图3所示的金属熔球150于第一导线140上。如此，第一导线140以及第一金属熔球150为一体成型。本实施例可通过改变电弧的强度以及持续时间来调整所形成的第一金属熔球150的大小至特定的尺寸。
请参照图1E以及图1F，接着，将连接第一导线140的第一金属熔球150压合至第一接垫124的其中之一上(第一金属熔球150冷却而形成金属球块于上述的第一接垫124)，以使第一导线140位于第一金属熔球150以及上述的第一接垫124。接着，可重复图1C至图1F所示的制程步骤以连续地对第二芯片160以及第三芯片190进行打线。详细而言，请参照图1G，从前述的第一接垫124形成第二导线170至第二接垫164的其中之一。更具体来说，瓷嘴10如图1G所示从第一接垫124移动至第二接垫164，以形成第二导线170。接着，通过相同于前述的放电结球制程来形成第二金属熔球180于第二导线170上。接着，将连接第二导线170的第二金属熔球180压合于第二接垫164上，以使第二导线170位于第二金属熔球180以及第二接垫164之间。请参照图1H，通过相似的制程，形成连接第三导线196的第三金属熔球192于第三接垫194上，以使第三导线196位于第三金属熔球192以及第三接垫194之间。如此，第一金属熔球150以及第二导线170为连续形成且一体成型，且第二导线170以及第二金属熔球180为一体成型。
图4是图1F的封装结构的局部放大示意图。请参照图1H以及图4，依据上述的打线接合方法即可形成如图1H以及图4所示的封装结构100。在本实施例中，封装结构100包括基板110、第一芯片120、至少一金属球块130、至少一第一导线140以及至少一第一金属熔球150。基板110包括第一表面112以及至少一金属垫114，金属垫114设置于第一表面112上。第一芯片120设置于第一表面112且包括第一主动表面122以及至少一第一接垫124，第一接垫124设置于第一主动表面122。金属球块130分别设置于对应的金属垫114上。第一导线140分别连接于对应的金属球块130以及对应的第一接垫124。第一金属熔球150连接对应的第一导线140且分别设置于对应的第一接垫124上，以使第一导线140位于对应的第一金属熔球124以及对应的第一接垫124之间。如此配置，由于打线的最高点紧邻金属垫114，因而可降低第一导线140的整体高度。在本实施例中，由第一主动表面122至各第一导线140的最高点的距离D1约可介于第一导线140的直径至200微米(μm)之间。
此外，封装结构100还可包括第二芯片160、至少一第二导线170以及至少一第二金属熔球180。第二芯片160如图1H所示可堆叠于第一芯片120的第一主动表面122上并暴露第一接垫124。第二芯片160如图1B所示包括至少一第二接垫164，其设置于第二主动表面162。第二导线170连接于对应的第一接垫124以及对应的第二接垫164之间。连接对应的第二导线170的第二金属熔球180分别设置于对应的第二接垫164上，以使第二导线170位于第二金属熔球180以及对应的第二接垫164之间。第二导线的整体高度也可因此降低。在本实施例中，由第二主动表面162至第二导线170的最高点的距离约可介于第二导线170的直径至200微米之间。
综上所述，本发明的金属熔球是通过放电结球制程而形成于导线上，再被压合于芯片的接垫上，以使导线位于金属熔球以及接垫之间。依上述的打线接合制程，封装结构的打线接合可连续进行而不需先置放凸块于接垫上，再设置金属球块于基板的金属垫上，因而可简化封装结构的制作流程，进而可加速封装结构的打线接合制程。
此外，由于导线的最高点紧邻基板的金属垫，本发明的打线接合制程将金属垫设定为较低的打线平面，因而可降低打线的整体高度。并且，由于导线是位于金属熔球以及接垫之间，而非设置于金属熔球上，打线的整体高度更可进一步降低。因此，打线接合的方法以及应用此打线接合方法的封装结构不仅可满足低打线高度的需求，还可增进打线接合制程的效率。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (17)

1.一种反向打线接合的方法，其特征在于，包括：
提供基板，所述基板包括至少一金属垫；
设置第一芯片于所述基板上，且所述第一芯片包括至少一第一接垫；
形成金属球块于对应的金属垫上；
由所述金属球块形成第一导线至对应的第一接垫；
进行放电结球制程以形成第一金属熔球于所述第一导线上；以及
压合连接所述第一导线的所述第一金属熔球于对应的第一接垫上，以使所述第一导线位于所述第一金属熔球与对应的第一接垫之间。
2.根据权利要求1所述的反向打线接合的方法，其特征在于，形成所述第一导线的方法包括：
将打线装置的瓷嘴由所述金属球块移动至对应的第一接垫，以形成所述第一导线。
3.根据权利要求1所述的反向打线接合的方法，其特征在于，所述放电结球制程包括：
将放电棒设置于所述第一导线，并使预设距离维持在所述放电棒以及所述第一导线之间，以在所述放电棒以及所述第一导线之间形成电弧。
4.根据权利要求1所述的反向打线接合的方法，其特征在于，所述第一导线以及所述第一金属熔球为一体成型。
5.根据权利要求1所述的反向打线接合的方法，其特征在于，还包括：
堆叠第二芯片于所述第一芯片上，其中所述第二芯片暴露所述第一接垫且包括至少一第二接垫。
6.根据权利要求5所述的反向打线接合的方法，其特征在于，还包括：
在压合连接所述第一导线的所述第一金属熔球于对应的第一接垫上之后，由对应的第一接垫形成第二导线至对应的第二接垫；
进行放电结球制程以形成第二金属熔球于对应的第二导线上；以及
压合连接所述第二导线的所述第二金属熔球于对应的第二接垫上，以使所述第二导线位于所述第二金属熔球以及对应的第二接垫之间。
7.根据权利要求6所述的反向打线接合的方法，其特征在于，形成所述第二导线的方法包括：
将打线装置的瓷嘴由对应的第一接垫移动至对应的第二接垫，以形成所述第二导线。
8.根据权利要求6所述的反向打线接合的方法，其特征在于，所述放电结球制程包括：
将放电棒设置于所述第二导线，并使预设距离维持在所述放电棒以及所述第二导线之间，以在所述放电棒以及所述第二导线之间形成电弧。
9.根据权利要求6所述的反向打线接合的方法，其特征在于，所述第一金属熔球以及所述第二导线为连续形成且一体成型。
10.根据权利要求6所述的反向打线接合的方法，其特征在于，所述第二导线以及所述第二金属熔球为一体成型。
11.一种封装结构，其特征在于，包括：
基板，包括第一表面以及至少一金属垫，所述金属垫设置于所述第一表面；
第一芯片，设置于所述第一表面且包括第一主动表面以及至少一第一接垫，所述第一接垫设置于所述第一主动表面；
至少一金属球块，分别设置于对应的金属垫上；
至少一第一导线，分别连接于对应的金属球块以及对应的第一接垫之间；以及
至少一第一金属熔球，连接至对应的第一导线且分别设置于对应的第一接垫，以使所述第一导线位于对应的第一金属熔球以及对应的第一接垫之间，所述第一导线以及连接至所述第一导线的所述第一金属熔球为一体成型。
12.根据权利要求11所述的封装结构，其特征在于，由所述第一主动表面至所述第一导线的最高点的距离介于所述第一导线的直径至200微米之间。
13.根据权利要求11所述的封装结构，其特征在于，还包括：
第二芯片，堆叠于所述第一芯片的所述第一主动表面上并暴露所述第一接垫，所述第二芯片包括第二主动表面以及至少一第二接垫，所述第二接垫设置于所述第二主动表面上。
14.根据权利要求13所述的封装结构，其特征在于，还包括：
至少一第二导线，分别连接于所述第一接垫以及所述第二接垫之间；以及
至少一第二金属熔球，连接对应的第二导线且设置于对应的第二接垫上，以使所述第二导线位于对应的第二金属熔球以及对应的第二接垫之间。
15.根据权利要求14所述的封装结构，其特征在于，所述第一金属熔球以及连接至所述第一金属熔球的所述第二导线为连续形成且一体成型。
16.根据权利要求14所述的封装结构，其特征在于，所述第二导线以及连接所述第二导线的所述第二金属熔球为一体成型。
17.根据权利要求14所述的封装结构，其特征在于，由所述第二主动表面至所述第二导线的最高点的距离介于所述第二导线的直径至200微米之间。
CN201510287352.4A 2015-02-12 2015-05-29 打线接合的方法以及封装结构 Active CN106206521B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/620,947 US9362254B1 (en) 2015-02-12 2015-02-12 Wire bonding method and chip structure
US14/620,947 2015-02-12

Publications (2)

Publication Number Publication Date
CN106206521A CN106206521A (zh) 2016-12-07
CN106206521B true CN106206521B (zh) 2018-11-30

Family

ID=56083224

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510287352.4A Active CN106206521B (zh) 2015-02-12 2015-05-29 打线接合的方法以及封装结构

Country Status (3)

Country Link
US (2) US9362254B1 (zh)
CN (1) CN106206521B (zh)
TW (1) TWI635548B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10324097B2 (en) 2017-08-30 2019-06-18 NeoLight LLC System and methods for bilirubin analysis
CN109872982A (zh) * 2019-03-08 2019-06-11 东莞记忆存储科技有限公司 半导体多层晶粒堆叠模块及其焊接方法
CN110444522B (zh) * 2019-08-16 2022-03-18 四川九洲电器集团有限责任公司 一种芯片的制备方法及芯片
CN112652549A (zh) * 2019-10-10 2021-04-13 中芯长电半导体（江阴）有限公司 垂直打线设备及打线方法
TWI825829B (zh) * 2022-05-12 2023-12-11 南亞科技股份有限公司 具有電氣連接基底之半導體元件的製備方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247589A (zh) * 2012-02-08 2013-08-14 三星电子株式会社 半导体封装件和制造半导体封装件的方法
WO2014063281A1 (en) * 2012-10-22 2014-05-01 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including stacked bumps for emi/rfi shielding
CN104078439A (zh) * 2013-03-25 2014-10-01 株式会社东芝 半导体装置及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5735030A (en) * 1996-06-04 1998-04-07 Texas Instruments Incorporated Low loop wire bonding
JP2002280414A (ja) * 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7021520B2 (en) * 2001-12-05 2006-04-04 Micron Technology, Inc. Stacked chip connection using stand off stitch bonding
JP2008034567A (ja) * 2006-07-27 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法
US20080265385A1 (en) * 2007-04-11 2008-10-30 Siliconware Precision Industries Co., Ltd. Semiconductor package using copper wires and wire bonding method for the same
US8722457B2 (en) * 2007-12-27 2014-05-13 Stats Chippac, Ltd. System and apparatus for wafer level integration of components
CN101971313B (zh) * 2008-01-30 2013-07-24 库力索法工业公司 导线环以及形成导线环的方法
JP2010177456A (ja) * 2009-01-29 2010-08-12 Toshiba Corp 半導体デバイス
US8096461B2 (en) * 2009-09-03 2012-01-17 Advanced Semiconductor Engineering, Inc. Wire-bonding machine with cover-gas supply device
US8610271B2 (en) * 2009-11-30 2013-12-17 Baw-Ching Perng Chip package and manufacturing method thereof
CN103107111B (zh) * 2011-11-11 2017-03-01 飞思卡尔半导体公司 用于监测线接合中无空气球（fab）形成的方法和装置
US20140263584A1 (en) * 2013-03-12 2014-09-18 Jia Lin Yap Wire bonding apparatus and method
JP6125332B2 (ja) * 2013-05-31 2017-05-10 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247589A (zh) * 2012-02-08 2013-08-14 三星电子株式会社 半导体封装件和制造半导体封装件的方法
WO2014063281A1 (en) * 2012-10-22 2014-05-01 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including stacked bumps for emi/rfi shielding
CN104078439A (zh) * 2013-03-25 2014-10-01 株式会社东芝 半导体装置及其制造方法

Also Published As

Publication number Publication date
TWI635548B (zh) 2018-09-11
CN106206521A (zh) 2016-12-07
US9362254B1 (en) 2016-06-07
US20160247777A1 (en) 2016-08-25
US9508673B2 (en) 2016-11-29
TW201630091A (zh) 2016-08-16

Similar Documents

Publication Publication Date Title
CN106206521B (zh) 打线接合的方法以及封装结构
US6455785B1 (en) Bump connection with stacked metal balls
US4814855A (en) Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape
TWI538762B (zh) 銲球凸塊與封裝結構及其形成方法
JP6088950B2 (ja) スタッドバンプ構造およびその製造方法
JP2000200859A (ja) チップサイズ半導体パッケ―ジ及びその集合体並びにその製造方法
JP2010251483A (ja) 半導体装置およびその製造方法
TW201140765A (en) Microelectronic assembly with joined bond elements having lowered inductance
CN207781646U (zh) 一种led芯片倒装焊接结构和led灯珠
US6874673B2 (en) Initial ball forming method for wire bonding wire and wire bonding apparatus
JP2737953B2 (ja) 金バンプ用金合金細線
US20190221538A1 (en) Semiconductor structure
JP2012160554A (ja) ボンディングワイヤの接合構造及び接合方法
TW201545173A (zh) 異向性導電接著劑
TWI358337B (en) Method and device of continuously wire-bonding bet
JP4560644B2 (ja) はんだ引けを改善した半導体基板用放熱板
JP2007281509A (ja) 半導体装置
US9799624B1 (en) Wire bonding method and wire bonding structure
JP2010225892A (ja) 半導体装置及びその製造方法、並びに電子機器
JP2018195673A (ja) バンプ及びその形成方法、並びに基板
CN105870268A (zh) 一种基于镀金线的led封装工艺方法
US20100148364A1 (en) Semiconductor device and method for producing semiconductor device
JP2004221258A (ja) 半導体装置及びその製造方法
KR20240033887A (ko) 접속핀의 접속방법
CN116666228A (zh) 一种功率芯片混合凸点的结构、制作方法及半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant