JP4560644B2 - はんだ引けを改善した半導体基板用放熱板 - Google Patents
はんだ引けを改善した半導体基板用放熱板 Download PDFInfo
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- JP4560644B2 JP4560644B2 JP2005234526A JP2005234526A JP4560644B2 JP 4560644 B2 JP4560644 B2 JP 4560644B2 JP 2005234526 A JP2005234526 A JP 2005234526A JP 2005234526 A JP2005234526 A JP 2005234526A JP 4560644 B2 JP4560644 B2 JP 4560644B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
下記(2)式および(3)式を満たすように高さの異なる突起を設けたことを特徴とする半導体基板用放熱板が提供される。特に、下記基板Aを下記(4)式を満たすように搭載する放熱板が好適な対象となる。
1000≦R≦10000 ……(1)
3×10-4≦(h1−h2)/LP≦5×10-3 ……(2)
1×10-6≦(h1−h2)/R≦5×10-5 ……(3)
2≦X≦10 ……(4)
ただし、並設する複数の半導体基板のうち一方の端に位置するものを基板A、その隣のものを基板Bと呼び、基板Aを載せたときに接する突起のうち、基板Bと反対側の端に位置するものを突起P1、基板B側の端に位置するものを突起P2と呼び、半導体基板を搭載する面を上にして水平面上に置いたときの鉛直方向に平行で、かつ突起P1と突起P2の先端を通る断面を断面Zと呼ぶとき、
R:断面Zにおける板厚中心部の曲率半径(mm)、
h1およびh2:それぞれ突起P1およびP2の突起高さ(mm)、
LP:突起P1とP2の先端距離(mm)
X:断面Zにおいて基板Aのはんだと接触する部位の突起P1側の端部と突起P1先端との距離(mm)、すなわち周縁部の長さ、
である。
1000≦R≦10000 ……(1)
1000≦R≦7000 ……(1)'
曲率半径Rが1000mmより小さい場合は、Pbフリーはんだ使用時に生じる反り量がキャンセルされても、なお半導体基板搭載面側が凹となる反りが残ってしまう。一方、Rが10000mmを超えるとPbフリーはんだ使用時の反りを十分軽減することが難しくなる。Rは7000mm以下とすることが好ましい。
3×10-4≦(h1−h2)/LP≦5×10-3 ……(2)
5×10-4≦(h1−h2)/LP≦3×10-3 ……(2)'
1×10-6≦(h1−h2)/R≦5×10-5 ……(3)
5×10-6≦(h1−h2)/R≦3×10-5 ……(3)'
(h1−h2)/LPが小さすぎる、または(h1−h2)/Rが小さすぎると、はんだ層が自由端となる突起P1側の周縁部で「引け」を十分軽減することができない。逆に(h1−h2)/LPが大きすぎる、または(h1−h2)/Rが大きすぎると、過剰のはんだが必要になるとともに、半導体基板の水平性が不足する。なお、LP自体は概ね10〜200mmの範囲で設定できる。
2≦X≦10 ……(4)
3≦X≦5 ……(4)'
Xが小さすぎると当該周縁部がはんだクラック発生の起点となる。一方Xが大きすぎると、当該周縁部で基板Aと放熱板との間隔が狭くなりすぎ、「引け」を十分防止することが難しくなる。
基板Aと放熱板の間を構成するはんだ層の厚みを十分確保するために、基板B側の突起P2の高さh2を0.01〜0.5mmの範囲で調整することができ、0.1〜0.4mmとすることが好ましい。
2 はんだ層
3 半導体基板
4 銅パターン
5 絶縁基板
6 導体層
7 半導体素子
8 リード線
11 突起
12 窪み
13 隆起部
Claims (6)
- 複数の半導体基板をはんだ接合により搭載するための銅または銅合金からなる放熱板であって、各半導体基板と放熱板の間隔を確保するための複数の突起を有し、半導体基板を搭載する面が凹面となる下記(1)式を満たす曲面形状を有する放熱板において、
下記(2)式および(3)式を満たすように高さの異なる突起を設けたことを特徴とする半導体基板用放熱板。
1000≦R≦10000 ……(1)
3×10-4≦(h1−h2)/LP≦5×10-3 ……(2)
1×10-6≦(h1−h2)/R≦5×10-5 ……(3)
ただし、並設する複数の半導体基板のうち一方の端に位置するものを基板A、その隣のものを基板Bと呼び、基板Aを載せたときに接する突起のうち、基板Bと反対側の端に位置するものを突起P1、基板B側の端に位置するものを突起P2と呼び、半導体基板を搭載する面を上にして水平面上に置いたときの鉛直方向に平行で、かつ突起P1と突起P2の先端を通る断面を断面Zと呼ぶとき、
R:断面Zにおける板厚中心部の曲率半径(mm)、
h1およびh2:それぞれ突起P1およびP2の突起高さ(mm)、
LP:突起P1とP2の先端距離(mm)、
である。 - 前記基板Aを下記(4)式を満たすように搭載する請求項1に記載の半導体基板用放熱板。
2≦X≦10 ……(4)
ただし、
X:断面Zにおいて基板Aのはんだと接触する部位の突起P1側の端部と突起P1先端との距離(mm)である。 - 突起高さh2が0.01〜0.5mmである請求項1または2に記載の半導体基板用放熱板。
- Z断面における基板Aのはんだ接触面の長さをLA、基板Bのはんだ接触面の長さをLBと呼ぶとき、LA>LBである請求項1〜3の何れか1項に記載の半導体基板用放熱板。
- 板面に設けた突起は、プレス加工により周囲を窪ませることによって形成した円柱状または円錐台状の形状(ただし上面は曲面であって構わない)を有するものである請求項1〜4の何れか1項に記載の半導体基板用放熱板。
- Pbフリーはんだによって半導体基板を接合する請求項1〜5の何れか1項に記載の半導体基板用放熱板。
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WO2012108073A1 (ja) * | 2011-02-08 | 2012-08-16 | 富士電機株式会社 | 半導体モジュール用放熱板の製造方法、その放熱板およびその放熱板を用いた半導体モジュール |
WO2022102253A1 (ja) * | 2020-11-16 | 2022-05-19 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277143A (ja) * | 1988-09-13 | 1990-03-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH1050928A (ja) * | 1996-05-27 | 1998-02-20 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2002057280A (ja) * | 2000-08-10 | 2002-02-22 | Mitsubishi Electric Corp | 半導体装置 |
JP2004228352A (ja) * | 2003-01-23 | 2004-08-12 | Mitsubishi Electric Corp | 電力半導体装置 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277143A (ja) * | 1988-09-13 | 1990-03-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH1050928A (ja) * | 1996-05-27 | 1998-02-20 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2002057280A (ja) * | 2000-08-10 | 2002-02-22 | Mitsubishi Electric Corp | 半導体装置 |
JP2004228352A (ja) * | 2003-01-23 | 2004-08-12 | Mitsubishi Electric Corp | 電力半導体装置 |
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