CN106129004A - 以鳍式fet技术实现的集成式拉伸性应变硅nfet和压缩性应变硅锗pfet - Google Patents

以鳍式fet技术实现的集成式拉伸性应变硅nfet和压缩性应变硅锗pfet Download PDF

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CN106129004A
CN106129004A CN201511021307.0A CN201511021307A CN106129004A CN 106129004 A CN106129004 A CN 106129004A CN 201511021307 A CN201511021307 A CN 201511021307A CN 106129004 A CN106129004 A CN 106129004A
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fin
strain
area
group
silicon
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CN106129004B (zh
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柳青
P·莫林
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STMicroelectronics lnc USA
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STMicroelectronics lnc USA
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

对拉伸性应变的硅层进行图案化以形成在第一衬底区域中的第一组鳍以及在第二衬底区域中的第二组鳍。该第二组鳍覆盖有拉伸性应变的材料，并且执行退火以使在该第二组鳍中的拉伸性应变的硅半导体材料弛豫并在该第二区域中产生多个弛豫的硅半导体鳍。该第一组鳍覆盖有掩模，并且在这些弛豫的硅半导体鳍上提供硅锗材料。然后，将来自该硅锗材料的锗驱入这些弛豫的硅半导体鳍中以在该第二衬底区域中产生多个压缩性应变的硅锗半导体鳍(从中形成多个p沟道鳍式FET器件)。去除该掩模以显露出在该第一衬底区域中的多个拉伸性应变的硅半导体鳍(从中形成多个n沟道鳍式FET器件)。

Description

以鳍式FET技术实现的集成式拉伸性应变硅NFET和压缩性应 变硅锗PFET
技术领域
本发明涉及集成电路，并且具体地涉及使用半导体材料鳍制造的场效应晶体管(FET)器件，其中，NFET器件利用拉伸性应变的硅鳍材料，并且PFET器件利用压缩性应变的硅锗鳍材料。
背景技术
本领域技术人员认识到，相对于n沟道金属氧化物半导体(MOS)场效应晶体管(FET)器件，拉伸性应变的硅(Si)材料提供了增大的电子迁移率和提高的性能。然而，许多集成电路设计同样要求使用p沟道MOSFET器件。这种类型的电路通常被称为互补金属氧化物半导体(CMOS)电路。遗憾的是，拉伸性应变的硅材料对而是优选压缩性应变的硅锗(SiGe)材料以提高空穴迁移率并且提高性能的p沟道MOSFET器件的操作是不利的。拉伸性应变的硅材料与压缩性应变的硅锗材料在支持CMOS电路的制造的公共衬底上的集成已被证明是个挑战。
现有技术教导了利用鳍式FET型场效应晶体管形成集成电路。鳍式FET晶体管包括沟道区，该沟道区被定向为与衬底的表面平行地传导电流。沟道区被提供在半导体材料的被称为“鳍”的细长部分中。晶体管的源极区和漏极区形成在沟道区的任一侧上的细长部分中。栅极被放置为跨坐在沟道区位置处的细长部分的两个相对侧之上和上，以提供对晶体管的导电状态的控制。该鳍式FET设计非常适合于制造多沟道晶体管，在该多沟道晶体管中多个细长部分被并联地形成以限定相邻的沟道区，这些沟道区通过晶体管栅极的以垂直定向在多个细长部分之上的中间栅极部分而彼此分离。
优选以鳍式FET器件制造CMOS电路、n沟道MOSFET器件的半导体材料的细长部分(即，鳍)由拉伸性应变的硅材料制成并且p沟道MOSFET器件的半导体材料的细长部分(即，鳍)由压缩性应变的硅锗(SiGe)材料制成。然而，已经证明难以实现为了支持压缩性应变的硅锗材料的形成而在衬底上获得拉伸性应变的硅材料的弛豫。换言之，在用于支撑CMOS电路的鳍的衬底上提供拉伸性应变的硅材料与压缩性应变的硅锗材料两者具有挑战性。
相应地，本领域中需要一种可以集成拉伸性应变的硅材料与压缩性应变的硅锗材料以便形成CMOS鳍式FET器件的制造方法。
发明内容
在实施例中，一种方法包括：在由衬底所支撑的拉伸性应变的硅半导体层上沉积硬掩模；将所述硬掩模和所述拉伸性应变的硅半导体层图案化为多个鳍；所述多个鳍包括在该衬底的第一区域中的第一组鳍以及在该衬底的第二区域中的第二组鳍；在该多个鳍上形成多个侧壁间隔物；沉积并图案化拉伸性应变的材料以覆盖该第二区域中的该第二组鳍但是不覆盖该第一组鳍；执行退火，该退火使在该衬底的该第二区域中的该第二组鳍的该拉伸性应变的硅半导体层弛豫；沉积并图案化掩模材料以覆盖该衬底的该第一区域中的该第一组鳍但是不覆盖该第二组鳍；在该衬底的该第二区域中的该第二组鳍上提供硅锗材料；将来自该硅锗材料的锗驱入该第二组鳍中以在该衬底的该第二区域中产生多个压缩性应变的硅锗半导体鳍；以及去除该掩模材料以在该衬底的该第一区域中产生多个拉伸性应变的硅半导体鳍。
在实施例中，一种方法包括：在衬底的拉伸性应变的半导体层上沉积硬掩模；将所述硬掩模和所述拉伸性应变的半导体层图案化为多个鳍，所述多个鳍包括在该衬底的第一区域中的第一组鳍以及在该衬底的第二区域中的第二组鳍；形成并图案化拉伸性应变的材料，从而使得该拉伸性应变的材料覆盖该第二组鳍但是不覆盖该第一组鳍；当该拉伸性应变的材料覆盖该第二组鳍但是不覆盖该第一组鳍时执行退火，该退火使在该第二组鳍中的该拉伸性应变的半导体材料弛豫，导致在该第二组鳍中的拉伸性应变比在该第一组鳍中的相对较低；形成并图案化掩模材料，从而使得该掩模材料覆盖该第一组鳍但是不覆盖该第二组鳍；在该第二组鳍上形成第二半导体材料，该第二半导体材料包括锗；将来自该第二半导体材料的锗驱入该第二组鳍中以在该衬底的该第二区域中产生多个压缩性应变的半导体鳍；以及去除该掩模材料以在该衬底的该第一区域中产生多个拉伸性应变的半导体鳍。
在实施例中，一种方法包括：在由衬底所支撑的拉伸性应变的硅半导体层上沉积硬掩模；将所述硬掩模和所述拉伸性应变的硅半导体层图案化为多个鳍；所述多个鳍包括在该衬底的第一区域中的第一组鳍以及在该衬底的第二区域中的第二组鳍；在该多个鳍上形成多个侧壁间隔物；以拉伸性应变的材料覆盖该第二区域内的该第二组鳍，该拉伸性应变的材料不覆盖该第一组鳍；执行退火，该退火使在该第二组鳍中的该拉伸性应变的硅半导体材料弛豫以在该衬底的该第二区域中产生多个弛豫的硅半导体鳍；以掩模材料覆盖该衬底的该第一区域中的该第一组鳍，该掩模材料不覆盖该第二组鳍；在该衬底的该第二区域中的该弛豫的硅半导体鳍上提供硅锗材料；将来自该硅锗材料的锗驱入该弛豫的硅半导体鳍中以在该衬底的该第二区域中产生多个压缩性应变的硅锗半导体鳍；以及去除该掩模材料以在该衬底的该第一区域中产生多个拉伸性应变的硅半导体鳍。
在实施例中，在该衬底的该第一区域中的这些拉伸性应变的硅半导体鳍用于产生多个第一导电类型鳍式FET晶体管，并且在该衬底的该第二区域中的这些压缩性应变的硅锗半导体鳍用于产生多个第二导电类型鳍式FET晶体管。
在实施例中，一种集成电路包括：包含第一区域和第二区域的衬底；在该衬底的该第一区域中的多个拉伸性应变的硅半导体鳍；在该衬底的该第二区域中的多个压缩性应变的硅锗半导体鳍；在该第一区域中的该多个拉伸性应变的硅半导体鳍之上延伸的第一金属栅极；以及在该第二区域中的该多个压缩性应变的硅锗半导体鳍之上延伸的第二金属栅极；其中，所述多个压缩性应变的硅锗半导体鳍包括已经被弛豫并且已经向其内驱入锗的拉伸性应变的硅半导体材料。
附图说明
为了更好地理解实施例，现在将仅以示例方式参照附图，在附图中：
图1至图21B展示了形成CMOS鳍式FET器件的工艺步骤。
具体实施方式
现在参照图1至图21B，图1至图21B展示了形成CMOS鳍式FET器件的工艺步骤。将理解的是，附图不一定示出按比例绘制的特征。
图1示出了绝缘体上硅(SOI)半导体衬底10，该绝缘体上硅半导体衬底包括在晶片的堆叠中的半导体衬底12、绝缘层14和拉伸性应变的硅半导体层16。这种衬底在本领域中通常通过首字母缩略词sSOI来提及，其中，小写字母“s”指的是术语“应变的(strained)”。拉伸性应变的硅半导体层16根据应用可以是掺杂的，或者替代性地可以是未掺杂的(在这种情况下，sSOI衬底10是“完全耗尽”型的)。例如，拉伸性应变的半导体层16可以具有30nm-50nm的厚度。绝缘层14在本领域中通常被称为掩埋氧化物(BOX)层。衬底10包括被预留用于形成多个第一极性(例如，n沟道)的器件(NFET)的区域18以及被预留用于形成多个第二相反极性(例如，p沟道)的器件(PFET)的区域20。
然后，在半导体层16上沉积包括氮化硅(SiN)层34的硬掩模30。例如，可以使用化学气相沉积(CVD)工艺以例如大约20nm的厚度来沉积氮化硅层34。在图2中示出了结果。
然后使用在本领域已知的光刻工艺来从拉伸性应变的硅半导体层16中限定多个鳍50。对硬掩模30进行图案化，以在这些鳍50的期望位置处留下掩模材料36。然后，执行蚀刻操作(如各向异性干法蚀刻)穿过该掩模以在每个鳍50的每一侧上的层16中开出多个孔52。例如，在sSOI衬底的优选实施例中，限定这些鳍50的蚀刻延伸至到达绝缘层14的深度。每个鳍50相应地包括拉伸性应变的硅半导体鳍区16’和掩模材料36。这些鳍50可以具有6nm-12nm的宽度和25nm-30nm的间距(具有17nm-22nm的相邻鳍之间的间隔)。在图3中示出了用于鳍形成的刻蚀工艺的结果。
然后，使用原子层沉积技术进行氧化硅(SiO2)层60的共形沉积。层60可以具有大约3nm的厚度。参见图4。然后，执行定向刻蚀(如，反应离子蚀刻(RIE))以在每个鳍50的每一侧上限定氧化物侧壁间隔物62。在图5中示出了结果。
然后，使用原子层沉积技术进行氮化硅(SiN)层70的共形沉积。层70可以具有大约3nm的厚度。参见图6。然后，执行定向刻蚀(如，反应离子蚀刻(RIE))以在每个鳍50的每一侧上限定氮化物侧壁间隔物72。在图7中示出了结果。
然后，使用原子层沉积技术进行氧化硅(SiO2)层80的共形沉积。层80可以具有大约10nm的厚度。参见图8。在对层80进行沉积之后，晶片经受退火(例如，在1050℃的温度下进行30秒)，以便实现对所沉积的氧化物侧壁间隔物62和氮化物侧壁间隔物72的稠化。在这种情况下，稠化有利地使氧化硅材料变硬，以使得该材料更难以用常规的蚀刻工艺(如HF、COR或热磷酸)去除或凹陷。
然后，以光刻掩模工艺封堵针对形成n沟道器件(NFET)所预留的区域18，并且开出针对形成p沟道器件(PFET)所预留的区域20(参考82)。区域20的此开出包括去除层80和那些氮化物侧壁间隔物72。然后，去除自光刻工艺存在以封堵区域18的任何抗蚀剂。在图9中示出了结果。
注意，可以至少关于所开出的区域20进行可选的对氧化硅(SiO2)层进行共形沉积，以便针对每个鳍50覆盖并保护掩模材料36。在图9中未明确示出此层。
接下来，进行对拉伸性应变的氮化硅(SiN)的沉积以填充区域20。如在本领域中已知的，可以通过适当地选择沉积参数(温度、压力等)来调节对氮化硅材料的沉积以提高或者拉伸性或者压缩性的应力。然后，执行化学机械抛光(CMP)操作以对在存在于区域18中的氧化硅层80的顶部处的拉伸性应变的氮化硅沉积进行平坦化。如在图10中所示出的，结果是覆盖区域20中的这些鳍50的拉伸性应变的氮化硅块90。例如，拉伸性应变可以在500Mpa至1.5GPa的范围内。
然后，使用BHF/HF蚀刻去除区域18中的氧化硅层80。在图11中示出了结果。注意，由于去除了区域18中的层80，拉伸性应变的氮化硅块90被完全地切断与区域18中的这些鳍50的接触(即，块90并不直接接触区域18中的这些鳍50或这些鳍50上的这些侧壁间隔物)。
然后，衬底晶片经受高温退火(例如，在1200℃的温度下进行2分钟)以使区域20中的应变弛豫。此弛豫由于所施加的温度以及拉伸性应变的氮化硅块90与区域20中的这些鳍50的非常接近而发生(即，材料之间的分离仅仅是通过这些侧壁间隔物62的变薄的厚度进行的)。因此，区域20中的每个鳍50的拉伸性应变的硅半导体鳍区16’被转换为弛豫的硅半导体鳍区116。取决于初始应变，区域16’可以具有1Gpa-1.5Gpa的应变，而区域116在弛豫之后可以具有大约100MPa的应变。在图12中示出了结果。注意，区域18中的每个鳍50的拉伸性应变的硅半导体鳍区16’不是弛豫的(或到弛豫发生的程度，这种弛豫是最小的(例如，其将保持大于其原始应变的80％))，因为拉伸性应变的氮化硅块90没有对区域18中的这些鳍50的直接接触。
接下来，进行对氧化硅(SiO2)的沉积以填充区域18。使用可流动氧化物工艺来进行此沉积。然后，执行化学机械抛光(CMP)操作以对在存在于区域20中的拉伸性应变的氮化硅块90的顶部处的氧化硅沉积进行平坦化。如在图13中所示出的，结果是覆盖区域18中的这些鳍50的氧化硅块92。
然后，去除拉伸性应变的氮化硅块90使其不再覆盖区域20中的这些鳍50。例如，此去除是使用对氧化硅具有选择性的热磷酸蚀刻来完成的。然后，执行HF或COR蚀刻工艺以去除氧化硅。此工艺将从区域20中的这些鳍50中去除全部的侧壁间隔物62和掩模材料36，从而留下那些弛豫的硅半导体鳍区116，同时去除覆盖区域18中的这些鳍50的全部或基本上全部氧化硅块92。在图14中示出了结果。然而，注意，覆盖区域18中的这些鳍50的掩模材料36、侧壁间隔物72和侧壁间隔物62保留在位，以在对区域20中的这些鳍50进行接下来的加工操作期间保护区域18中的这些鳍50。
此时关于硅锗材料在区域20中的供应提供了两个选项。在第一个选项中，如在图15A中所示出的，执行外延生长工艺以在那些弛豫的硅半导体鳍区116上生长外延硅锗区120。在第二个选项中，如在图15B中所示出的，使用非选择性外延工艺来沉积非晶态硅锗层122以覆盖这些弛豫的硅半导体鳍区116。虽然非晶态层122也将覆盖区域18中的这些鳍50，注意，掩模材料36、侧壁间隔物72和侧壁间隔物62保持在位以覆盖这些鳍50。然后，执行冷凝工艺以将来自区120或层122的锗驱入这些弛豫的硅半导体鳍区116并且产生多个压缩性应变的硅锗鳍区216。例如，该冷凝可以包括氧化工艺，该氧化工艺使用900℃氧化，接着是1000℃ N2退火。然后，去除从冷凝工艺中所产生的氧化硅和/或氧化锗。在图16中示出了结果。
使用热磷酸清洗、氢氟酸清洗和热磷酸清洗的序列，去除用于区域18中的这些鳍50的掩模材料36、侧壁间隔物72和侧壁间隔物62。在图17中示出了结果，其中，区域18包括多个拉伸性应变的硅半导体鳍区16’，并且区域20包括多个压缩性应变的硅锗鳍区216。注意，如果所关心的是关于在热磷酸清洗、氢氟酸清洗和热磷酸清洗的序列期间这些压缩性应变的硅锗鳍区216的硅锗材料的消耗，可以首先通过薄氧化硅层(大约5nm)来保护这些压缩性应变的硅锗鳍区216，其中，对氧化硅层进行光刻加工并且将其从区域18中去除。然后，使用热磷酸清洗来去除氮化硅掩模和间隔物。然后，使用氢氟酸清洗来去除二氧化硅间隔物和保护层。
使用常规的化学气相沉积(CVD)工艺来沉积牺牲性多晶硅材料240以覆盖这些拉伸性应变的硅半导体鳍区16’和这些压缩性应变的硅锗鳍区216。在替代性实现方式中，多晶硅材料240可以而是包括非晶态硅。可以在沉积多晶硅材料240之前，在这些鳍区16’和216的暴露表面上形成共形氧化物(未明确示出)。如本领域技术人员所理解的那样，多晶硅材料(具备氧化物)与通常被称为“假栅极”结构的结构的形成相关联。随后在制造工艺中将后续去除这些假栅极结构的多晶硅材料，并且以限定用于那些晶体管器件的实际操作的栅极电极的金属栅极堆叠来对其进行替换(此工艺在本领域中被称为“替换栅极电极(RMG)”工艺)。从而，不需要对多晶硅材料240进行掺杂。多晶硅材料240的沉积将具有超过这些鳍区16’和216的高度的高度，从而使得这些鳍将被完全去除。材料240可以具有例如60nm-100nm的厚度。使用常规的化学机械抛光(CMP)技术来使多晶硅材料240沉积的顶表面平坦化以提供平坦顶表面。
使用化学气相沉积(CVD)工艺在多晶硅材料240的平坦顶表面上沉积具有20nm-40nm的厚度的硬掩模层242。以本领域技术人员所熟知的方式对层242进行光刻图案化以在用于那些假栅极结构的多个期望位置处留下掩模材料244。然后，执行反应离子蚀刻(RIE)以在假栅极248的任一侧上的多晶硅材料中开出多个孔246。假栅极248的结构可以被认为在沟道区处跨坐在鳍区16’和216中的每一个鳍区之上或者跨坐在多个相邻鳍区之上(参见图18A)。
然后，例如，使用本领域中已知的原子层沉积(ALD)技术对氮化硅材料进行共形沉积，并且随后优先在那些水平表面上对其进行蚀刻以在那些多晶硅假栅极248的那些侧壁上留下多个侧壁间隔物250(参见图18B和图18C)。
假栅极结构相应地包括图案化的多晶硅(或非晶态硅)假栅极结构248、叠置的氮化硅帽盖(由掩模材料244形成)以及多个侧壁间隔物250。虽然没有在图18B和图18C中具体示出，还可以根据已知的栅极翻转(tuck-under)技术而在鳍区16’和216中的每个鳍区的端部形成假栅极结构。
使用外延工艺工具并且从鳍区16’和216的暴露表面开始，进行对基于硅的半导体材料的外延生长270。外延生长270在这些鳍的顶表面上方延伸至与在这些假栅极结构的任一侧上的这些侧壁间隔物250相邻的多个区。如给定应用所需要的，可以对基于硅的外延生长270进行原位掺杂。由于外延生长270，分别在这些假栅极结构的任一侧上形成升高的源极区272和漏极区274。在图19A至图19B中示出了结果。例如，外延生长70可以包括针对NFET区域18内的这些鳍区16’的掺杂有达1×1020至5×1020at/cm3掺杂浓度的磷或砷的硅或碳化硅。例如，外延生长70可以包括针对PFET区域20内的这些鳍区216的掺杂有达1×1020至5×1020at/cm3掺杂浓度的硼的硅锗。使用本领域中已知的适当的光刻掩模工艺来分别地开出区域18和20以在每个区内容纳选择性外延生长。
现参照图20A至图20B。沉积二氧化硅材料280以覆盖衬底。可以使用常规的化学机械抛光(CMP)技术对材料280进行进一步的加工以提供停止于每个假栅极结构的顶部的平坦顶表面。
使用选择性去除工艺(如氢氧化铵蚀刻)，去除这些假栅极248。然后以金属栅极结构290替换所去除的这些假栅极248。在一个示例中，金属栅极结构可以包括使用原子层沉积(ALD)工艺以1nm-2nm的厚度沉积的高K电介质内衬(形成用于晶体管的栅极电介质)、使用化学气相沉积工艺沉积的功函数金属以及使用化学气相沉积工艺沉积的接触金属填充物。绝缘帽盖292覆盖金属栅极结构290。在图21A至图21B中示出了结果。
然后，执行本领域技术人员所熟知的进一步加工，以产生对栅极(金属栅极结构290)、源极区272和漏极区274的金属接触。例如，可以沉积附加的二氧化硅材料，以便完成针对集成电路形成预金属化电介质(PMD)层。可以使用常规的化学机械抛光(CMP)技术来对这种材料进行进一步的加工以提供平坦顶表面。然后，使用涂覆工艺在PMD层的平坦顶表面上沉积硬掩模层，例如，有机平坦化层(OPL)。然后，以本领域技术人员所熟知的方式对OPL进行光刻图案化，以在用于与栅极、源极区和漏极区进行电接触的多个期望位置处形成多个开口。然后，执行反应离子蚀刻(RIE)以开出多个孔并且使这些孔完全延伸穿过预金属化电介质(PMD)，以便暴露栅极金属的顶表面和源极区与漏极区的外延生长。然后去除该OPL。然后，以一种或多种金属材料填充这些孔，以便限定对晶体管的栅极、源极区和漏极区中每一项的接触。如必要，可以使用常规的化学机械抛光(CMP)技术来去除过多的金属以便提供平坦顶表面。例如，限定这些接触的这些金属材料可以包括使用化学气相沉积工艺沉积的钨。该制造工艺与在源极接触和漏极接触的底部形成硅化物相兼容。这些用于硅化物化的技术对于本领域技术人员而言是熟知的。例如，硅化物可以包括典型的镍钼硅化物、或者替代性地由于针对接触使用氮化钛内衬而产生的硅化物。
此时，完成了集成电路的前段制程(FEOL)制造。然后，可以如本领域技术人员所熟知的那样执行进一步的后段制程(BEOL)加工以制造金属化和互连。
已经通过对本发明的示例性实施例的完整且信息性的描述的示例性且非限制性示例提供了之前的描述。然而，对于相关领域的技术人员而言，鉴于前面的描述，当结合附图和所附权利要求书来阅读本说明书时，各种修改和适配会变得明显。然而，对本发明教导的所有这样和类似的修改将仍然落入如所附权利要求书所确定的本发明的范围之内。

Claims (27)

1.一种方法，包括：
在由衬底所支撑的拉伸性应变的硅半导体层上沉积硬掩模；
将所述硬掩模和所述拉伸性应变的硅半导体层图案化为多个鳍；所述多个鳍包括在所述衬底的第一区域中的第一组鳍以及在所述衬底的第二区域中的第二组鳍；
在所述多个鳍上形成多个侧壁间隔物；
沉积并图案化拉伸性应变的材料以覆盖所述第二区域中的所述第二组鳍但是不覆盖所述第一组鳍；
执行退火，所述退火使在所述衬底的所述第二区域中的所述第二组鳍的所述拉伸性应变的硅半导体层弛豫；
沉积并图案化掩模材料以覆盖所述衬底的所述第一区域中的所述第一组鳍但是不覆盖所述第二组鳍；
在所述衬底的所述第二区域中的所述第二组鳍上提供硅锗材料；
将来自所述硅锗材料的锗驱入所述第二组鳍中以在所述衬底的所述第二区域中产生多个压缩性应变的硅锗半导体鳍；以及
去除所述掩模材料以在所述衬底的所述第一区域中产生多个拉伸性应变的硅半导体鳍。
2.如权利要求1所述的方法，进一步包括：
使用在所述衬底的所述第一区域中的所述拉伸性应变的硅半导体鳍来产生多个第一导电类型鳍式FET晶体管；以及
使用在所述衬底的所述第二区域中的所述压缩性应变的硅锗半导体鳍来产生多个第二导电类型鳍式FET晶体管。
3.如权利要求2所述的方法，其中，使用在所述衬底的所述第一区域中的所述拉伸性应变的硅半导体鳍来产生多个第一导电类型鳍式FET晶体管包括：
形成在所述拉伸性应变的硅半导体鳍之上延伸的假栅极结构，所述假栅极结构包括多晶硅材料；
在所述假栅极结构上形成多个侧壁间隔物；以及
以替换金属栅极结构替换所述假栅极结构的所述多晶硅材料。
4.如权利要求2所述的方法，其中，使用在所述衬底的所述第二区域中的所述压缩性应变的硅锗半导体鳍来产生多个第二导电类型鳍式FET晶体管包括：
形成在所述压缩性应变的硅锗半导体鳍之上延伸的假栅极结构，所述假栅极结构包括多晶硅材料；
在所述假栅极结构上形成多个侧壁间隔物；以及
以替换金属栅极结构替换所述假栅极结构的所述多晶硅材料。
5.如权利要求2所述的方法，其中，所述第一导电类型是n型，并且所述第二导电类型是p型。
6.如权利要求1所述的方法，其中，所述拉伸性应变的材料是拉伸性应变的氮化硅。
7.如权利要求1所述的方法，其中，所述衬底是绝缘体上硅型衬底。
8.如权利要求1所述的方法，其中，提供硅锗材料包括在所述衬底的所述第二区域中的所述第二组鳍的多个暴露的半导体表面上外延地生长硅锗材料。
9.如权利要求1所述的方法，其中，提供硅锗材料包括在所述衬底的所述第二区域中的所述第二组鳍的多个暴露的半导体表面上沉积非晶态硅锗材料。
10.如权利要求1所述的方法，其中，沉积并图案化所述拉伸性应变的材料包括确保所述拉伸性应变的材料未与所述第一区域中的所述第一组鳍的所述侧壁间隔物直接接触。
11.如权利要求1所述的方法，其中，在所述多个鳍上形成多个侧壁间隔物包括：
在所述多个鳍的多个侧表面上形成氧化物侧壁间隔物；以及
在所述氧化物侧壁间隔物的多个侧表面上形成氮化物侧壁间隔物。
12.如权利要求11所述的方法，其中，沉积并图案化所述拉伸性应变的材料包括：
从所述第二区域中的所述第二组鳍中去除所述氮化物侧壁间隔物；以及
在所述第二区域中的所述第二组鳍的所述氧化物侧壁间隔物上沉积所述拉伸性应变的材料。
13.一种方法，包括：
在衬底的拉伸性应变的半导体层上沉积硬掩模；
将所述硬掩模和所述拉伸性应变的半导体层图案化为多个鳍，所述多个鳍包括在所述衬底的第一区域中的第一组鳍以及在所述衬底的第二区域中的第二组鳍；
形成并图案化拉伸性应变的材料，使得所述拉伸性应变的材料覆盖所述第二组鳍但是不覆盖所述第一组鳍；
当所述拉伸性应变的材料覆盖所述第二组鳍但是不覆盖所述第一组鳍时执行退火，所述退火使在所述第二组鳍中的所述拉伸性应变的半导体材料弛豫，导致在所述第二组鳍中的拉伸性应变比在所述第一组鳍中的相对更低；
形成并图案化掩模材料，使得所述掩模材料覆盖所述第一组鳍但是不覆盖所述第二组鳍；
在所述第二组鳍上形成第二半导体材料，所述第二半导体材料包括锗；
将来自所述第二半导体材料的锗驱入所述第二组鳍中以在所述衬底的所述第二区域中产生多个压缩性应变的半导体鳍；以及
去除所述掩模材料以在所述衬底的所述第一区域中产生多个拉伸性应变的半导体鳍。
14.如权利要求13所述的方法，其中，在所述多个鳍中的所述第一组鳍包括在所述衬底的所述第一区域中的多个压缩性应变的半导体鳍，所述方法进一步包括：
使用在所述衬底的所述第一区域中的所述拉伸性应变的半导体鳍来产生多个第一导电类型鳍式FET晶体管；以及
使用在所述衬底的所述第二区域中的所述压缩性应变的半导体鳍来产生多个第二导电类型鳍式FET晶体管。
15.如权利要求14所述的方法，其中，所述第一导电类型是n型，并且所述第二导电类型是p型。
16.如权利要求13所述的方法，其中，所述拉伸性应变的材料是拉伸性应变的氮化硅。
17.如权利要求13所述的方法，其中，形成所述第二半导体材料包括在所述衬底的所述第二区域中的所述第二组鳍的多个暴露的半导体表面上外延地生长含锗的半导体材料。
18.如权利要求13所述的方法，其中，形成所述第二半导体材料包括在所述衬底的所述第二区域中的所述第二组鳍的多个暴露的半导体表面上沉积含锗的非晶态半导体材料。
19.一种集成电路，包括：
包含第一区域和第二区域的衬底；
在所述衬底的所述第一区域中的多个拉伸性应变的硅半导体鳍；
在所述衬底的所述第二区域中的多个压缩性应变的硅锗半导体鳍；
在所述第一区域中的所述多个拉伸性应变的硅半导体鳍之上延伸的第一金属栅极；以及
在所述第二区域中的所述多个压缩性应变的硅锗半导体鳍之上延伸的第二金属栅极；
其中，所述多个压缩性应变的硅锗半导体鳍包括已经被弛豫并且已经向其内驱入了锗的拉伸性应变的硅半导体材料。
20.如权利要求19所述的集成电路，其中，所述衬底是绝缘体上硅型衬底。
21.如权利要求19所述的集成电路，其中：
所述拉伸性应变的硅半导体鳍和所述第一金属栅极形成多个第一导电类型鳍式FET晶体管；以及
所述压缩性应变的硅锗半导体鳍和第二金属栅极形成多个第二导电类型鳍式FET晶体管。
22.如权利要求21所述的集成电路，其中，所述第一导电类型是n型，并且所述第二导电类型是p型。
23.一种方法，包括：
在由衬底所支撑的拉伸性应变的硅半导体层上沉积硬掩模；
将所述硬掩模和所述拉伸性应变的硅半导体层图案化为多个鳍，所述多个鳍包括在所述衬底的第一区域中的第一组鳍以及在所述衬底的第二区域中的第二组鳍；
在所述多个鳍上形成多个侧壁间隔物；
以拉伸性应变的材料覆盖所述第二区域内的所述第二组鳍，所述拉伸性应变的材料不覆盖所述第一组鳍；
执行退火，所述退火使在所述第二组鳍中的所述拉伸性应变的硅半导体材料弛豫以在所述衬底的所述第二区域中产生多个弛豫的硅半导体鳍；
以掩模材料覆盖所述衬底的所述第一区域中的所述第一组鳍，所述掩模材料不覆盖所述第二组鳍；
在所述衬底的所述第二区域中的所述弛豫的硅半导体鳍上提供硅锗材料；
将来自所述硅锗材料的锗驱入所述弛豫的硅半导体鳍中以在所述衬底的所述第二区域中产生多个压缩性应变的硅锗半导体鳍；以及
去除所述掩模材料以在所述衬底的所述第一区域中产生多个拉伸性应变的硅半导体鳍。
24.如权利要求23所述的方法，进一步包括：
使用在所述衬底的所述第一区域中的所述拉伸性应变的硅半导体鳍来产生多个第一导电类型鳍式FET晶体管；以及
使用在所述衬底的所述第二区域中的所述压缩性应变的硅锗半导体鳍来产生多个第二导电类型鳍式FET晶体管。
25.如权利要求24所述的方法，其中，所述第一导电类型是n型，并且所述第二导电类型是p型。
26.如权利要求23所述的方法，其中，所述拉伸性应变的材料是拉伸性应变的氮化硅。
27.如权利要求23所述的方法，其中，所述硅锗材料是通过以下方式之一提供的：外延地生长硅锗材料或沉积非晶态硅锗材料。
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