CN110692119A - 具有共用栅极堆叠的双通道cmos - Google Patents
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- CN110692119A CN110692119A CN201880032181.2A CN201880032181A CN110692119A CN 110692119 A CN110692119 A CN 110692119A CN 201880032181 A CN201880032181 A CN 201880032181A CN 110692119 A CN110692119 A CN 110692119A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
实施例涉及用于具有共用过栅极堆叠的双通道互补金属氧化物半导体(CMOS)的方法和所得结构。在衬底上形成第一半导体鳍片。在衬底上与第一半导体鳍片相邻地形成第二半导体鳍片。在第一和第二半导体鳍片上形成氧化物层,并在有效增加第二半导体鳍片的锗浓度的温度下退火。退火工艺对第二半导体鳍片具有选择性,并且不会增加第一半导体鳍片的锗浓度。
Description
背景技术
本发明一般涉及用于半导体器件的制造方法和所得结构。更具体地,本发明涉及具有共用栅极堆叠的双通道互补金属氧化物半导体(CMOS)。
在现代半导体器件制造工艺中,在单个晶片上制造大量半导体器件,例如n型金属氧化物半导体(NMOS)和p型金属氧化物半导体(PMOS)。在CMOS集成电路(IC)中,这些NMOS和CMOS晶体管的互补和对称对用于逻辑功能。使用PMOS补充每个NMOS并将两个栅极和两个漏极连接在一起,相对于其他逻辑系列,大大降低了功耗和发热量。例如,在CMOS IC中,栅极上的高电压将仅导致NMOS导通,而栅极上的低电压仅导致PMOS导通。
发明内容
本发明的实施例涉及一种用于制造具有共用栅极堆叠的双通道互补金属氧化物半导体(CMOS)的方法。该方法的非限制性示例包括在衬底上形成第一半导体鳍片。在衬底上与第一半导体鳍片相邻地形成第二半导体鳍片。在第一和第二半导体鳍片上形成氧化物层,并在有效增加第二半导体鳍片的锗浓度的温度下退火。退火工艺对第二半导体鳍片具有选择性,并且不会增加第一半导体鳍片的锗浓度。
本发明的实施例涉及一种用于制造具有共用栅极堆叠的双通道互补金属氧化物半导体(CMOS)的方法。该方法的非限制性示例包括使硅衬底的一部分凹陷并在硅衬底的凹陷部分上形成包括硅锗的半导体层。在衬底的未凹陷部分上形成第一半导体鳍片,并且在半导体层上方并且与第一半导体鳍片相邻地形成第二半导体鳍片。在第一和第二半导体鳍片上形成包括锗的氧化物层,并在有效增加第二半导体鳍片的锗浓度的温度下对氧化物层进行退火。然后在第一和第二半导体鳍片的沟道区上形成共用导电栅极。
本发明的实施例涉及一种用于制造具有共用栅极堆叠的双通道互补金属氧化物半导体(CMOS)的方法。该方法的非限制性示例包括在衬底上形成包括硅和锗的半导体鳍片。在半导体鳍片上形成包括锗的氧化物层,并在有效增加半导体鳍片的锗浓度的温度下退火。退火工艺根据反应(I)氧化半导体鳍片中的硅,并将锗在氧化物层中缩合:
(I)Si+Ge+2GeO2→SiO2+Ge+GeO。
本发明的实施例涉及半导体器件。半导体器件的非限制性示例包括衬底上的第一半导体鳍片和与衬底上的第一半导体鳍片相邻的第二半导体鳍片。第二半导体鳍片包括底部、中间部分和顶部。中间部分包括第一浓度的第一材料,顶部包括第二浓度的第一材料。第二浓度高于第一浓度。共用导电栅极形成在第一和第二半导体鳍片的沟道区上方。
本发明的实施例涉及半导体器件。半导体器件的非限制性示例包括在衬底上包括硅的第一半导体鳍。具有底部、中间部分和顶部的第二半导体鳍,形成在衬底上,与第一半导体鳍相邻。第二半导体鳍片的底部不包括锗。第二半导体鳍片的中间部分包括较低浓度的锗,第二半导体鳍片的顶部包括较高浓度的锗。共用导电栅极在第一和第二半导体鳍片的沟道区上方形成。
通过本发明的技术实现了其他技术特征和益处。本文详细描述了本发明的实施例和各个方面,并且其被认为是所要求保护的主题的一部分。为了更好地理解,请参考详细的说明书和附图。
附图说明
在说明书结论的权利要求中特别指出并清楚地要求保护本文所述专有权的细节。通过以下结合附图的详细描述,本发明的实施例的前述和其他特征和优点将变得显而易见,其中:
图1描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图2描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图3描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图4描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图5描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图6描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图7描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;
图8描述了根据本发明的一个或多个实施例的处理操作之后的半导体结构的截面图;以及
图9描述了根据本发明的一个或多个实施例的方法的流程图。
这里描绘的图是说明性的。在不脱离本发明的精神的情况下,可以对图或其中描述的操作进行许多变化。例如,可以以不同的顺序执行动作,或者可以添加、删除或修改动作。
在附图和以下对本发明实施例的详细描述中,附图中示出的各种元件具有两个或三个数字的附图标记。除了少数例外,每个附图标记的最左边的数字对应于其元素首先被示出的图。
具体实施方式
为简洁起见,本文中可能会或可能不会详细描述与半导体器件和集成电路(IC)制造相关的传统技术。此外,本文描述的各种任务和处理步骤可以合并到更全面的过程或工艺中,该过程或工艺具有本文未详细描述的附加步骤或功能。特别地,半导体器件和基于半导体的IC的制造中的各种步骤是众所周知的,因此,为了简洁起见,许多常规步骤将仅在本文中简要提及或将完全省略而不提供众所周知的工艺细节。
现在转向与本发明的各方面更具体相关的技术的概述,如前所述,CMOS逻辑架构采用用于逻辑功能的互补的NMOS和PMOS对,从而相对其他逻辑家族降低功耗和发热量。然而,在将CMOS架构扩展到10nm节点之外存在挑战。随着器件特征尺寸变小,电子和空穴迁移率开始成为设备性能改进的瓶颈。未来(低于10nm节点)架构的有希望的CMOS集成方案之一是使用应变工程通过调制晶体管沟道中的机械应变来改善电子和空穴迁移率。
在CMOS平台中使用应变工程的一个特定挑战是NMOS和PMOS晶体管对不同类型的应变的响应不同。例如,双通道CMOS结合用于pFET的压缩应变Si1-xGex层与用于nFET的拉伸应变Si层串联,可以提供极大增强的电子和空穴迁移率。增加电子和空穴迁移率可提高CMOS通道的导电性,并提高器件性能。如果对nFET和pFET器件均相同地增强载流子迁移率,则简化CMOS电路设计。然而,在双通道CMOS器件中同样增加空穴和电子迁移率的设计方法是有问题的,部分原因是难以为具有足够高的锗浓度的pFET提供应变Si1-xGex层以满足性能和可靠性要求。特别地,由于硅上Si1-xGex外延生长的临界厚度,使用当前的CMOS技术不能实现具有高Ge浓度(即,大于25原子百分比Ge)的应变Si1-xGex层。此外,用于增加pFET的Ge浓度的常规Ge缩合技术不能用于双通道CMOS工艺,因为高温氧气氛氧化工艺(即,大于约950摄氏度)也氧化nFET鳍片。因此,传统的双通道CMOS电子迁移率可以是空穴迁移率的大约两倍。
现在转到本发明的各方面的概述,本发明的一个或多个实施例提供了具有公共栅极堆叠的双通道CMOS器件。在硅(Si)衬底的凹陷部分上形成具有相对低的锗(Ge)浓度的半导体层。如本文所用,“低”锗浓度限于小于约25原子百分比,以满足硅临界厚度要求下的Si1-xGex外延生长。图案化半导体层和衬底以形成互补的硅nFET鳍和硅锗pFET鳍对。在nFET和pFET鳍片上共形地形成诸如GeO2的含锗氧化物层。然后氧化物层中的锗选择性地凝聚到pFET鳍中。
Ge缩合过程不需要高温(即,约500至约700摄氏度的温度就足够)并且可以在惰性无氧环境中完成。以这种方式,选择性Ge缩合过程使得具有“高”锗浓度(即,Ge浓度大于约25%)的应变Si1-xGexpFET成为可能。有利地,可以通过调节含锗氧化物层的厚度来调节pFET鳍片的最终锗含量。例如,增加氧化物层的厚度将增加pFET鳍片的最终Ge浓度。此外,Ge缩合工艺对pFET鳍片具有选择性,并且不会改变nFET鳍片。因此,该工艺与具有共用栅极堆叠的Si/SiGe双沟道CMOS平台完全兼容。
现在转到本发明的各方面的更详细描述,图1描述了根据一个或多个本发明的实施例的制造CMOS器件的方法的中间操作期间具有衬底102的结构100的截面图。衬底102包括与PMOS区106相邻的NMOS区104。在NMOS区104上形成硬掩模108。使用例如湿法蚀刻、干法蚀刻或其组合使衬底102的暴露部分(即,PMOS区106中未被硬掩模108覆盖的那些部分)凹陷。然后,在衬底102的凹陷部分上的PMOS区域106中形成具有第一锗浓度的半导体层110。
衬底102可以是任何合适的衬底材料,例如单晶硅、SiC、III-V化合物半导体、II-VI化合物半导体或绝缘体上半导体(SOI)。在一些实施例中,衬底102包括掩埋氧化物层(未示出)。在本发明的一些实施例中,衬底102是硅。
半导体层110可以是任何合适的PMOS材料,例如硅锗(SiGe)。在本发明的一些实施例中,衬底102是硅,半导体层110是外延生长的SiGe。由于硅和SiGe之间的晶格常数的差异,在硅上外延生长SiGe有利地使SiGe层变形。
如前所述,硅上Si1-xGex外延生长的临界厚度限制了半导体层110的锗浓度。在本发明的一些实施例中,半导体层110是锗浓度小于约25锗原子百分比的SiGe,以满足临界厚度要求。例如,锗浓度可为约10至约20原子百分比。半导体层110可以形成为约10nm至约100nm的厚度。在本发明的一些实施例中,半导体层110是具有约50nm的厚度的SiGe20%(即,包括20原子百分比的锗的SiGe)。
可以通过在PMOS区域106中的衬底102上选择性外延生长来形成半导体层110。可以使用气相外延(VPE)、分子束外延(MBE)、液相外延(LPE)或其他合适的工艺从气态或液态前体生长半导体层110。在本发明的一些实施例中,用于沉积外延半导体材料的气体源包括含硅气体源和含锗气体源。硅气源可选自硅烷、乙硅烷、丙硅烷、四硅烷、六氯乙硅烷、四氯硅烷、二氯硅烷、三氯硅烷、甲基硅烷、二甲基硅烷、乙基硅烷、甲基二硅烷、二甲基二硅烷、六甲基二硅烷及其组合。锗气源可选自锗烷、二锗烷、卤代锗烷、二氯锗烷、三氯锗烷、四氯锗烷及其组合。可以利用这些气体源的组合形成外延硅锗合金层。可以使用诸如氢气、氮气、氦气和氩气的载气。
半导体层110可以在沉积期间(原位掺杂)掺杂或者在外延之后通过添加n型掺杂剂(例如,As、P、Sb)或p型掺杂剂(例如,Ga、B、BF2、Al)掺杂,取决于晶体管的类型(即,用于nFET的n型掺杂剂和用于pFET的p型掺杂剂)。半导体层110中的掺杂剂浓度可以在1x1019cm-3至2x1021 cm-3的范围内,或者在1x1020 cm-3至1x1021cm-3的范围内。
图2描述了根据本发明的一个或多个实施例的在制造CMOS器件的方法的中间操作期间在NMOS区域104中形成nFET鳍片200和在PMOS区域106中形成pFET鳍片202之后的结构100的横截面图。可以使用已知的前端(FEOL)制造技术在衬底102上形成nFET鳍片200和pFET鳍片202。
在本发明的一些实施例中,图案化硬掩模204以暴露NMOS区域104中的衬底102的部分。然后可以使用蚀刻工艺(可以是湿法蚀刻工艺、干法蚀刻工艺或其组合)去除衬底102的暴露部分以形成多个半导体鳍片。以类似的方式,可以在PMOS区域106中图案化硬掩模206以暴露半导体层110的部分。可以使用湿法蚀刻、干法蚀刻或其组合来去除半导体层110的暴露部分。在本发明的一些实施例中,在去除半导体层110的部分之后去除衬底102的暴露部分。以这种方式,提供了具有顶部208的pFET鳍202(由具有第一锗浓度的半导体层110形成)以及底部210(由衬底102形成)。在本发明的一些实施例中,使用对硬掩模204和206具有选择性的的RIE同时对nFET鳍片200和pFET鳍片202图案化。
nFET鳍片200和pFET鳍片202均可具有1nm至150nm的高度。在本发明的一些实施例中,pFET鳍片202的顶部208形成为约50nm的高度。每个鳍片的宽度可以为5nm至40nm。鳍片可以以10nm至100nm的间距分开。
图3描述了根据本发明的一个或多个实施例的在制造CMOS装置的方法的中间操作期间在衬底102上方形成浅沟槽隔离(STI)300之后的结构100的横截面图。STI 300形成在衬底102上方并且在nFET鳍片200和pFET鳍片202之间。STI 300可以是任何合适的电介质材料,例如氧化硅,并且可以使用任何合适的工艺形成。在本发明的一些实施例中,STI 300在硬掩模204和206的表面上方过满,然后使用例如CMP对硬掩模204和206的表面平面化。然后使用例如化学氧化物去除(COR)使STI 300凹陷。在本发明的一些实施例中,尽管其他有源鳍长度在本发明的预期范围内,STI 300凹进以提供约35nm的有源鳍长度(即,高于STI 300的鳍长度)。
图4描述了根据本发明的一个或多个实施例在制造CMOS器件的方法的中间操作期间在STI 300、nFET鳍片200和pFET鳍片202上方形成氧化物层400之后的结构100的横截面图。氧化物层400包括锗,并且可以使用ALD或其他合适的工艺共形地形成。在本发明的一些实施例中,氧化物层400共形地形成至约1nm至约10nm的厚度,例如5nm,但是其他厚度也在本发明的预期范围内。
图5描述了根据本发明的一个或多个实施例的制造CMOS器件的方法的中间操作期间在将pFET鳍片202的顶部部分208的一部分接触的氧化物层400的一部分转换成第二氧化物层500之后的结构100的截面图。在本发明的一些实施例中,根据反应(I),氧化物层400包括GeO2,pFET鳍202的顶部208包括SiGe20%,并且低温退火导致STI300的表面上方的顶部208中的一些Si氧化成氧化物层400(形成,即包括SiO2的第二氧化物层500和pFET鳍片202的顶部502):
(I)Si+Ge+2GeO2→Ge+2GeO+SiO2
有利地,该低温退火可以在约500摄氏度至约700摄氏度的温度下进行,而没有氧气环境。此外,在没有锗的情况下,在nFET鳍片200中硅和GeO2之间没有反应。以这种方式,反应(I)允许在CMOS兼容工艺中在pFET鳍片202中选择性地缩合锗,这可以在NMOS区间104和PMOS区间106两者之上执行。在低温退火之后,可以例如通过用惰性气体吹扫反应室来提取挥发性物质GeO。
在反应(I)之后,pFET鳍片202包括三个材料不同的部分:(1)由衬底102形成的底部部分210;(2)由Ge缩合形成具有高Ge浓度的顶部502;(3)具有低Ge浓度的中间部分504,其对应于顶部208的其余部分,即由于在STI 300表面下方而未与氧化物层400接触的那些顶部208的未反应部分。
在本发明的一些实施例中,底部210由硅衬底102形成,并且不包括锗或仅包含跟踪锗。pFET鳍片202的中间部分504由具有第一锗浓度的半导体层110形成。在本发明的一些实施例中,第一锗浓度为约20原子百分比。如前所述,反应方案(I)通过氧化硅选择性地缩合锗,以形成第二氧化物层500和pFET鳍片202的顶部502。因此,选择性缩合增加了顶部502相对于中部504的锗浓度。在本发明的一些实施例中,顶部502包括约40原子百分比的第二锗浓度,尽管其他浓度在本发明的预期范围内。通过增加氧化物层400的厚度,或者通过去除未反应的GeO2,并且重复该过程(即,在pFET鳍片202上形成新的氧化物层并且选择性地冷凝顶部502中的附加Ge),可以进一步增加第二锗浓度。
图6描述了根据本发明的一个或多个实施例的制造CMOS器件的方法的中间操作期间去除氧化物层400的未反应部分之后的结构100的截面图。可以使用湿法蚀刻、干法蚀刻或其组合来去除氧化物层400。在本发明的一些实施例中,氧化物层400被对nFET鳍片200、第二氧化物层500和/或pFET鳍片202的顶部部分502有选择性地去除。在本发明的一些实施例中,氧化物层400使用去离子水去除。
图7描述了根据本发明的一个或多个实施例的在制造CMOS器件的方法的中间操作期间在除去第二氧化物层500与硬掩模204与206之后的结构100的横截面图。可以使用湿法蚀刻、干法蚀刻或其组合来去除氧化物层500。在本发明的一些实施例中,使用对硬掩模204和206有选择性的RIE去除氧化物层500。然后可以使用已知的硬掩模开口(HMO)工艺去除硬掩模204和206。
在本发明的一些实施例中,清洁nFET鳍片200和pFET鳍片202的暴露表面以去除杂质和污染物。可以使用例如稀释的氢氟酸和/或盐酸清洁暴露的表面。
图8描述了根据本发明的一个或多个实施例的在制造CMOS器件的方法的中间操作期间在nFET鳍片200和pFET鳍片202上方形成导电栅极800(也称为公用或共用栅极)之后的结构100的横截面图。使用已知工艺在nFET鳍片200和pFET鳍片202的沟道区上方形成导电栅极800。导电栅极800可以是高k金属栅极(HKMG)并且可以包括例如界面层(IL)802、高k电介质膜804和功函数金属(WFM)806(IL802,高k电介质膜804和WFM 806统称为栅极堆叠)。
在传统器件中,栅极堆叠取决于晶体管的类型以及在nFET和pFET器件之间的差异。然而,如前所述,pFET 202的沟道区(即顶部502)包括具有高Ge浓度的SiGe(即Ge浓度约为40原子百分比)。该高Ge浓度降低了pFET 202的沟道区的带隙。因此,可以在NMOS和PMOS区104和106上形成具有n型功函数金属的公共栅极堆叠。
高k介电膜804可包括介电常数大于例如3.9、7.0或10.0的介电材料。用于高k介电膜804的合适材料的非限制性实例包括氧化物、氮化物、氮氧化物、硅酸盐(例如金属硅酸盐)、铝酸盐、钛酸盐,氮化物或其任何组合。介电常数大于7.0的高k材料的例子包括但不限于金属氧化物,例如氧化铪、氧化铪硅、氧氮化铪、氧化镧、氧化镧铝、氧化锆、氧化锆锆、锆氧氮化硅、氧化钽、氧化钛、氧化钡钡、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化钪铅锶和铌酸铅锌。高k介电膜804还可包括掺杂剂,例如镧和铝。高k介电膜804可以通过合适的沉积工艺形成,例如,CVD、PECVD、原子层沉积(ALD)、蒸发、物理气相沉积(PVD)、化学溶液沉积或其他类似工艺。高k介电膜804的厚度可以根据沉积工艺以及所使用的高k介电材料的组成和数量而变化。高k介电膜804的厚度可以为约0.5至约20nm。
WFM 806可以设置在高k电介质膜804上。P型功函数金属包括诸如钌、钯、铂、钴、镍和导电金属氧化物的组合物,或其任何组合。N型功函数金属包括诸如铪、锆、钛、钽,铝、金属碳化物(例如,碳化铪、碳化锆、碳化钛和碳化铝)、铝化物的组合物或其任何组合。
WFM 806可以是共用的WFM(即,WFM 806可以在NMOS和PMOS区域104和106上形成)并且可以包括单层或两个或更多个堆叠的功函数金属。在本发明的一些实施例中,共用的WFM 806是TiN/TiC/TiN三层功函数金属。在本发明的一些实施例中,TiC层包括Al。在本发明的一些实施例中,共用的WFM 806是含TiN/Al的合金/TiN的三层功函数金属。共用的WFM806可以通过合适的沉积工艺(例如,CVD、PECVD、PVD、电镀、加热或电子束蒸发和溅射)沉积。
可以在高k介电膜804和WFM 806上沉积用于导电栅极800的块状材料(栅极导体材料)以形成HKMG。合适的导电材料的非限制性例子包括铝(Al)、铂(Pt)、金(Au)、钨(W)、钛(Ti)或其任何组合。栅极导体材料可以通过合适的沉积工艺(例如,CVD,PECVD,PVD,电镀,热或电子束蒸发和溅射)沉积。
可以使用已知的金属化技术形成或沉积导电触点(栅极触点和源极/漏极触点,未示出)。在一些实施例中,ILD被图案化为具有开口沟槽,并且触点被沉积到沟槽中。在一些实施例中,触点过度填充到沟槽中,在ILD的表面上方形成过载。在一些实施例中,对ILD有选择性的CMP去除了过载。触点可以由任何合适的导电材料,例如金属(例如,钨、钛、钽、钌、锆、钴、铜、铝,铅、铂、锡、银、金)、导电金属复合材料(例如,氮化钽、氮化钛、碳化钽、碳化钛、碳化铝铝、硅化钨、氮化钨、氧化钌、硅化钴、硅化镍)、碳纳米管、导电碳,石墨烯或任何这些材料合适的组合制成。导电材料还可包括在沉积期间或之后掺入的掺杂剂。在一些实施例中,触点可以是铜并且可以包括阻挡金属衬垫。阻挡金属衬垫防止铜扩散到或掺杂周围的材料,这会降低它们的性能。例如,硅在掺杂铜时形成深层陷阱。理想的阻挡金属衬垫必须足以限制铜的扩散性,以使铜导体与周围材料化学隔离,并应具有高导电性,例如氮化钽和钽(TaN/Ta)、钛、氮化钛、钴、钌、和锰。
图9描述了根据本发明的一个或多个实施例的用于形成半导体器件的方法的流程图。如框902所示,在衬底上形成第一半导体鳍片。在框904处,在衬底上形成第二半导体鳍片并且与第一半导体鳍片相邻。根据本发明的一个或多个实施例,可以使用已知的前端(FEOL)制造技术来形成第一和第二半导体鳍。
如方框906所示,在第一和第二半导体鳍片上形成氧化物层。氧化物层可以包括锗,并且可以以与氧化物层400类似的方式形成(如图4所示)。
如方框908所示,在有效增加第二半导体鳍片的锗浓度的温度下对氧化物层退火。在本发明的一些实施例中,退火根据本发明的一个或多个实施例,使氧化物层中的锗凝聚成第二半导体鳍片的一部分。
这里参考相关附图描述了本发明的各种实施例。在不脱离本发明的范围的情况下,可以设计替代实施例。尽管在以下描述和附图中的元件之间阐述了各种连接和位置关系(例如,上方,下方,相邻等),但是本领域技术人员将认识到,本文描述的许多位置关系是方向独立的-即使方向改变,当所描述的功能也是被保持的。除非另有说明,这些连接和/或位置关系可以是直接的或间接的,并且本发明并不意图在这方面进行限制。类似地,术语“耦合”及其变形描述了在两个元件之间具有通信路径,并不意味着元件之间的直接连接而在它们之间没有中间元件/连接。所有这些变化都被认为是说明书的一部分。因此,实体的耦合可以指直接或间接耦合,并且实体之间的位置关系可以是直接或间接的位置关系。作为间接位置关系的示例,本说明书中关于在层“B”上形成层“A”的引用包括其中一个或多个中间层(例如,层“C”)在层“A”和层“B”之间的情况,只要层“A”和层“B”的相关特性和功能基本上不被中间层改变。
以下定义和缩写将用于解释权利要求和说明书。如这里所使用的,术语现在时的“包括”、进行时的“包括”、现在时的“包含”、进行时的“包含”、现在时的“具有”、进行时的“具有”、现在时的“含有”或进行时的“含有”或其任何其他变型旨在涵盖非、独家包容。例如,包含元素列表的组合物、混合物、工艺、方法,物品或装置不一定仅限于那些元素,而是可以包括未明确列出的或对这种组合物、混合物、工艺、方法,物品或装置隐含的其他元素。
另外,术语“示例性”在本文中用于表示“用作示例、实例或说明”。本文中描述为“示例性”的任何实施例或设计不一定被解释为比其他实施例或者设计优选或有利。术语“至少一个”和“一个或多个”应理解为包括大于或等于1的任何整数,即一个、两个、三个、四个等。术语“多个”应理解为包括任何整数,数字大于或等于2,即两个、三个、四个、五个等。术语“连接”可以包括间接“连接”和直接“连接”。
说明书中对“一个实施例”、“实施例”、“示例实施例”等的引用指示所描述的实施例可包括特定特征、结构或特性,但是每个实施例可以或可以不是包括特定的特征、结构或特性。而且,这些短语不一定是指同一实施例。此外,当结合实施例描述特定特征、结构或特性时,可以认为,无论是否明确描述,结合其他实施例来影响这样的特征、结构或特性是在本领域技术人员的知识范围内。
以下出于描述的目的,术语“上”、“下”、“右”、“左”,“垂直”,“水平”,“顶部”,“底部”及其派生词应涉及所描述的结构和方法,如附图中所示。术语“覆盖”,“顶上”,“顶部”,“定位在”或“定位在顶部”意味着第一元件(例如第一结构)存在于第二元件上(例如第二结构),其中在第一元件和第二元件之间可以存在诸如接口结构的中间元件。术语“直接接触”是指第一元件(例如第一结构)和第二元件(例如第二结构)在两个元件的接口处没有任何中间传导、绝缘或半导体层的情况下连接。
术语“约”,“基本上”,“大约”及其变体旨在包括与基于提交申请时可用设备的特定量的测量相关联的误差程度。例如,“约”可以包括给定值的±8%或5%,或2%的范围。
短语“对……有选择性”,例如“对第二元素具有选择性的第一元素”,是指第一元素可以被蚀刻,第二元素可以用作蚀刻停止层。
术语“保形的”(例如,保形层)是指该层的厚度在所有表面上基本相同,或者厚度变化小于该层的标称厚度的15%。
术语“外延生长和/或沉积”和“外延形成和/或生长”是指半导体材料(晶体材料)在另一半导体材料(晶体材料)的沉积表面上的生长,其中所生长的另半导体材料(晶体覆盖层)具有与沉积表面的半导体材料(种子材料)基本相同的晶体特性。在外延沉积工艺中,可以控制由源气体提供的化学反应物,并且可以设置系统参数,以使沉积原子以足够的能量到达半导体衬底的沉积表面以在表面上移动,从而使沉积原子将自身定向到沉积表面原子的晶体排列。外延生长的半导体材料可以具有与在其上形成外延生长的材料的沉积表面基本相同的晶体特性。例如,沉积在{100}方向为晶体表面上的外延生长的半导体材料可以呈现{100}方向。在本发明的一些实施例中,外延生长和/或沉积工艺可以选择性地在半导体表面上形成,并且不能在暴露的表面(例如二氧化硅或氮化硅表面)上沉积材料。
如前所述,为了简洁起见,本文中可能详细描述或不详细描述与半导体器件和集成电路(IC)制造有关的常规技术。然而,作为背景,现在将提供可用于实现本发明的一个或多个实施例的半导体器件制造工艺的更一般描述。尽管用于实现本发明的一个或多个实施例的特定制造操作可以是单独已知的,但是所描述的本发明的操作和/或所得结构的组合是唯一的。因此,结合根据本发明的半导体器件的制造描述的操作的独特组合利用在半导体(例如,硅)衬底上执行的各种单独已知的物理和化学工艺,其中一些工艺在紧接着的段落描述。
通常,用于形成将被封装到IC中的微芯片的各种工艺分为四大类,即膜沉积,去除/蚀刻,半导体掺杂和图案化/光刻。沉积是生长、涂覆或以其他方式将材料转移到晶片上的任何过程。可用的技术包括物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、分子束外延(MBE)以及最近的原子层沉积(ALD)等。去除/蚀刻是从晶片上去除材料的任何过程。实例包括蚀刻工艺(湿法或干法)、化学机械平坦化(CMP)等。例如,反应离子蚀刻(RIE)是一种干蚀刻,其通过将材料暴露在离子的轰击中,使离子的一部分从裸露的表面移走来使用化学反应等离子体去除材料,例如半导体材料的掩模图案。等离子体通常通过电磁场在低压(真空)下产生。半导体掺杂是通过掺杂(例如,晶体管源极和漏极),通常通过扩散和/或通过离子注入来改变电特性。这些掺杂工艺之后是炉退火或快速热退火(RTA)。退火用于激活注入的掺杂剂。两个导体(例如,多晶硅、铝、铜等)和绝缘体(例如,各种形式的二氧化硅、氮化硅等)的膜用于连接和隔离晶体管及其组件。半导体衬底的各个区域的选择性掺杂允许通过施加电压来改变衬底的导电性。通过创建这些各种组件的结构,可以构建数百万个晶体管并将它们连接在一起以形成现代微电子器件的复杂电路。半导体光刻是在半导体衬底上形成三维浮雕图像或图案,用于随后将图案转移到衬底。在半导体光刻中,图案由称为光致抗蚀剂的光敏聚合物形成。为了构建构成晶体管的复杂结构和连接电路的数百万个晶体管的许多导线,重复多次光刻和蚀刻图案转移步骤。印刷在晶片上的每个图案与先前形成的图案对齐,并且缓慢地构建导体、绝缘体和选择性的掺杂区域以形成最终器件。
附图中的流程图和框图显示了根据本发明的各种实施例的制造和/或操作方法的可能实施方式。该方法的各种功能/操作在流程图中由块表示。在一些替代实施方式中,框中提到的功能可以不按图中所示的顺序发生。例如,连续示出的两个方框实际上可以基本上同时执行,或者这些方框有时可以以相反的顺序执行,这取决于所涉及的功能。
以上已经描述了本发明的各实施例,上述说明是示例性的,并非穷尽性的,并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下,对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择,旨在最好地解释各实施例的原理、实际应用或对市场中的技术的技术改进,或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。
Claims (25)
1.一种用于形成半导体器件的方法,该方法包括:
在衬底上形成第一半导体鳍片;
在所述衬底上形成第二半导体鳍片;
在所述第一和第二半导体鳍片上形成氧化物层;以及
在有效增加第二半导体鳍片的锗浓度的温度下对所述氧化物层进行退火;
其中所述退火不会增加所述第一半导体鳍片的锗浓度。
2.如权利要求1所述的方法,其中所述氧化物层包括锗。
3.如权利要求2所述的方法,其中增加所述第二半导体鳍片的锗浓度还包括将所述氧化物层中的所述锗会聚到所述第二半导体鳍片的一部分中。
4.如权利要求1所述的方法,其中所述第二半导体鳍片包括硅锗。
5.如权利要求4所述的方法,其中增加所述第二半导体鳍片的锗浓度还包括氧化所述第二半导体鳍片中的硅。
6.如权利要求1所述的方法,还包括在所述第一和第二半导体鳍的沟道区上方形成共用导电栅极。
7.如权利要求6所述的方法,其中所述共用导电栅极包括TiN/TiAlC/TiN栅极堆叠。
8.如权利要求1所述的方法,其中所述第一半导体鳍片包括硅,并且所述第二半导体鳍片包括硅锗。
9.如权利要求8所述的方法,其中在所述退火之前,所述第二半导体鳍片还包括约20原子百分比的锗浓度。
10.如权利要求9所述的方法,其中在所述退火之后,所述第二半导体鳍片还包括约40原子百分比的锗浓度。
11.一种形成双通道互补金属氧化物半导体(CMOS)器件的方法,该方法包括:
使硅衬底的一部分凹陷;
在所述硅衬底的凹陷部分上形成包括硅锗的半导体层;
在所述衬底的未凹陷部分上形成第一半导体鳍片;
在所述半导体层上形成第二半导体鳍片;
在所述第一和第二半导体鳍片上形成包含锗的氧化物层;
在有效增加所述第二半导体鳍片的锗浓度的温度下对所述氧化物层进行退火;以及
在所述第一和第二半导体鳍片的沟道区上形成共用导电栅极。
12.如权利要求11所述的方法,其中所述第二半导体鳍片包括硅锗。
13.如权利要求11所述的方法,其中所述共用导电栅极包括TiN/TiAlC/TiN栅极堆叠。
14.如权利要求11所述的方法,其中在所述退火之前,所述第二半导体鳍片还包括约20原子百分比的锗浓度。
15.如权利要求14所述的方法,其中在所述退火之后,所述第二半导体鳍片还包括约40原子百分比的锗浓度。
16.一种用于形成半导体器件的方法,所述方法包括:
在衬底上形成包含硅和锗的半导体鳍片;
在所述半导体鳍片上形成包含锗的氧化物层;以及
在有效增加半导体鳍片的锗浓度的温度下对所述氧化物层进行退火;
其中所述退火根据以下反应来氧化所述半导体鳍片中的硅:
(I)Si+Ge+2GeO2→SiO2+Ge+GeO。
17.一种半导体器件,包括:
第一半导体鳍片,在衬底上;
第二半导体鳍片,与所述衬底上的第一半导体鳍片相邻,所述第二半导体鳍片包括底部、中间部分和顶部;以及
共用导电栅极,在所述第一和第二半导体鳍片的沟道区域上形成;
其中,所述中间部分包括第一浓度的第一材料,所述顶部包括第二浓度的第一材料;
其中所述第二浓度高于所述第一浓度。
18.如权利要求17所述的半导体器件,其中所述第一半导体鳍片和所述第二半导体鳍片的底部部分不包括所述第一材料。
19.如权利要求17所述的半导体器件,其中所述第一材料包括锗,所述第一浓度包括20原子百分比,并且所述第二浓度包括40原子百分比。
20.如权利要求17所述的半导体器件,其中所述共用导电栅极包括TiN/TiAlC/TiN栅极堆叠。
21.一种双通道互补金属氧化物半导体(CMOS),包括:
第一半导体鳍片,在衬底上,包括硅;
第二半导体鳍片,与所述衬底上的所述第一半导体鳍片相邻,所述第二半导体鳍片包括底部、中间部分和顶部;以及
共用导电栅极,在所述第一和第二半导体鳍片的沟道区域上形成;
其中,所述第二半导体鳍的所述底部不包括锗,所述第二半导体鳍的所述中间部分包括第一锗浓度,所述第二半导体鳍的所述顶部包括第二锗浓度。
22.如权利要求21所述的半导体装置,其中所述第一锗浓度小于所述第二锗浓度。
23.如权利要求22所述的半导体器件,其中所述第一锗浓度为20原子百分比,所述第二锗浓度为40原子百分比的锗。
24.如权利要求22所述的半导体器件,还包括浅沟槽隔离(STI),其形成在所述第一和第二半导体鳍之间并且在所述底部的表面上方。
25.如权利要求21所述的半导体器件,其中所述底部部分包括约10nm至约50nm的厚度,所述中间部分包括约15nm的厚度,并且所述顶部部分包括约35nm的厚度。
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GB2577190B (en) | 2020-09-09 |
US10229856B2 (en) | 2019-03-12 |
WO2018211379A1 (en) | 2018-11-22 |
US20180337098A1 (en) | 2018-11-22 |
GB2577190A (en) | 2020-03-18 |
DE112018000689T5 (de) | 2019-10-10 |
US20180337097A1 (en) | 2018-11-22 |
JP2020520108A (ja) | 2020-07-02 |
US10249540B2 (en) | 2019-04-02 |
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