CN106089782A - Parlor fan natural wind control system - Google Patents
Parlor fan natural wind control system Download PDFInfo
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- CN106089782A CN106089782A CN201610448468.6A CN201610448468A CN106089782A CN 106089782 A CN106089782 A CN 106089782A CN 201610448468 A CN201610448468 A CN 201610448468A CN 106089782 A CN106089782 A CN 106089782A
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Classifications
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
- F04D27/001—Testing thereof; Determination or simulation of flow characteristics; Stall or surge detection, e.g. condition monitoring
Abstract
The present invention relates to a kind of parlor fan natural wind control system, comprise multiple fan governor and a main controller.Each wall fan or the unified fixing sensing open air of stand fan blowing direction, produce the natural wind effect that each fan is uniformly coordinated, more effectively heat is sent open air, main controller is provided with infrared receiving circuit, when needing to change fan operational mode, infra-red remote control transmitter sends operational mode command signal, it is achieved pattern changes and various operation.
Description
(1) technical field:
The present invention relates to a kind of parlor fan natural wind control system, comprise multiple fan governor and a main controller.
Each wall fan or the unified fixing sensing open air of stand fan blowing direction, produce the natural wind effect that each fan is uniformly coordinated, more effectively
Open air is sent heat in ground.Main controller is provided with infrared receiving circuit, and when needing to change fan operational mode, infra-red remote control is sent out
Emitter sends operational mode command signal, it is achieved pattern changes and various operation.
(2) background technology:
Thered is provided the control system of power supply by power network, its each electronic equipment or intermodule are all to be communicated by special circuit,
Correct the timing time of each electronic equipment or electronic module, reach to run simultaneously purpose.Owing to using special circuit communication to make
Wiring complicates and increases cost, if timing time is not corrected by line traffic, then due to tradition timing error, runs number
After hour, its accumulation timing error can make system control action inconsistent, is likely to result in system crash, often changes at some and sets
Meter, its products application of occasion that wiring installation amount is big is restricted.
(3) summary of the invention:
Many parlors do not fill air-conditioning but dry desultorily with electric fan, and radiating effect is poor.The present invention relates to parlor
Fan natural wind control system, comprises multiple fan governor and a main controller.Each fan governor controls a ceiling fan
Or the unified fixing open air of pointing to of the electric fan such as wall fan or stand fan, each wall fan or stand fan blowing direction, blowing is unified in order, more
Effectively heat is sent open air.There is an air switch on the main switchboard of parlor, an electronics is installed after air switch
Switch, this electrical switch parallel connection isolating diode, and each installation one in the telecommunication circuit of main controller and each fan governor
Individual communications electronics switch, switch drive module.Main controller and each fan governor are respectively mounted cycle discriminator circuit, are used for producing
The lock in time of system keeps system acting consistent.During communication, main controller turns off electrical switch and connects its communications electronics switch,
Through isolating diode, civil power is sent into system, and system is in the half wave communication half-wave power supply state through electric lines of force, each fan control
Device is also when can't detect power network and being rectified the half-wave voltage signal that diode blocks, and system is in half-wave communications status, i.e. turns off
Fan power supply, connects communications electronics switch；Otherwise, when switching to before all-wave from half-wave, main controller is first sent out to each fan governor
Send switching command, turn off communications electronics switch connection fan power supply.Main controller is provided with infrared receiving circuit, and it is generally by producer
It is integrated in an element, being integrally forming infrared receiving terminal, when needing to change fan operational mode, infra-red remote control transmitter
Sending operational mode command signal, main controller mid-infrared receiving device receives the infrared command signal of infra-red remote control transmitter
Time, infrared signal is become the signal of telecommunication and delivers to pre-amplification circuit and be amplified, then after demodulated device, signal examining by it
Go out circuit to be detected by command signal, it is achieved pattern changes and various operation.Main controller selects running the mild wind of natural wind or temporary
Carrying out half-wave traffic operation during blow off wind, call duration time is the shortest, does not affect natural wind effect.The output warp of each fan governor
Phototube Coupling and bidirectional triode thyristor are serially connected with on former socket or switch, and electric fan inserts on socket or is connected in on-off circuit, real
Existing its load energized power and control of time, produce the natural wind effect that each fan is uniformly coordinated, and changes parlor design the most square
Just, wall paper line need not be broken.
The switch drive module of communications electronics switch is that one tunnel is used for each wind from electric power netting twine point two-way after resistance blood pressure lowering
Fan controller, it is connected to the single-chip processor i/o mouth of each fan governor through reversal connection diode, bears in clock timer timing to cycle
During half-wave, scan this I/O mouth, be in half-wave communications status without signal i.e. system.Another road is used for each fan governor
And main controller, communication therebetween is that this road is followed by d type flip flop through electric resistance partial pressure by controlling lock in time to keep keeping strokes
CLK end, the external interrupt mouth (INT0 or INT1) of the Q termination single-chip microcomputer of d type flip flop, in this, fracture is set to level triggers.D touches
Sending out the D end ground connection of device, its S end connects with the I/O mouth of single-chip microcomputer, and original state S end puts 1.When the positive square-wave signal of CLK end arrives
Time, its rising edge makes d type flip flop set to 0, and external interrupt mouth low level produces interrupts, and first makes S end set to 0 and make in interrupt service routine
It is 1 to close interruption that d type flip flop puts 1 i.e. Q end, then communicates, and communications electronics switch is connected to monolithic according to used communication mode
Machine corresponding port, and carry out signal condition, before sign off, S end puts 1 communication making out next cycle of interrupt latency, so week and
Renew and realize half wave communication.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three examination points and realizes sentencing the identification of cycle signal
Fixed, the recycling cycle time sets up lock in time, it is achieved main controller and the synchronous operation of each fan governor in system.
The cycle discriminator circuit structural representation of main controller and each fan governor is as in figure 2 it is shown, used hysteresis by two
The voltage comparator composition of comparator, all comprises filter circuit, the reference voltage of its voltage comparator in each voltage comparator
Thered is provided by mu balanced circuit.System arranges clock timer and synchrotimer.If be detected that adjacent two cycle signals are equal
It is true, then takes out the clock timer timing time between these two adjacent cycle signal zero passages, be sequentially stored in the cycle time
In memory element, this cycle time memory cell can deposit 100 cycle times, is often stored in a cycle time, all when being filled with
First remove the cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value to reflect
Cycle signal the most to be identified, to reduce the impact of power network frequency fluctuation, uses three to screen point simultaneously and reduces erroneous judgement probability.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.Cycle in the cycle positive half cycle ascent stage
At zero passage, i.e. screening point 0 and arrange voltage zero-cross detection module, it uses cycle positive half-wave signal to enter through electric resistance partial pressure, diode
The clock end CLK, the Q of d type flip flop that send into d type flip flop after one step isolation negative half period, signal condition terminate single-chip microcomputer external interrupt
Mouthful, this external interrupt mouth is arranged to level triggers, the D end ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, and this I/O mouth is put at ordinary times
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes d type flip flop Q end be 0, outside single-chip microcomputer
Fracture low level in portion, thus produce interruption, interrupt service routine performs instruction: described I/O mouth sets to 0, closes interruption, meter
Time, described I/O mouth puts 1, opens interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
Point 1 and the examination point 2 at 50% to 70% place are screened by 35% to 50% place.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, works as cycle
During voltage zero-cross, it is arranged on the output voltage of d type flip flop in the voltage zero-cross detection module V0 screening point 0 and jumps vanishing, produce
Raw interruption, records its zero crossing break period Th0；Hereafter, the output electricity of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Pressure, when week, wave voltage reached the threshold voltage of V1, output voltage saltus step from high to low, scanning records its bound-time Th1；
Voltage comparator V2 output voltage bound-time Th2 at point 2 screened in same scanning record, and with voltage zero-cross, Th0 is detected mould
Output voltage bound-time setting value Ts0 of block V0 is made comparisons；The output voltage bound-time of Th1 and voltage comparator V1
Output voltage bound-time setting value Ts2 of setting value Ts1 and Th2 and voltage comparator V2 is made comparisons respectively, if
In the range of allowable error, then this discriminator signal detected is true, is otherwise false.Above-mentioned judge discriminator signal as true time, calculate
During clock timer timing between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Between Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle signal
Being true, at this moment preserve Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing is to opening the break period between 16ms to 18.5ms
Open interruption during setting value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt.
After system boot, clock timer starts timing, when first cycle voltage zero-cross being detected, is arranged on examination
The output voltage saltus step of the voltage zero-cross detection module V0 of point 0, thus produce interruption, take out the time of cycle voltage over zero
T0 preserves, and is reset by clock timer and starts timing, and at this moment cycle time voltage crosses zero Th0 is 0, and single-chip microcomputer is by above-mentioned simultaneously
Method scans and judges discriminator signal.Due to detection is first cycle, and clock timer is to open when cycle voltage zero-cross
Beginning timing, the value of its Th0, Th1 and Th2 must deduct open the difference of break period setting value Tk plus cycle time 20ms, as
Really three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. for the first time open the break period takes Tk next time.Being otherwise fictitious time, now the clock timer time must continue detection plus T0.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving the cycle time of detection,
Therefore the clock timer timing time between twice cycle signal zero passage is to make comparisons with cycle time 20ms, it is determined that cycle signal
For true time, then it is to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, preserves the standard cycle time i.e. for the first time
20ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all when opening interruption by clock meter the most every time
Time device reset after restart timing, and be when opening interruption, the standard cycle time to be counted in synchrotimer, open interruption
Rear clock timer reset, otherwise judges cycle signal as fictitious time, now the clock timer time must add T1=T0+Tk, continue
Continuous first cycle of detection the most again.After first cycle signal of detection is very, recover above-described cycle
Signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, opens the break period and all open the break period at this next time
After, when meansigma methods Tz of time delay cycle time, open interruption, and have no progeny in opening time delay Tns time close and interrupt, pass is set when interrupting
Between be when cycle signal screen point 0 time do not produce interruption, at this moment must be at the setting time point more than Ts0 allowable error scope
Starting scanning, and scanning examination point 1 is with when screening point 2, voltage comparator output voltage does not produce saltus step, all interrupts in pass
Time Tns closes and interrupts and stop scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and weight after resetting
Newly start timing, close during timing to Tns and interrupt, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and when this cycle judges, discriminator signal is
Vacation, or the cycle time detected compare with meansigma methods Tz of cycle time and exceed setting cycle time error Tzv, or clock meter
Time device timing to when closing break period setting value Tns, the voltage zero-cross detection module non-saltus step of V0 output voltage, in not producing
Disconnected, then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time after Tz, open interruption, clock timer have no progeny in opening clearing and timing, during timing to Tns
Close and interrupt, judge the cycle signal true and false the most every time, though if false or this detection discriminator signal is true last time is false, then take
N, restores after N+1 in memorizer.
When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by N zero setting in memorizer, and recover to make
Using setting value Tks, the value at this moment taking (N+1) × 20ms is added in synchrotimer.
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by setting with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen a some signal true and false, can select: Th0, Th1, Th2 are
This cycle discriminator signal of true time is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true time, should
Cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, due to main controller and each fan in system
Controller, the Tz value of its detection may be different with N value, and at this moment, power network frequency cumulative error, when being likely to result in synchrotimer
Between cannot by true cycle signal being detected time corrected, when detecting that cycle signal is true time, at this moment use clock meter
Time device accumulative clocking value be directly added in synchrotimer, to reduce the asynchronous time of system, accumulative clocking value is N × Tz
+20ms.In the case of power network normal operation, N is much smaller than 25.
The cycle time error Tzv allowed and setting value flip-flop transition of voltage comparator output voltage, by test assessment
Take its meansigma methods to obtain.
(4) accompanying drawing explanation:
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural representation；
Fig. 3 is the circuit structure block diagram of parlor fan natural wind control system.
(5) detailed description of the invention:
Fig. 3 is that parlor fan natural wind control system circuit structure block diagram includes: main controller 10, communications electronics leave
Pass 11, switch drive module 12, infra-red remote control transmitter 13, electrical switch 14, electric fan 15, cycle are screened
Circuit 16, fan governor 17.Wherein communications electronics switch 11, switch drive module 12, cycle discriminator circuit
During in 16 and Fig. 2, single-chip microcomputer U0 is included in fan governor 17 and main controller 10 respectively.Electrical switch 14, logical
Letter electrical switch 11 uses bidirectional triode thyristor as switch.
Fig. 2 is the structural representation of cycle discriminator circuit 16, by: input circuit S0, voltage zero-cross detection module
V0, voltage comparator V1 and voltage comparator V2 are constituted.Single-chip microcomputer U0 refers to fan governor 17 and main controller
Single-chip microcomputer in 10.Input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to electricity
The input voltage that pressure comparator is the most stable.Single-chip microcomputer U0 uses 89C55WD.Voltage comparator V1, voltage comparator
V2 all uses special voltage comparator LM393, and its reference voltage is to use the mu balanced circuit of stabilivolt to carry out burning voltage to compare
The threshold voltage of device.
When mains AC voltage cycle signal zero passage, the output voltage saltus step of voltage zero-cross detection module V0, single
Sheet machine U0 produces interruption, records the break period, and single-chip microcomputer U0 is additionally operable to scanning voltage comparator V1 and voltage ratio simultaneously
The relatively output voltage of device V2, records bound-time, is used for judging power network cycle signal thus produces when output voltage saltus step
Raw lock in time.
Main controller 10 is provided with integration infrared receiving terminal, infra-red remote control transmitter 13 emission instruction signal, master
When integration infrared receiving terminal receives infrared command signal in control device 10, this infrared signal is become the signal of telecommunication and send front storing
Big circuit is amplified, then after demodulated device, signal detection circuit is detected by command signal, it is achieved various operations.
Claims (2)
1. the present invention relates to parlor fan natural wind control system, it is characterized in that, an electronic cutting is installed after air switch
Close, this electrical switch parallel connection isolating diode, main controller and each fan governor are respectively mounted cycle discriminator circuit, are used for producing
The lock in time of system, simultaneously communications electronics switch, switch drive module of each installation, each fan in its telecommunication circuit
The output of controller is serially connected with on former socket or switch through Phototube Coupling and bidirectional triode thyristor, and electric fan inserts on socket or is connected to
In on-off circuit；During communication, civil power sends into system through isolating diode, and the half wave communication half-wave that system is in through electric lines of force is powered
State, each fan governor also when can't detect power network and being rectified the half-wave voltage signal that diode blocks, connects communications electronics
Switch；Infra-red remote control transmitter sends operational mode command signal, and main controller mid-infrared receiving device receives infra-red remote control
During the infrared command signal of emitter, infrared signal is become signal of telecommunication implementation pattern and changes and various operation by it；Communication electricity
The switch drive module of son switch is that one tunnel is used for each fan governor, its warp from electric power netting twine point two-way after resistance blood pressure lowering
Reversal connection diode is connected to the single-chip processor i/o mouth of each fan governor, and when half-wave is born in clock timer timing to cycle, scanning should
I/O mouth, is in half-wave communications status without signal i.e. system, and another road is used for each fan governor and main controller, this road
Be followed by the CLK end of d type flip flop through electric resistance partial pressure, the external interrupt mouth of the Q termination single-chip microcomputer of d type flip flop, when the positive square wave of CLK end
When signal arrives, its rising edge makes d type flip flop set to 0, and external interrupt mouth low level produces interrupts, and communicates；
Cycle discriminator circuit is the positive half cycle ascent stage utilizing power network cycle, takes three and screens the some realization knowledge to cycle signal
Not judging, the recycling cycle time sets up lock in time, and system arranges clock timer and synchrotimer, if be detected that phase
Two the cycle signals faced are very, then when taking out the clock timer timing between these two adjacent cycle signal zero passages
Between, sequentially it is stored in cycle time memory cell, is often stored in a cycle time when being filled with 100 cycle time, the most first removes
The cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in, utilize Tz value to differentiate cycle to be identified
Signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, i.e. screen a little
0 arranges voltage zero-cross detection module, it use cycle positive half-wave signal through electric resistance partial pressure, diode isolate further negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after
Number rising edge makes d type flip flop Q end be 0, single-chip microcomputer external interrupt mouth low level, thus produces interruption, and remaining two comparator divides
Not being arranged on the cycle positive half cycle ascent stage, point 1 and the examination at 50% to 70% place are screened by 35% to 50% place of crest voltage
Point 2；
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, when week wave voltage
During zero passage, it is arranged on the output voltage of d type flip flop in the voltage zero-cross detection module screening point 0 and jumps vanishing, produce and interrupt, note
Record its zero crossing break period Th0；Hereafter, the output voltage of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning, works as cycle
When voltage reaches the threshold voltage of voltage comparator V1, output voltage saltus step from high to low, scanning records its bound-time
Th1；Same scanning record screens voltage comparator V2 output voltage bound-time Th2 at point 2, if described bound-time exists
In the range of allowable error, then this discriminator signal detected is true, is otherwise false, above-mentioned judges that discriminator signal, as true time, calculates
During clock timer timing between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Between Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle signal
Being true, at this moment preserve Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer；
When clock timer starts timing with cycle voltage zero-cross, then timing set to the break period of opening between 16ms to 18.5ms
Open interruption during value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt；
When first cycle voltage zero-cross being detected, the output voltage being arranged on the voltage zero-cross detection module screening point 0 is jumped
Becoming, thus produce interruption, the time T0 taking out cycle voltage over zero preserves, and is reset by clock timer and starts timing, this
Shi Zhoubo time voltage crosses zero Th0 is 0, and single-chip microcomputer scans as stated above and judges discriminator signal, its Th0, Th1 and Th2's
Value must deduct open the difference of break period setting value Tk plus cycle time 20ms, if three discriminator signals are true, takes out
The time T0 of cycle voltage over zero be stored in synchrotimer as initial time, open the break period the most for the first time next time
Taking Tk, be otherwise fictitious time, now the clock timer time must continue detection plus T0；
When first and adjacent second cycle voltage zero-cross being detected, it is determined that cycle signal is true time, then be to take 20ms to subtract
The difference of Th0 is added with synchrotimer timing time, and clock timer of having no progeny in opening resets, and otherwise judges that cycle signal is as false
Time, now the clock timer time must continue first cycle of detection the most again plus T1=T0+Tk, work as detection
First cycle signal be very after, recover above-described cycle signal determining；
If be detected that cycle signal is false, open the break period all after this opens the break period, when time delay cycle next time
Between meansigma methods Tz time open interruption, and have no progeny in opening time delay Tns time close and interrupt, arranging the pass break period is when cycle signal is discriminated
Not Wei fictitious time, close break period Tns close interrupt and stop scanning, Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and again opens after resetting
Beginning timing, closes during timing to Tns and interrupts；
Repeat said process, if described in the upper cycle signal that detects be true, when this cycle judges, discriminator signal is false,
Then closing when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, open the break period is next time
Opening the break period in last time and open interruption after Tz, clock timer is had no progeny in opening and is reset and timing, Central Shanxi Plain during timing to Tns
Disconnected, judge the cycle signal true and false the most every time, though if false or this detection discriminator signal is true last time is false, then take N, will
Restore in memorizer after N+1；
When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by N zero setting in memorizer, and recover use and set
Definite value Tks, the value at this moment taking (N+1) × 20ms is added in synchrotimer；
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing；
When judging to screen the some signal true and false, select: it is true that Th0, Th1, Th2 are this cycle discriminator signal of true time, or Th0 is
True and one of Th1, Th2 are true time, or Th1, Th2 are true time, and this cycle discriminator signal is true, depending on to judging that cycle signal is true
Depending on pseudo-different requirement, if N is more than a setting value between 25 to 70, the accumulative clocking value using clock timer is direct
Being added in synchrotimer, accumulative clocking value is N × Tz+20ms.
Parlor the most according to claim 1 fan natural wind control system, it is characterised in that including:
Main controller 10, communications electronics switch 11, switch drive module 12, infra-red remote control transmitter 13, electronic cutting
Pass 14, electric fan 15, cycle discriminator circuit 16, fan governor 17, wherein single-chip microcomputer U0 and communications electronics leave
Pass 11, switch drive module 12, cycle discriminator circuit 16 are included in fan governor 17 and main controller respectively
In 10；
Cycle discriminator circuit 16 is by input circuit S0, voltage zero-cross detection module V0, voltage comparator V1 and voltage
Comparator V2 is constituted, and input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to
The input voltage that voltage comparator is the most stable；
Main controller 10 is provided with integration infrared receiving terminal, infra-red remote control transmitter 13 emission instruction signal, main controller
10 through receiving and after signal processing, it is achieved various operations.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004120930A (en) * | 2002-09-27 | 2004-04-15 | Nishishiba Electric Co Ltd | Fault detection device of power conversion element |
| JP2006343171A (en) * | 2005-06-08 | 2006-12-21 | Yazaki Corp | Flying capacitor system voltage measuring device |
| CN101097653A (en) * | 2007-07-17 | 2008-01-02 | 东北大学 | Electric energy quality and electrical power system malfunction detection wave recording device and method |
| CN101176386A (en) * | 2005-05-16 | 2008-05-07 | 路创电子公司 | Two-wire dimmer with power supply and load protection circuit in the event of switch failure |
| CN101788615A (en) * | 2010-01-11 | 2010-07-28 | 中色科技股份有限公司 | Simple method for detecting phase sequence of three-phase industrial-frequency alternating current and detection device |
| CN103558476A (en) * | 2013-11-09 | 2014-02-05 | 张金木 | Detection system for high-voltage power grid running state |
-
2016
- 2016-06-20 CN CN201610448468.6A patent/CN106089782B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004120930A (en) * | 2002-09-27 | 2004-04-15 | Nishishiba Electric Co Ltd | Fault detection device of power conversion element |
| CN101176386A (en) * | 2005-05-16 | 2008-05-07 | 路创电子公司 | Two-wire dimmer with power supply and load protection circuit in the event of switch failure |
| JP2006343171A (en) * | 2005-06-08 | 2006-12-21 | Yazaki Corp | Flying capacitor system voltage measuring device |
| CN101097653A (en) * | 2007-07-17 | 2008-01-02 | 东北大学 | Electric energy quality and electrical power system malfunction detection wave recording device and method |
| CN101788615A (en) * | 2010-01-11 | 2010-07-28 | 中色科技股份有限公司 | Simple method for detecting phase sequence of three-phase industrial-frequency alternating current and detection device |
| CN103558476A (en) * | 2013-11-09 | 2014-02-05 | 张金木 | Detection system for high-voltage power grid running state |
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|---|---|
| CN106089782B (en) | 2017-06-30 |
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Effective date of registration: 20191204 Address after: 528300 1st floor, No.8, Xiangan North Road, Jun'an community residents committee, Jun'an Town, Shunde District, Foshan City, Guangdong Province Patentee after: Foshan Shunde nengqu Electronic Technology Co., Ltd Address before: The riverside road in Taijiang District of Fuzhou City, Fujian Province, No. 180 350004 Patentee before: Fuzhou Taijiang Chaoren Electronic Co., Ltd. |
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