CN106030790B - 晶片级封装(wlp)的浮置ubm焊球上的电感器设计 - Google Patents

晶片级封装(wlp)的浮置ubm焊球上的电感器设计 Download PDF

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Publication number
CN106030790B
CN106030790B CN201580008222.0A CN201580008222A CN106030790B CN 106030790 B CN106030790 B CN 106030790B CN 201580008222 A CN201580008222 A CN 201580008222A CN 106030790 B CN106030790 B CN 106030790B
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China
Prior art keywords
inductor
tube core
layer
terminal
semiconductor devices
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CN201580008222.0A
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English (en)
Chinese (zh)
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CN106030790A (zh
Inventor
Y·K·宋
Y·朴
X·张
R·D·莱恩
A·哈德吉克里斯托斯
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201580008222.0A 2014-02-12 2015-02-11 晶片级封装(wlp)的浮置ubm焊球上的电感器设计 Active CN106030790B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/179,202 US9245940B2 (en) 2014-02-12 2014-02-12 Inductor design on floating UBM balls for wafer level package (WLP)
US14/179,202 2014-02-12
PCT/US2015/015450 WO2015123321A1 (en) 2014-02-12 2015-02-11 Inductor design on floating ubm balls for wafer level package (wlp)

Publications (2)

Publication Number Publication Date
CN106030790A CN106030790A (zh) 2016-10-12
CN106030790B true CN106030790B (zh) 2019-08-20

Family

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CN201580008222.0A Active CN106030790B (zh) 2014-02-12 2015-02-11 晶片级封装(wlp)的浮置ubm焊球上的电感器设计

Country Status (7)

Country Link
US (1) US9245940B2 (https=)
EP (1) EP3105788A1 (https=)
JP (1) JP6440723B2 (https=)
KR (1) KR102389227B1 (https=)
CN (1) CN106030790B (https=)
BR (1) BR112016019464A2 (https=)
WO (1) WO2015123321A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12113038B2 (en) * 2020-01-03 2024-10-08 Qualcomm Incorporated Thermal compression flip chip bump for high performance and fine pitch
CN112366154A (zh) * 2020-11-06 2021-02-12 深圳市Tcl高新技术开发有限公司 芯片转移方法
US12381156B2 (en) 2021-11-10 2025-08-05 Samsung Electronics Co., Ltd. Redistribution substrate and semiconductor package including the same

Citations (5)

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Publication number Priority date Publication date Assignee Title
CN1543674A (zh) * 2001-08-14 2004-11-03 �ƶ���ɭ��ϵͳ�ɷ����޹�˾ 带有埋设电感器的无引线芯片承载器的制造结构和方法
US20070279176A1 (en) * 2006-05-31 2007-12-06 Broadcom Corporation On-chip inductor using redistribution layer and dual-layer passivation
CN101320726A (zh) * 2007-02-13 2008-12-10 卡西欧计算机株式会社 混入磁性体粉末的半导体装置及其制造方法
US20110031584A1 (en) * 2009-08-06 2011-02-10 Casio Computer Co., Ltd. Semiconductor device and manufacturing method thereof
US20130127060A1 (en) * 2011-11-18 2013-05-23 Cambridge Silicon Radio Limited Under bump passives in wafer level packaging

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ，半導体チップ群及びマルチチップモジュール
JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
JP3983199B2 (ja) * 2003-05-26 2007-09-26 沖電気工業株式会社 半導体装置及びその製造方法
US7619296B2 (en) * 2005-02-03 2009-11-17 Nec Electronics Corporation Circuit board and semiconductor device
JP2008205422A (ja) * 2006-07-03 2008-09-04 Nec Electronics Corp 半導体装置
JP2008124363A (ja) * 2006-11-15 2008-05-29 Nec Electronics Corp 半導体装置
JP2008210828A (ja) * 2007-02-23 2008-09-11 Casio Comput Co Ltd 半導体装置およびその製造方法
TWI397158B (zh) * 2007-02-13 2013-05-21 兆裝微股份有限公司 混有磁性體粉末之半導體裝置及其製造方法
JP5103032B2 (ja) * 2007-03-01 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置
US8471358B2 (en) 2010-06-01 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. 3D inductor and transformer
US9000876B2 (en) 2012-03-13 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor for post passivation interconnect

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1543674A (zh) * 2001-08-14 2004-11-03 �ƶ���ɭ��ϵͳ�ɷ����޹�˾ 带有埋设电感器的无引线芯片承载器的制造结构和方法
US20070279176A1 (en) * 2006-05-31 2007-12-06 Broadcom Corporation On-chip inductor using redistribution layer and dual-layer passivation
CN101320726A (zh) * 2007-02-13 2008-12-10 卡西欧计算机株式会社 混入磁性体粉末的半导体装置及其制造方法
US20110031584A1 (en) * 2009-08-06 2011-02-10 Casio Computer Co., Ltd. Semiconductor device and manufacturing method thereof
US20130127060A1 (en) * 2011-11-18 2013-05-23 Cambridge Silicon Radio Limited Under bump passives in wafer level packaging

Also Published As

Publication number Publication date
WO2015123321A1 (en) 2015-08-20
CN106030790A (zh) 2016-10-12
BR112016019464A2 (pt) 2018-05-08
EP3105788A1 (en) 2016-12-21
JP2017510063A (ja) 2017-04-06
KR20160120303A (ko) 2016-10-17
JP6440723B2 (ja) 2018-12-19
US9245940B2 (en) 2016-01-26
KR102389227B1 (ko) 2022-04-20
US20150228707A1 (en) 2015-08-13

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