BR112016019464A2 - projeto de indutor em esferas de ubm flutuantes para encapsulamento no nível de pastilha (wlp). - Google Patents

projeto de indutor em esferas de ubm flutuantes para encapsulamento no nível de pastilha (wlp).

Info

Publication number
BR112016019464A2
BR112016019464A2 BR112016019464A BR112016019464A BR112016019464A2 BR 112016019464 A2 BR112016019464 A2 BR 112016019464A2 BR 112016019464 A BR112016019464 A BR 112016019464A BR 112016019464 A BR112016019464 A BR 112016019464A BR 112016019464 A2 BR112016019464 A2 BR 112016019464A2
Authority
BR
Brazil
Prior art keywords
wlp
ubm
encapsulation
floating
inductor design
Prior art date
Application number
BR112016019464A
Other languages
English (en)
Portuguese (pt)
Inventor
Hadjichristos Aristotele
David Lane Ryan
Zhang Xiaonan
Kyu Song Young
Park Yunseo
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016019464A2 publication Critical patent/BR112016019464A2/pt

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/922Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9415Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/942Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
BR112016019464A 2014-02-12 2015-02-11 projeto de indutor em esferas de ubm flutuantes para encapsulamento no nível de pastilha (wlp). BR112016019464A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/179,202 US9245940B2 (en) 2014-02-12 2014-02-12 Inductor design on floating UBM balls for wafer level package (WLP)
PCT/US2015/015450 WO2015123321A1 (en) 2014-02-12 2015-02-11 Inductor design on floating ubm balls for wafer level package (wlp)

Publications (1)

Publication Number Publication Date
BR112016019464A2 true BR112016019464A2 (pt) 2018-05-08

Family

ID=52596604

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016019464A BR112016019464A2 (pt) 2014-02-12 2015-02-11 projeto de indutor em esferas de ubm flutuantes para encapsulamento no nível de pastilha (wlp).

Country Status (7)

Country Link
US (1) US9245940B2 (https=)
EP (1) EP3105788A1 (https=)
JP (1) JP6440723B2 (https=)
KR (1) KR102389227B1 (https=)
CN (1) CN106030790B (https=)
BR (1) BR112016019464A2 (https=)
WO (1) WO2015123321A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12113038B2 (en) * 2020-01-03 2024-10-08 Qualcomm Incorporated Thermal compression flip chip bump for high performance and fine pitch
CN112366154A (zh) * 2020-11-06 2021-02-12 深圳市Tcl高新技术开发有限公司 芯片转移方法
US12381156B2 (en) 2021-11-10 2025-08-05 Samsung Electronics Co., Ltd. Redistribution substrate and semiconductor package including the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710433B2 (en) * 2000-11-15 2004-03-23 Skyworks Solutions, Inc. Leadless chip carrier with embedded inductor
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ,半導体チップ群及びマルチチップモジュール
JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
JP3983199B2 (ja) * 2003-05-26 2007-09-26 沖電気工業株式会社 半導体装置及びその製造方法
US7619296B2 (en) * 2005-02-03 2009-11-17 Nec Electronics Corporation Circuit board and semiconductor device
US8717137B2 (en) 2006-05-31 2014-05-06 Broadcom Corporation On-chip inductor using redistribution layer and dual-layer passivation
JP2008205422A (ja) * 2006-07-03 2008-09-04 Nec Electronics Corp 半導体装置
JP2008124363A (ja) * 2006-11-15 2008-05-29 Nec Electronics Corp 半導体装置
JP2008210828A (ja) * 2007-02-23 2008-09-11 Casio Comput Co Ltd 半導体装置およびその製造方法
JP4492621B2 (ja) * 2007-02-13 2010-06-30 カシオ計算機株式会社 半導体装置およびその製造方法
TWI397158B (zh) * 2007-02-13 2013-05-21 兆裝微股份有限公司 混有磁性體粉末之半導體裝置及其製造方法
JP5103032B2 (ja) * 2007-03-01 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置
JP5536388B2 (ja) 2009-08-06 2014-07-02 株式会社テラプローブ 半導体装置およびその製造方法
US8471358B2 (en) 2010-06-01 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. 3D inductor and transformer
US8710658B2 (en) 2011-11-18 2014-04-29 Cambridge Silicon Radio Limited Under bump passive components in wafer level packaging
US9000876B2 (en) 2012-03-13 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor for post passivation interconnect

Also Published As

Publication number Publication date
WO2015123321A1 (en) 2015-08-20
CN106030790A (zh) 2016-10-12
EP3105788A1 (en) 2016-12-21
JP2017510063A (ja) 2017-04-06
KR20160120303A (ko) 2016-10-17
JP6440723B2 (ja) 2018-12-19
US9245940B2 (en) 2016-01-26
KR102389227B1 (ko) 2022-04-20
CN106030790B (zh) 2019-08-20
US20150228707A1 (en) 2015-08-13

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

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