CN106024741B - 用于处理芯片的方法 - Google Patents

用于处理芯片的方法 Download PDF

Info

Publication number
CN106024741B
CN106024741B CN201610165364.4A CN201610165364A CN106024741B CN 106024741 B CN106024741 B CN 106024741B CN 201610165364 A CN201610165364 A CN 201610165364A CN 106024741 B CN106024741 B CN 106024741B
Authority
CN
China
Prior art keywords
chip
metallization structure
side metallization
fixing means
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610165364.4A
Other languages
English (en)
Other versions
CN106024741A (zh
Inventor
M·施内甘斯
M·聪德尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN106024741A publication Critical patent/CN106024741A/zh
Application granted granted Critical
Publication of CN106024741B publication Critical patent/CN106024741B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C19/00Alloys based on nickel or cobalt
    • C22C19/03Alloys based on nickel or cobalt based on nickel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01007Nitrogen [N]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20105Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20106Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20107Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20108Temperature range 300 C=<T<350 C, 573.15K =<T< 623.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/20109Temperature range 350 C=<T<400 C, 623.15K =<T< 673.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/201Temperature ranges
    • H01L2924/2011Temperature range 400 C=<T<450 C, 673.15K =<T< 723.15K
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

在不同实施方式中提供了芯片。所述芯片可以包含芯片体和在所述芯片体的前侧上的正面金属化结构和/或在所述芯片体的背侧上的背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内是平坦的或者具有正的曲率半径。

Description

用于处理芯片的方法
技术领域
不同实施方式总体涉及用于处理芯片的方法。此外,不同实施方式涉及用于处理芯片的、能够改善芯片固定质量的方法。
背景技术
存在四种用于芯片固定的主要方法,即,金属填充聚合式的芯片固定、金属/烧结式芯片固定、共晶式芯片连接固定和基于焊接的芯片固定。在这些方法中,基于焊接的芯片固定广为流传,因为该方法在容易处理的同时在很大程度上是可靠的。此外,在基于焊接的芯片固定方法中使用的焊料不仅具有极好的导热性和导电性,而且由热膨胀系数(CTE=热膨胀系数)导致的错误匹配是低的。
然而,焊料中的空腔和气泡形成是在基于焊接的芯片固定方法中遇到的一个问题。空腔和气泡形成是基于焊接的芯片固定方法的不同参数的结果,例焊剂活性(例如排气)、合金选择和沉积量。如果在焊料界面和芯片的背侧金属化部中存在空腔,则可能出现芯片从焊料脱落。此外,空腔的存在也降低了导热性和导电性,这导致电阻更高和散热差。当芯片运行时,由于散热差而总是局部地在空腔周围环境中升温。其后果是,芯片可能在运行期间受损坏。这些问题对于在高电流下工作的功率装置和功率元件可能更显著。
因此,存在对于改善的方法的需求,所述改善的方法针对以上提到的要求。
发明内容
在不同实施方式中提供了芯片。所述芯片可以如此包含芯片体和在芯片体的前侧上的正面金属化结构和/或在芯片体的背侧上的背侧金属化结构,使得所述芯片是平坦的或者在芯片固定方法的温度范围内包含正的曲率半径。
附图说明
在附图中,类似附图标记通常在所有不同视图中涉及相同部分。附图不一定是按比例的,而重点通常在于阐述本发明的原理。在以下描述中参考以下附图描述了不同实施方式,其中:
图1示出装置的一种实施方式的示例性横截面视图;
图2示出在芯片固定方法期间具有凸起形状和载体上的焊料的装置的示例性横截面视图;
图3示出在芯片固定方法期间具有凹陷形状和载体上的焊料的装置的示例性横截面视图;
图4示出在芯片固定方法期间具有平坦的上表面和平坦的下表面和载体上的焊料的装置的示例性横截面视图;
图5示出用于处理装置的方法的示例性流程图;
图6示出示例性金属沉积系统;
图7示出用于处理装置的方法的示例性流程图;
图8示出用于在载体上固定芯片的方法的示例性流程图;
图9示出示例性测试情况;
图10示出示例性测试情况。
具体实施方式
以下的详细描述涉及附图,所述附图借助图解示出特定细节和实施方式,在这些特定细节和实施方式中能够利用本发明。在充分的细节中描述了这些实施方式,以使技术人员能够利用本发明。可以利用其他实施方式并且可以进行结构方面的、逻辑方面的和电学方面的改变,而不脱离本发明的保护范围。所述不同实施方式不彼此排斥,因为一些实施方式可以与一个或多个其他实施方式组合,以形成新的实施方式。因此,以下详细描述不应视为限定,而本发明的保护范围由权利要求限定。
提供了用于方法的不同实施方式,并且提供了用于装置的不同实施方式。显然,所述方法的基本特征也适用于所述装置,反之亦然。因此,出于简洁目的而省略了对这些特征的重复描述。
在此使用的措辞“至少一个”可以理解为包括大于或等于一的任何整数,即,“一”、“二”、“三”等。
在此使用的措辞“多个”可以理解为包括大于或等于二的任何整数,即,“二”、“三”、“四”等。
只要未另作说明,在此使用的措辞“层”可以理解为既包含在其中一个层是一个单独层的实施方式,也包含在其中一个层是包含多个子层的一个层堆叠的实施方式。
在此,词“示例性”用于表示“作为一个示例、一种情况或一个图解”的含义。在此被描述为“示例性”的任何一种实施方式或设计并不一定设计为相对于其他实施方式或设计是优选或有利的。
涉及“在”侧面或表面“上方”形成的沉积材料使用的措辞“在…上方”在此可以用于表示能够“直接在…上方”形成沉积材料的含义,例如与所涉及的侧面或表面直接接触。涉及“在”侧面或表面“上方”形成的沉积材料使用的词“在…上方”在此可以用于表示能够“间接在”具有一个或多个附加层的所涉及的侧面或表面“上方”形成沉积材料,所述一个或多个附加层被布置在所涉及的侧面或表面与沉积材料之间。
图1示出装置100的一种实施方式的示例性横截面视图。所述装置例如可以是半导体装置,如集成电路(IC)的半导体芯片或芯片。应理解,措辞“管芯(die)”和“芯片(chip)”在此作同义词使用。所述IC可以是任何一种类型的IC。例如,所述IC可以是功率IC或功率芯片,所述功率IC或功率芯片包括功率二极管、晶闸管、功率MOSFET、具有绝缘栅电极的双极型晶体管(IGBT)以及其他类型的装置或其组合。功率IC例如按照其低功率配对件(Gegenstück)的类似原理工作。然而,功率IC能够传输更大的电流量并且在截止状态中支持更大的反向偏置电压(Sperrvorspannung)。
如图1中所示,所示装置可以包含衬底110,所述衬底具有第一表面111和第二表面112。所述衬底110例如可以是半导体衬底,如硅衬底。也可以使用其他类型的衬底,例如SiGe、SiGeC或SiC。在不同实施方式中,所述衬底110可以是绝缘体上晶体衬底(COI-衬底),例如绝缘体上硅衬底(SOI-衬底)。也可以使用其他类型的COI衬底。所述衬底110例如可以是掺杂的或无掺杂的衬底。在不同实施方式中,所述衬底110可以具有小于约100μm的厚度,例如约60μm。
所述第一表面111例如可以是所述衬底110的上表面。所述上表面也称为装置——例如管芯或者芯片——的前侧。在不同实施方式中,所述上表面可以是经处理的衬底表面。所述上表面例如可以包括至少一个有源区。所述有源区可以包括掺杂区120和栅极区130。所述掺杂区120例如可以包含第一类型的掺杂物。第一类型的掺杂物可以由p型掺杂物组成。例如,掺杂区可以包含p型掺杂物,例如硼(B)、铝(Al)或其组合。替代地,第一类型的掺杂物可以是n型掺杂物,例如磷(P)、砷(As)、锑(Sb)或其组合。在不同实施方式中,所述掺杂区120相应于装置——例如功率MOSFET的扩散区(例如源极和漏极),而所述栅极区130相应于装置的栅极。
正面金属化结构150可以布置在衬底110的第一表面111上。所述正面金属化结构150可以是一个层、多个子层的一个堆叠或由多个堆叠组成,其中,每个堆叠具有多个子层。在不同实施方式中,正面金属化结构150可以布置在有源区上方。所述正面金属化结构150可以由金属或金属合金构成。所述正面金属化结构150可以由铜(Cu)、锡(Sn)、铝(Al)、金(Au)、银(Ag)、镍(Ni)、铂(Pt)或者其合金或者它们的组合组成。在不同实施方式中,所述正面金属化结构150可以是铜层。所述正面金属化结构150例如可以是装置的源极电极和栅极电极。
所述第二表面112例如可以是与第一表面111相对的衬底110的底部表面。所述底部表面也称为装置——例如管芯或者芯片——的背侧。在不同实施方式中,所述底部表面可以是经处理的衬底表面。例如,所述底部表面可以包括至少一个有源区。所述有源区可以包含掺杂区140。所述掺杂区例如可以包括第一类型的掺杂物。第一类型的掺杂物可以是p型掺杂物。例如,掺杂区可以包含p型掺杂物,例如硼(B)、铝(Al)或其组合。替代地,第一类型的掺杂物可以是n型掺杂物,例如磷(P)、砷(As)、锑(Sb)或其组合。在不同实施方式中,所述掺杂区相应于装置的扩散区(例如源极和漏极)。
背侧金属化结构160可以布置在衬底110的第二表面112上。所述背侧金属化结构160可以是一个层、多个子层的一个堆叠或由多个堆叠组成,其中,每个堆叠具有多个子层。在不同实施方式中,背侧金属化结构160可以布置在有源区上方。所述背侧金属化结构160可以由金属或金属合金构成。所述背侧金属化结构160可以由铜(Cu)、锡(Sn)、铝(Al)、金(Au)、银(Ag)、镍(Ni)、铂(Pt)或者其合金或者它们的组合组成。在不同实施方式中,所述背侧金属化结构160可以是镍钒层(NiV层)。所述背侧金属化结构160例如可以是装置的源极电极。
在不同实施方式中,所述正面金属化结构和背侧金属化结构可以是相同材料或不同材料。
在基于焊接的芯片固定方法中,经常使用例如400℃高的温度,以便将装置固定在载体上,例如印刷电路板(PCB)上。在芯片固定方法的这种高温下,流的排气可能在焊料中形成气泡。同时,芯片可能经历几何结构的变化,其中,所述芯片由于通过正面金属化结构与背侧金属化结构所施加的应力而偏离其平坦状态。
图2示出向下弯曲的芯片的示例性横截面视图,所述芯片在芯片固定方法期间具有凸起形状并且在载体上具有熔融焊料。所述正面金属化结构250和背侧金属化结构260可以具有比衬底210的CTE(热膨胀系数)更高的热膨胀系数(CTE)。因此,在可以在大约150℃至大约400℃的温度下实施的芯片固定方法期间,正面金属化结构250和背侧金属化结构260可能宏观上比衬底210更强地膨胀。然而,所述正面金属化结构250和背侧金属化结构260可能受衬底210限制,因为衬底210具有更小的CTE。其结果是,所述正面金属化结构250和背侧金属化结构260可能在芯片固定方法期间受到应力。也就是说,所述正面金属化结构和背侧金属化结构“希望”在芯片固定方法期间膨胀。在在衬底210上布置的正面金属化结构和背侧金属化结构中应力的存在可能引起衬底210弯曲。
常规上,在可在大约150℃至大约400℃的温度下实施的芯片固定方法期间,通过正面金属化结构250在衬底210上施加的压应力可能强于通过背侧金属化结构260在衬底210上施加的压应力。其结果是,芯片200可能偏离其初始的平坦状态,其中,在熔融焊料280上方形成拱形,所述熔融焊料在芯片固定方法中被布置在载体270(例如PCB)上。
在假设根据笛卡尔坐标系芯片的长度沿着x方向并且高度沿着y方向的情况下,经形变的芯片200可能向下沿着负的y方向弯曲,例如芯片200的中心点比芯片的边缘进一步远离载体270。如从芯片的前侧看上去,所述经形变的芯片可以具有凸起形状。在假设芯片被布置在曲率中心点与载体270之间的情况下,所述经形变的芯片的曲率半径因此是负的,因为芯片向下沿着负的y方向弯曲。也就是说,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,所述经形变的芯片200可能具有负的曲率半径。
由于通过凸起的芯片形成的位于上方的拱形所产生的气流和压力,在芯片固定方法期间气泡290不能从熔融焊料280向上和向外逸出。因此可能围绕焊料280的中心点积聚气泡290。当焊料280在芯片固定方法期间持续凝固时,所俘获的气泡290可能成为空腔并且持久地残留在已凝固的焊料280中,所述已凝固的焊料将芯片200固定在载体270上。
空腔的存在可能降低导热性和导电性,这导致局部的高电阻并导致差的散热。因此当芯片运行时,该芯片可能由于差的散热而总是升温。其后果是,芯片可能在运行期间损坏。这些问题对于具有在大电流下工作的薄衬底(例如大约60μm)的功率装置和功率组件——例如功率IC可能更重要。由于非常薄的衬底,在空腔周围环境中的局部升温变得危险。这样的局部升温可能在运行期间损坏芯片。
图3示出向上弯曲的芯片的示例性横截面视图,所述芯片在芯片固定方法期间具有凹陷形状并且在载体上具有熔融焊料。所述正面金属化结构350和背侧金属化结构360可以具有比衬底310的CTE更高的热膨胀系数(CTE)。因此,在可以在大约150℃至大约400℃的温度下实施的芯片固定方法期间,正面金属化结构350和背侧金属化结构360可能宏观上比衬底310更强地膨胀。然而,所述正面金属化结构350和背侧金属化结构360可能受衬底310限制,因为衬底310具有更小的CTE。其结果是,所述正面金属化结构350和背侧金属化结构360可能在芯片固定方法期间受到应力。也就是说,所述正面金属化结构和背侧金属化结构“希望”在芯片固定方法期间膨胀。根据这里描述的不同实施方式,可能提高通过背侧金属化结构360施加到衬底310上的压应力。也就是说,可以如此提高通过背侧金属化结构360施加到衬底310上的压应力,使得其比通过正面金属化结构350施加到衬底310上的压应力更强。其结果是,芯片300可能偏离其初始的平坦状态,其中,在熔融焊料380上方形成倒拱形,所述熔融焊料在芯片固定方法中被布置在载体370(例如PCB)上。
在假设根据笛卡尔坐标系芯片的长度沿着x方向并且高度沿着y方向的情况下,经形变的芯片300可能向上沿着正的y方向弯曲,例如芯片的中心点比芯片的边缘更接近载体370。如从芯片的前侧看,所述经形变的芯片可以具有凹陷形状。因此,在假设芯片布置在曲率中心点与载体370之间的情况下,所述经形变的芯片的曲率半径是正的,因为芯片向上沿着正的y方向向上弯曲。也就是说,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,所述经形变的芯片300可能具有正的曲率半径。在不同实施方式中,所述正的曲率半径可以处于大约0.5m至大约3m的范围内,这相当于在长度为100mm(沿x方向)下具有距弧上最低点在从大约5μm至大约25μm范围内的垂直偏差(沿y方向)的弧(或弯曲表面)。
由凹陷的芯片300形成的位于上方的倒拱形使得气泡390能够在芯片固定方法期间从熔融焊料380向上和向外逸出。其结果是,当焊料280在芯片固定方法期间持续凝固时,大部分气泡390能够从熔融焊料380逸出。因此,能够在已凝固的焊料中存在较少的空腔并且显著增大芯片的可靠性。
图4示出平坦的芯片的示例性横截面视图,所述芯片在芯片固定方法期间具有平坦的上表面和平坦的底部表面并且在载体上具有熔融焊料。在可在大约150℃至大约400℃的温度下实施的芯片固定方法期间,通过正面金属化结构450施加到衬底410上的压应力可能基本上与通过背侧金属化结构460施加到衬底410上的压应力相同。其结果是,芯片400可以在熔融焊料480上方保持其初始的平坦状态。也就是说,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,所述芯片400能够保持其初始的平坦状态。
类似于图3中所示的具有凹陷形状的芯片300,芯片400使得气泡490能够在芯片固定方法期间从焊料480向上和向外逸出。其结果是,能够在已凝固的焊料中存在较少的空腔并且显著增大芯片的可靠性。
图5示出用于根据不同实施方式处理芯片的方法的示例性流程图500,从而使芯片如图3和4所示那样在芯片固定方法期间具有凹陷形状或者保持其初始的平坦状态。应注意,在对图5的讨论中可以继续参考图3和4中所示的元件和附图标记。
如图5中502所示,能够在芯片的前侧上形成正面金属化结构和/或能够在芯片的背侧上如此形成背侧金属化结构,使得所述芯片是平坦的或者在芯片固定方法的温度范围内具有正的曲率半径。
在不同实施方式中,在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构可以包括在芯片的前侧和/或背侧上方沉积金属。所述金属可以由铜(Cu)、锡(Sn)、铝(Al)、金(Au)、银(Ag)、镍(Ni)、铂(Pt)或者其合金或者它们的组合组成。在不同实施方式中,可以将铜用于沉积正面金属化结构,并且将镍钒层(NiV)用于沉积背侧金属化结构。
在不同实施方式中,例如可以通过蒸镀(Aufdampfen)实施金属沉积,但不限于此。应理解,可以使用各种合适的沉积方法、技术和系统,以便实施在此包括的公开内容的教导。
图6示出示例性金属沉积系统600。出于图解目的,如其所示地简化了所述示例性金属沉积系统600。例如省略或简化了众所周知的特征,以便阐明示例性实现的描述和本公开内容的实施方式,并且以便由此更好地阐述示例性实现和实施方式。
所述金属沉积系统600可以包括沉积室601,所述沉积室具有入口603和出口605。蒸镀气体(例如氩气或者任何其他惰性气体/稀有气体或可能对于进行反应的蒸镀有用的氮气)可以经过入口603导入所述沉积室601中,并且经过出口605排空。在所述室中可以提供蒸镀目标(或者源)607,例如在衬底609对面。所述蒸镀目标607可以包含要在衬底609的与蒸镀目标607相对置的表面上沉积的材料(例如金属或金属合金)。所述蒸镀目标607可以以负电压偏置,反之,所述衬底609可以以正电压偏置。
在不同实施方式中,所述衬底609可以是具有多个芯片的半导体晶片,所述多个芯片在所述半导体晶片上形成。所述芯片可以是设置用于高功率应用的功率芯片。对此,可以在芯片的前侧或背侧上布置正面金属化结构和背侧金属化结构。所述正面金属化结构和背侧金属化结构可以在使用不同的沉积方法和系统下形成,例如在使用其中之一、在图6中所示的沉积方法和系统下形成。
可以如此调节一个或多个沉积参数(例如包含方法气体的蒸镀参数),使得所述芯片在随后实施的芯片固定方法期间具有凹陷形状或保持其初始的平坦状态。例如可以如此调节一个或多个沉积参数,使得经沉积的正面金属化结构相比背侧金属化结构可以具有不同的特性。所述沉积参数可以包含蒸镀气体(溅射气体)、蒸镀气体压力、蒸镀电压(溅射电压)、衬底偏置电压(Vorspannung)等的组合。
在不同实施方式中,可以在沉积所述背侧金属化结构期间添加氮气(N2)。例如在沉积所述背侧金属化结构期间可以将N2气体添加至蒸镀气体(例如氩气或者任何其他惰性气体/稀有气体)。N2气体流量与惰性气体流量的比例例如可以在大约5%至大约50%的范围内。
在所沉积的背侧金属化结构中可以包括中性离子和气体原子作为杂质,所述中性离子和气体原子可以包含氮。所包括的杂质可以在背侧金属化结构中附加残留应力(固有应力)。所述残留应力就其而言可以提高背侧金属化结构在芯片固定方法期间施加到衬底上的压应力,所述芯片固定方法可以在例如150℃至400℃的特定温度范围内实施。在一种或多种实施方式中,在芯片固定方法期间,通过背侧金属化结构施加到衬底上的压应力可能强于通过正面金属化结构施加到衬底上的压应力。这种应力不均衡可能导致芯片经受几何结构的改变(即,向上弯曲),其中,所述芯片在芯片固定方法期间具有如图3中所示的凹陷形状。在其他不同实施方式中,在芯片固定方法期间,通过正面金属化结构施加到衬底上的压应力可以充分补偿通过背侧金属化结构施加到衬底上的压应力。其结果是,所述芯片可以如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
在不同实施方式中,在可以在沉积背侧金属化结构期间调节蒸镀气体的压力。例如可以在沉积背侧金属化结构期间将蒸镀气体的压力从第一压力范围调节到第二压力范围。第一压力范围可以高于第二压力范围。第一压力范围例如可以是大约0.5Pa至2Pa,而第二压力范围例如可以是大约0.05Pa至0.5Pa。
蒸镀气体的压力可以具有对沉积率和所沉积的背侧金属化结构的组成的影响。例如降低蒸镀气体的压力可以降低离子化的气体离子量。然而,所逐出的金属原子与气体离子之间的碰撞导致金属原子的自离子化,所述自离子化导致自身进行离子化的等离子体。所述金属离子能够以弹道方式撞击蒸镀目标并且将金属原子抛出(herausschleudern),所述金属原子具有高动能。其结果是,可以在衬底上形成具有高密度的背侧金属化结构。在可以例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,稠密的背侧金属化结构能够施加更多压应力到Si衬底上。在一种或多种实施方式中,在芯片固定方法期间,通过背侧金属化结构施加到衬底上的压应力可以强于通过正面金属化结构施加到衬底上的压应力。这种应力不均衡可能导致芯片经受几何结构的改变(即,向上弯曲),其中,所述芯片在芯片固定方法期间具有如图3中所示的凹陷形状。在其他不同实施方式中,在芯片固定方法期间,通过正面金属化结构施加到衬底上的压应力可以充分补偿通过背侧金属化结构施加到衬底上的压应力。其结果是,所述芯片可以如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
在不同实施方式中,可以在沉积背侧金属化结构期间调节所述蒸镀电压。例如可以在沉积背侧金属化结构期间将所述蒸镀功率从第一电压范围调节到第二电压范围。第一电压范围可以低于第二电压范围。第一电压范围例如可以是大约0.5kV至0.8kV,而第二电压范围例如可以是大约0.8kV至1.5kV。
蒸镀电压可以具有对沉积率和所沉积的背侧金属化结构的组成的影响。例如蒸镀电压的提高可以提高所逐出的金属原子的能量,并由此形成在衬底上具有高密度的背侧金属化结构。在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,稠密的背侧金属化结构能够施加更多压应力到衬底上。在一种或多种实施方式中,在芯片固定方法期间,通过背侧金属化结构施加到衬底上的压应力强于通过正面金属化结构施加到衬底上的压应力。这种应力不均衡可能导致芯片经受几何结构的改变(即,向上弯曲),其中,所述芯片在芯片固定方法期间具有如图3中所示的凹陷形状。在其他不同实施方式中,在芯片固定方法期间,通过正面金属化结构施加到衬底上的压应力可以充分补偿通过背侧金属化结构施加到衬底上的压应力。其结果是,所述芯片可以如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
在不同实施方式中,可以根据不同的产品要求,例如根据金属或金属合金的选择、衬底的选择和应用对一个或多个沉积参数区分优先次序并且可选地进行实施。在不同实施方式中,可以在相同时间——即同时实施一个或多个沉积参数。此外应注意,经调节的沉积参数位于所述方法的预给定的控制界限内。
为了图解目的,结合背侧金属化结构的形成描述了不同实施方式。然而应注意,所述教导也可以用于形成正面金属化结构。在不同实施方式中,在沉积正面金属化结构期间可以如此调节一个或多个沉积参数,使得芯片可以在芯片固定方法期间具有凹陷形状或者保持其初始的平坦状态。例如在形成正面金属化结构期间可以或者提高蒸镀气体的压力或者降低蒸镀电压或者实施两者,从而在芯片固定方法期间,通过背侧金属化结构施加到衬底上的压应力可以大于或基本等于通过背侧金属化结构施加到衬底上的压应力。
在不同实施方式中,在沉积正面金属化结构和背侧金属化结构期间可以如此调节一个或多个沉积参数,使得芯片可以在芯片固定方法期间具有凹陷形状或保持其初始的平坦状态。
在不同实施方式中,正面金属化结构和背侧金属化结构可以由具有不同厚度的相同金属或相同金属合金组成。例如正面金属化结构可以具有比背侧金属化结构小的厚度。因此,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,背侧金属化结构可以在衬底上施加更多压应力。其结果是,芯片可能经受几何结构的改变(即,向上弯曲),以便在芯片固定方法期间具有如图3中所示的凹陷形状,或者以便如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
在不同实施方式中,衬底的正面金属化部和背侧金属化部可以由具有不同热膨胀系数(CTE)的不同金属或金属合金组成。例如背侧金属化结构可以具有比正面金属化结构更大的CTE。因此,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,背侧金属化结构比正面金属化结构膨胀更多。其结果是,芯片可能经受几何结构的改变(即,向上弯曲),以便在芯片固定方法期间具有如图3中所示的凹陷形状,或者以便如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
在不同实施方式中,正面金属化结构和背侧金属化结构可以分别包括多个子层。根据通过各个子层引起的应力,每个子层可以由相同金属(或金属合金)或由不同金属组成,并且每个子层可以具有相同厚度或不同厚度,只要在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间实现如图3和4所示的状态。
在形成正面金属化结构和/或背侧金属化结构之后,具有多个芯片的衬底可以被切割。应理解,可以使用各种合适的切割方法、技术和系统,以便使所述多个芯片从衬底分别单独分离或者分开。
如图5中504所示,在芯片固定温度范围内实施芯片固定方法,以便将经分开的芯片固定在载体上。在不同实施方式中,芯片固定温度位于大约150℃至大约400℃的范围内,例如从大约250℃至大约350℃。如图3和4所示,所述芯片可以在芯片固定方法期间在一个或多个实施方式中具有凹陷形状或者保持其初始的平坦状态。
在不同实施方式中,所包括的杂质可以在背侧金属化结构中传递残留应力,所述杂质可以包括氮。所述残留应力可以提高背侧金属化结构在芯片固定方法期间施加到衬底上的压应力,所述芯片固定方法可以在例如150℃至400℃的特定温度范围内实施。因此,在芯片固定方法期间,通过衬底背侧金属化部施加到衬底上的压应力可以强于通过正面金属化结构施加到衬底上的压应力。其结果是,芯片可能偏离其初始的平坦状态。在不同实施方式中,芯片可能向上弯曲,其中,在芯片固定方法期间在熔融焊料上方形成倒拱形。经形变的芯片可以具有如图3中所示的凹陷形状。也就是说,经形变的芯片可以在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间具有正的曲率半径。
在不同实施方式中,在可以在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,具有高密度的背侧金属化结构可以施加更多压应力到衬底上,所述高密度可以通过如前面讨论地调节蒸镀气体压力和/或蒸镀电压实现。因此,通过背侧金属化结构施加到衬底上的压应力可以强于通过正面金属化结构施加到衬底上的压应力。其结果是,芯片可能偏离其初始的平坦状态。在不同实施方式中,芯片向上弯曲,以便在芯片固定方法期间在熔融焊料上方形成倒拱形。经形变的芯片可以具有如图3中所示的凹陷形状。也就是说,经形变的芯片可以在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间具有正的曲率半径。
背侧金属化结构可以具有比正面金属化结构更大的厚度。在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,背侧金属化结构可以施加更多压应力到衬底上。其结果是,芯片可能偏离其初始的平坦状态并向上弯曲,以便在芯片固定方法期间在熔融焊料上方形成倒拱形。如图3所示,经形变的芯片可以具有凹陷形状。也就是说,在例如200℃至400℃的特定温度范围内实施的芯片固定方法期间,经形变的芯片可以具有正的曲率半径。
背侧金属化结构可以具有比正面金属化结构更大的CTE和/或更大的厚度。在例如200℃至400℃的特定温度范围内实施的芯片固定方法期间,背侧金属化结构可能比正面金属化结构更多地膨胀。其结果是,芯片可能偏离其初始的平坦状态并向上弯曲,以便在芯片固定方法期间在熔融焊料上方形成倒拱形。经形变的芯片可以具有如图3中所示的凹陷形状。也就是说,在例如200℃至400℃的特定温度范围内实施的芯片固定方法期间,经形变的芯片可以具有正的曲率半径。
在其他不同实施方式中,在芯片固定方法期间,通过正面金属化结构施加到衬底上的压应力可以充分补偿通过背侧金属化结构施加的压应力。其结果是,所述芯片可以如图4中所示那样在芯片固定方法期间保持其初始的平坦状态。
如图3中所示,在例如150℃至400℃的特定温度范围内实施的芯片固定方法期间,通过凹陷的芯片形成的位于上方的倒拱形使得气泡能够由于排气从熔融焊料向上和向外逸出。如图4中所示,在芯片固定方法期间,平坦的芯片能够以类似方式使得气泡能够从焊料向上和向外逸出。其结果是,当焊料在芯片固定方法期间持续凝固时,气泡中的大多数能够从熔融焊料逸出。因此,能够在已凝固的焊料中存在较少的空腔并且显著增大芯片的可靠性。
在芯片固定方法之后,固定在载体上的芯片可以被冷却到低于芯片固定方法的温度范围的一温度上。在不同实施方式中,固定在载体上的芯片可以被冷却到室温上。当芯片在低于芯片固定方法的温度范围的、在范围150℃至280℃的范围内的温度的情况下被冷却到熔融焊料凝固温度时,在芯片固定方法期间具有凹陷形状的芯片可以返回到其初始的平坦状态。
在将芯片固定在载体上并且将芯片冷却到低于芯片固定方法温度的温度范围之后,可以实施常规的后端方法,例如底部填充(Unterfüllung)、包覆(Umhüllung)和包封(Einkapselung),以便制造封装。
图7示出用于根据不同实施方式处理芯片的方法的示例性流程图700,从而所述芯片如图3和4中所示那样在芯片固定方法期间具有凹陷形状或保持其初始的平坦状态。
在702中,可以如此在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构,使得所述芯片在芯片固定方法期间所提供的温度范围内是平坦的或者具有正的曲率半径。
在704中,可以在所述温度范围内实施芯片固定方法,以便将芯片固定在载体上。
在706中,可以将固定在载体上的芯片冷却到低于所述温度范围的一温度上。
图8示出用于根据不同实施方式将芯片固定在载体上的方法的示例性流程图800,从而所述芯片如图3和4中所示那样在芯片固定方法期间具有凹陷形状或保持其初始的平坦状态。
在802中,可以在芯片的前侧上形成正面金属化结构和/或可以在芯片的背侧上如此形成背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内具有非负的曲率半径。
在804中,可以在所述芯片固定方法的温度范围内实施芯片固定方法,以便将芯片固定在载体上。
在806中,可以将固定在载体上的芯片冷却到低于所述芯片固定方法的温度范围的一温度上。
已经实施了一个实验。所述实验包括多个测试情况。
图9示出示例性测试情况900。在所述测试情况900中使用的芯片(即,芯片A)包含经修改的背侧金属化结构。例如根据在此描述的不同实施方式修改所述背侧金属化结构。在芯片固定方法期间并在芯片固定方法之后邻近所述温度903地测量所述芯片A的曲率半径901。通过曲线905和907表示加热轮廓曲线和冷却轮廓曲线。如通过曲线905所示,芯片A的曲率半径保持为负直到温度大约为280℃,这表示所述芯片具有如图2中所示的凸起形状。另外,曲线905还示出在温度升高超过280℃之后,芯片A的曲率半径变成正的,这表示所述芯片具有如图3中所示的凹陷形状。如通过曲线907所示那样,在芯片固定方法后的冷却期间,所述芯片的曲率半径从正的变化到负的。
图10示出示例性测试情况1000。在所述测试情况1000中使用的芯片(即,芯片B)具有符合标准的(常规的)背侧金属化结构。在芯片固定方法期间并在芯片固定方法之后邻近所述温度1003地测量所述芯片B的曲率半径1001。通过曲线1005和1007表示加热轮廓曲线和冷却轮廓曲线。如通过曲线1005和1007所示那样,芯片B的曲率半径在整个芯片固定方法期间并在芯片固定方法之后保持为负,这表示所述芯片具有如图2所示的凸起形状。
根据一种实施方式,芯片可以包含:芯片体;在芯片体的前侧上的正面金属化结构和/或在芯片体的背侧上的背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内是平坦的或者具有正的曲率半径。
在所述实施方式的一个示例中,所述芯片体可以包含半导体衬底。
在所述实施方式的另一个示例中,所述芯片固定方法的温度范围可以从大约150℃至大约400℃。
在所述实施方式的另一个示例中,正面金属化结构的热膨胀系数可以小于背侧金属化结构的热膨胀系数。
在所述实施方式的另一个示例中,正面金属化结构和背侧金属化结构可以包含相同材料,并且正面金属化结构的厚度可以小于背侧金属化结构的厚度。
在所述实施方式的另一个示例中,正面金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层,并且背侧金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层。
在所述实施方式的另一个示例中,正面金属化结构可以包含铜、锡、铝、金、银、镍、铂、其合金或者它们的组合。
在所述实施方式的另一个示例中,背侧金属化结构可以包含铜、锡、铝、金、银、镍、铂、其合金或者它们的组合。
在所述实施方式的另一个示例中,正面金属化结构可以包含铜,背侧金属化结构可以包含镍钒。
在所述实施方式的另一个示例中,背侧金属化结构可以包含氮杂质。
在所述实施方式的另一个示例中,芯片的正的曲率半径可以从大约0.5m至大约3m。
根据一种实施方式,芯片装置可以包含:载体和固定在载体上的芯片。所述芯片可以如此包含芯片体和布置在芯片体的前侧上的正面金属化结构和/或布置在芯片体的背侧上的背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内是平坦的或者包含正的曲率半径。
在所述实施方式的一个示例中,所述载体可以包括印刷电路板。
在所述实施方式的另一个示例中,所述芯片体可以包含半导体衬底。
在所述实施方式的另一个示例中,所述芯片固定方法的温度范围可以从大约150℃至大约400℃。
在所述实施方式的另一个示例中,正面金属化结构的热膨胀系数可以小于背侧金属化结构的热膨胀系数。
在所述实施方式的另一个示例中,正面金属化结构和背侧金属化结构可以包含相同材料,并且正面金属化结构的厚度可以小于背侧金属化结构的厚度。
在所述实施方式的另一个示例中,正面金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层,并且背侧金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层。
在所述实施方式的另一个示例中,背侧金属化结构可以包含氮杂质。
根据另一种实施方式,芯片装置可以包含:载体和固定在载体上的芯片。所述芯片可以包含芯片体和布置在芯片体的前侧上的正面金属化结构和/或布置在芯片体的背侧上的背侧金属化结构。所述芯片可以相对载体的表面包含正的曲率半径。
根据一种实施方式,用于处理芯片的方法可以包含:如此在芯片的前侧上形成正面金属化结构和在芯片的背侧上形成背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内是平坦的或者包含正的曲率半径;并且在所述芯片固定方法的温度范围内实施芯片固定方法,以便将所述芯片固定在载体上。
在所述实施方式的一个示例中,所述芯片固定方法的温度范围可以从大约150℃至大约400℃。
在所述实施方式的另一个示例中,所述在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构可以包含在芯片的前侧上和/或在芯片的背侧上沉积金属并且调节一个或多个沉积参数。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包含调节蒸镀气体的压力。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包括调节蒸镀功率。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包含当将金属蒸镀在芯片的前侧或背侧上时导入氮气。
在所述实施方式的另一个示例中,正面金属化结构的热膨胀系数可以小于背侧金属化结构的热膨胀系数。
在所述实施方式的另一个示例中,正面金属化结构和背侧金属化结构可以包含相同材料,并且正面金属化结构的厚度可以小于背侧金属化结构的厚度。
在所述实施方式的另一个示例中,正面金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层,并且背侧金属化结构可以包含多个子层的一个堆叠或者包含多个堆叠,其中,每个堆叠可以具有多个子层。
根据另一种实施方式的用于处理芯片的方法可以包含:在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构,使得所述芯片在芯片固定方法期间所提供的温度范围内是平坦的或者包含正的曲率半径;在所述温度范围内实施芯片固定方法,以便将所述芯片固定在载体上;并且将固定在载体上的芯片冷却到低于所述温度范围的一温度上。
在所述实施方式的一个示例中,所述温度范围可以从大约150℃至大约400℃。
在所述实施方式的另一个示例中,在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构可以包含在芯片的前侧上和/或在芯片的背侧上沉积金属并且调节一个或多个沉积参数。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包含调节蒸镀气体的压力。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包含调节蒸镀功率。
在所述实施方式的另一个示例中,调节一个或多个沉积参数可以包括当将金属蒸镀在芯片的前侧或背侧上时导入氮气。
在所述实施方式的另一个示例中,正面金属化结构的热膨胀系数可以小于背侧金属化结构的热膨胀系数。
在所述实施方式的另一个示例中,正面金属化结构和背侧金属化结构可以包含相同材料,并且正面金属化结构的厚度可以小于背侧金属化结构的厚度。
根据一种实施方式,用于将芯片固定在载体上的方法可以包括:如此在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构,使得所述芯片在芯片固定方法的温度范围内包含非负的曲率半径;在所述芯片固定方法的温度范围内实施芯片固定方法,以便将所述芯片固定在载体上;并且将固定在载体上的芯片冷却到低于所述芯片固定方法的温度范围的一温度上。
在所述实施方式的一个示例中,所述芯片固定方法的温度范围可以从大约150℃至大约400℃。
在所述实施方式的另一个示例中,所述在芯片的前侧上形成正面金属化结构和/或在芯片的背侧上形成背侧金属化结构可以包含在芯片的前侧上和/或在芯片的背侧上沉积金属并且调节一个或多个沉积参数。
尽管关于特定实施方式示出和描述了本发明,但本领域技术人员应理解,可以进行对形式和细节的不同改变,而不脱离通过所附权利要求限定的本发明的精神和范围。因此,通过所附权利要求给出了本发明的范围,因此可以为此设置、包含并且包括位于权利要求的含义或等同范围中的所有变化。

Claims (19)

1.一种芯片,其包括:
芯片体;
在所述芯片体的前侧上的正面金属化结构和/或在所述芯片体的背侧上的背侧金属化结构,使得所述芯片被构造成在芯片固定方法的温度范围内是平坦的或者在芯片固定方法的温度范围内具有正的曲率半径,
其中,所述背侧金属化结构是导电的且包括杂质,所述杂质被配置成在芯片固定方法的温度范围内施加到芯片体上的压应力强于正面金属化结构的压应力。
2.根据权利要求1所述的芯片,其中,所述芯片体包括半导体衬底。
3.根据权利要求1所述的芯片,
其中,所述芯片固定方法的温度范围从150℃至400℃。
4.根据权利要求1所述的芯片,
其中,所述正面金属化结构的热膨胀系数小于所述背侧金属化结构的热膨胀系数。
5.根据权利要求1所述的芯片,
其中,所述正面金属化结构和所述背侧金属化结构包含相同材料;
其中,所述正面金属化结构的厚度小于所述背侧金属化结构的厚度。
6.根据权利要求1所述的芯片,
其中,所述正面金属化结构包括多个子层的一个堆叠或者包括多个堆叠,其中,每个堆叠具有多个子层;
其中,所述背侧金属化结构包括多个子层的一个堆叠或者包括多个堆叠,其中,每个堆叠具有多个子层。
7.根据权利要求1所述的芯片,其中,所述正面金属化结构包括铜、锡、铝、金、银、镍、铂、其合金或者它们的组合。
8.根据权利要求1所述的芯片,其中,所述背侧金属化结构包括铜、锡、铝、金、银、镍、铂、其合金或者它们的组合。
9.根据权利要求1所述的芯片,其中,所述正面金属化结构包括铜,并且所述背侧金属化结构包括镍钒。
10.根据权利要求9所述的芯片,其中,所述杂质包括氮。
11.根据权利要求1所述的芯片,其中,所述芯片的正的曲率半径从0.5m至3m。
12.一种芯片装置,其包括:
载体;
固定在所述载体上的芯片,其中,所述芯片包括:芯片体;布置在所述芯片体的前侧上的正面金属化结构和/或布置在所述芯片体的背侧上的背侧金属化结构,使得所述芯片被构造成在芯片固定方法的温度范围内是平坦的或者在芯片固定方法的温度范围内具有正的曲率半径,
其中,所述背侧金属化结构是导电的且包括杂质,所述杂质被配置成在芯片固定方法的温度范围内施加到芯片体上的压应力强于正面金属化结构的压应力。
13.根据权利要求12所述的芯片装置,其中,所述载体包括印刷电路板。
14.根据权利要求12所述的芯片装置,其中,所述芯片体包括半导体衬底。
15.根据权利要求12所述的芯片装置,
其中,所述芯片固定方法的温度范围从150℃至400℃。
16.根据权利要求12所述的芯片装置,
其中,所述正面金属化结构的热膨胀系数小于所述背侧金属化结构的热膨胀系数。
17.根据权利要求12所述的芯片装置,
其中,所述正面金属化结构和所述背侧金属化结构包括相同材料;
其中,所述正面金属化结构的厚度小于所述背侧金属化结构的厚度。
18.根据权利要求12所述的芯片装置,
其中,所述正面金属化结构包括多个子层的一个堆叠或者包括多个堆叠,其中,每个堆叠具有多个子层;
其中,所述背侧金属化结构包括多个子层的一个堆叠或者包括多个堆叠,其中,每个堆叠具有多个子层。
19.根据权利要求12所述的芯片装置,其中,所述杂质包括氮。
CN201610165364.4A 2015-03-26 2016-03-22 用于处理芯片的方法 Active CN106024741B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015104570.2A DE102015104570B4 (de) 2015-03-26 2015-03-26 Leistungs-chip und chipanordnung
DE102015104570.2 2015-03-26

Publications (2)

Publication Number Publication Date
CN106024741A CN106024741A (zh) 2016-10-12
CN106024741B true CN106024741B (zh) 2019-06-28

Family

ID=56890134

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610165364.4A Active CN106024741B (zh) 2015-03-26 2016-03-22 用于处理芯片的方法

Country Status (3)

Country Link
US (1) US10340227B2 (zh)
CN (1) CN106024741B (zh)
DE (1) DE102015104570B4 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6821263B2 (ja) * 2017-05-26 2021-01-27 株式会社ディスコ チップの曲率を測定する方法及び測定する装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101714538A (zh) * 2008-10-03 2010-05-26 三洋电机株式会社 半导体器件及其制造方法
US7843006B2 (en) * 2006-02-03 2010-11-30 Infineon Technologies Ag Semiconductor component arrangement having a power transistor and a temperature measuring arrangement
US8004072B2 (en) * 2008-10-15 2011-08-23 Qimonda Ag Packaging systems and methods

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5171348A (en) * 1989-06-20 1992-12-15 Matsushita Electric Industrial Co., Ltd. Die for press-molding optical element
JP2757805B2 (ja) 1995-01-27 1998-05-25 日本電気株式会社 半導体装置
JP3179065B2 (ja) 1999-02-02 2001-06-25 宮崎沖電気株式会社 半導体素子の製造方法
US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
JP3767585B2 (ja) 2003-07-11 2006-04-19 株式会社デンソー 半導体装置
US20050026332A1 (en) 2003-07-29 2005-02-03 Fratti Roger A. Techniques for curvature control in power transistor devices
JP2006245408A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 半導体集積回路および半導体装置
KR100962140B1 (ko) 2008-07-10 2010-06-10 현대자동차주식회사 차량의 혼 신호용 스위치 장치
JP5483906B2 (ja) 2009-03-04 2014-05-07 三菱電機株式会社 半導体装置およびその製造方法
JP5707709B2 (ja) 2009-03-23 2015-04-30 富士電機株式会社 半導体装置の製造方法
JP5545000B2 (ja) 2010-04-14 2014-07-09 富士電機株式会社 半導体装置の製造方法
DE102010020884B4 (de) * 2010-05-18 2018-03-15 Infineon Technologies Ag Halbleiterbauelement
US8846500B2 (en) * 2010-12-13 2014-09-30 Semiconductor Components Industries, Llc Method of forming a gettering structure having reduced warpage and gettering a semiconductor wafer therewith
US9735126B2 (en) 2011-06-07 2017-08-15 Infineon Technologies Ag Solder alloys and arrangements
JP2013098481A (ja) 2011-11-04 2013-05-20 Sumitomo Electric Device Innovations Inc 半導体装置
CN102655125A (zh) 2012-01-16 2012-09-05 中国科学院上海微系统与信息技术研究所 一种双面溅射金属层减小硅圆片翘曲的结构
US9465049B2 (en) * 2012-04-13 2016-10-11 James B. Colvin Apparatus and method for electronic sample preparation
US20140020743A1 (en) * 2012-07-23 2014-01-23 E I Du Pont De Nemours And Company Solar cell and manufacturing method thereof
US9123732B2 (en) * 2012-09-28 2015-09-01 Intel Corporation Die warpage control for thin die assembly
US9445519B2 (en) * 2013-01-15 2016-09-13 E I Du Pont De Nemours And Company Method of manufacturing thick-film electrode
DE102013006009B3 (de) * 2013-04-09 2014-07-31 Boa Balg- Und Kompensatoren-Technologie Gmbh Verfahren zum Herstellen eines Balgs und/oder Balg
US9650723B1 (en) * 2013-04-11 2017-05-16 Soraa, Inc. Large area seed crystal for ammonothermal crystal growth and method of making
US9653554B2 (en) * 2014-07-21 2017-05-16 Soraa, Inc. Reusable nitride wafer, method of making, and use thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7843006B2 (en) * 2006-02-03 2010-11-30 Infineon Technologies Ag Semiconductor component arrangement having a power transistor and a temperature measuring arrangement
CN101714538A (zh) * 2008-10-03 2010-05-26 三洋电机株式会社 半导体器件及其制造方法
US8004072B2 (en) * 2008-10-15 2011-08-23 Qimonda Ag Packaging systems and methods

Also Published As

Publication number Publication date
DE102015104570B4 (de) 2019-07-11
US10340227B2 (en) 2019-07-02
CN106024741A (zh) 2016-10-12
US20160284648A1 (en) 2016-09-29
DE102015104570A1 (de) 2016-09-29

Similar Documents

Publication Publication Date Title
US8211752B2 (en) Device and method including a soldering process
US10079155B2 (en) Semiconductor device manufacturing method
EP0935286A4 (en) COPPER CIRCUIT JUNCTION SUBSTRATE AND PROCESS FOR PRODUCING THE SAME
US10014237B2 (en) Circuit board having a heat dissipating sheet with varying metal grain size
GB823559A (en) Improvements in or relating to silicon semiconductor devices
CN101901828A (zh) 生产半导体器件的方法
US3664874A (en) Tungsten contacts on silicon substrates
CN105247666A (zh) 半导体装置及其制造方法
CN102403292A (zh) 叠层和集成电路装置
US2702360A (en) Semiconductor rectifier
CN106024741B (zh) 用于处理芯片的方法
US8314473B2 (en) Die backside standoff structures for semiconductor devices
KR20200023101A (ko) 열전 모듈
CN1123924C (zh) 芯片焊接焊料
JP2020077833A (ja) 炭化珪素半導体装置、炭化珪素半導体組立体および炭化珪素半導体装置の製造方法
CN114823368A (zh) 一种功率器件的制造方法
CN114823367A (zh) 一种半导体功率器件的制造方法
US3166449A (en) Method of manufacturing semiconductor devices
US20150001726A1 (en) Power semiconductor module
US3240571A (en) Semiconductor device and method of producing it
JP5601004B2 (ja) 半導体素子及び半導体素子の製造方法
US3066053A (en) Method for producing semiconductor devices
CN110544626B (zh) 碳化硅衬底上的电接触
US12080762B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US20240055375A1 (en) Silicon carbide semiconductor device and method of manufacturing semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant