CN105990375B - Goi衬底上的光电子和cmos集成 - Google Patents

Goi衬底上的光电子和cmos集成 Download PDF

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CN105990375B
CN105990375B CN201610137306.0A CN201610137306A CN105990375B CN 105990375 B CN105990375 B CN 105990375B CN 201610137306 A CN201610137306 A CN 201610137306A CN 105990375 B CN105990375 B CN 105990375B
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semiconductor
substrate
cladding layer
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CN105990375A (zh
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E·里欧班端
李宁
D·K·萨达纳
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International Business Machines Corp
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Abstract

一种用于将光电子器件和硅器件形成在单个芯片上的方法。该方法可以包括：在单个芯片的第一区域和第二区域中形成硅衬底；将锗层形成在至少第一区域中的衬底之上；将光电子器件形成在第一区域中的锗层上，光电子器件具有顶部熔覆层、底部熔覆层以及有源区域，底部熔覆层处在半导体层上，有源区域邻近波导并且处在底部熔覆层上，顶部熔覆层处在有源区域上；以及将硅器件形成在第二区域中的硅层上。

Description

GOI衬底上的光电子和CMOS集成
技术领域
本发明大体涉及半导体器件制造，并且更具体地涉及III-V半导体光电子器件和硅互补金属氧化物半导体(CMOS)器件在单个芯片上的形成和集成。
背景技术
随着微电子系统继续按比例地缩小，产生的电子互连件密度将必须在以极高时钟速度运行的同时适应增大的功率损耗、信号延迟和串扰。当前趋势指示在不到十年内由互连件消耗的功率可能变成在确定集成电路中的切换速度中的限制因素。为了克服这些问题，对光学互连件和伴随基于传统硅(Si)的微电子电路的系统的集成将是向前迈出的重大一步。基于光的芯片内和芯片间通信将大大减少延迟并通过消除电容性互连件损耗来降低功率消耗。改进的光电子集成还能够帮助增大在光通信系统中使用的收发器电路的速度，由此增大总体带宽。
发明内容
根据本发明的一个实施例，提供了一种方法。所述方法可以包括：在第一区域和第二区域中形成绝缘体上半导体(SOI)衬底，所述SOI衬底包括第一绝缘体层上的半导体层，并且所述第一绝缘体层处在衬底上；从所述第二区域去除所述半导体层和所述绝缘体层，其中所述衬底的顶表面被暴露；将第二绝缘体层形成在所述第一区域中的所述半导体层上；将衬底延伸层形成在所述第二区域中的被暴露的衬底上；将所述器件形成在所述衬底延伸层上；将覆盖所述器件的器件绝缘体层形成在所述第二区域中；将波导形成在所述第二绝缘体层中；以及将所述光电子器件形成在所述第一区域中，所述光电子器件具有底部熔覆层、有源区域以及顶部熔覆层，其中所述底部熔覆层处在所述半导体层上，所述有源区域处在所述底部熔覆层上，并且所述顶部熔覆层处在所述有源区域上。
根据本发明的另一实施例，提供了一种方法。所述方法可以包括：将叠层形成在第一区域中和第二区域中的衬底上，所述叠层包括所述衬底上的半导体层、所述半导体层上的第一绝缘体层、所述第一绝缘体层上的波导、所述波导上的第二绝缘体层、以及所述第二绝缘体层上的器件基层；将所述器件形成在所述第二区域中的所述器件基层上；将器件绝缘体层形成在所述第二区域中的所述器件上和所述器件基层上；以及将所述光电子器件形成在所述第一区域中，所述光电子器件具有底部熔覆层、有源区域以及顶部熔覆层，其中所述底部熔覆层处在所述半导体层上，所述有源区域处在所述底部熔覆层上，并且所述顶部熔覆层处在所述有源区域上。
根据本发明的另一实施例，提供了一种结构。所述结构可以包括：硅衬底，所述硅衬底处在单个芯片的第一区域和第二区域中；锗层，所述锗层处在至少所述第一区域中的所述衬底之上；所述光电子器件，所述光电子器件处在所述第一区域中的所述锗层上，所述光电子器件具有底部熔覆层、邻近波导的有源区域以及顶部熔覆层，其中所述底部熔覆层处在所述锗层上，所述有源区域处在所述底部熔覆层上，并且所述顶部熔覆层处在所述有源区域上；以及所述硅器件，所述硅器件处在所述第二区域中的硅层上。
附图说明
通过示例的方式给出且不旨在将本发明仅仅限于此的以下具体实施方式将结合附图被最好地理解，在附图中：
图1是根据示例性实施例的半导体结构的横截面视图；
图2是根据示例性实施例的半导体结构的横截面视图并且图示了从绝缘体上半导体(SOI)衬底的第一区域去除半导体层和第一绝缘体层；
图3是根据示例性实施例的半导体结构的横截面视图并且图示了器件在SOI衬底的第二区域中的形成；
图4是根据示例性实施例的半导体结构的横截面视图并且图示了波导在第一区域中的半导体层之上的形成；
图5是根据示例性实施例的半导体结构的横截面视图并且图示了光电子器件在第一区域中的形成；
图6是根据示例性实施例的半导体结构的横截面视图并且图示了光电子器件接触和器件接触的形成；
图7是根据示例性实施例的半导体结构的横截面视图并且图示了半导体结构的顶视图；
图8是根据示例性实施例的备选半导体结构的横截面视图并且图示了叠层在衬底上的形成；
图9是根据示例性实施例的备选半导体结构的横截面视图并且图示了器件在SOI衬底的第二区域中的形成；并且
图10是根据示例性实施例的备选半导体结构的横截面视图并且图示了光电子器件在SOI衬底的第一区域中的形成。
附图不一定是按比例绘制的。附图仅仅是示意性表示，不旨在描绘本发明的具体参数。附图旨在仅仅描绘本发明的典型实施例。在附图中，类似的附图标记表示类似的元件。
具体实施方式
在本文中公开了要求保护的结构和方法的详细实施例；然而，能够理解，所公开的实施例仅仅说明了可以以各种形成来体现的要求保护的结构和方法。然而，本发明可以以许多不同的形式来体现并且不应当被解释为限于本文中阐述的示例性实施例。更确切地说，提供了这些示例性实施例使得本公开内容将是透彻的和完整的并且将完全地将本发明的范围传达给本领域技术人员。在本说明书中，众所周知的特征和技术的细节可以被省略以避免不必要地使所呈现的实施例不清楚。
在说明书中对“一个实施例”、“实施例”、“示例实施例”等等的引用指示所描述的实施例可以包括特定特征、结构或特性，但是每个实施例可以不必包括特定特征、结构或特性。此外，这样的短语不一定指代相同实施例。另外，当结合实施例描述特定特征、结构或特性时，所承认的是，无论是否明确描述，结合其他实施例来影响这样的特征、结构或特性在本领域技术人员的知识范围内。
为了后文中描述的目的，如在附图中所定向的，术语“上”、“下”、“右”、“左”、“垂直”、“水平”、“顶部”、“底部”以及它们的衍生词将涉及所公开的结构和方法。术语“上覆”、“在...顶上”、“在顶部上”、“被定位在...上”或“被定位在...顶上”意味着诸如第一结构的第一元件被呈现在诸如第二结构的第二元件上，其中诸如接口结构的中介元件可以被呈现在第一元件与第二元件之间。术语“直接接触”意味着诸如第一结构的第一元件和诸如第二结构的第二元件在两个元件的接口处没有任何中间传导层、绝缘层或半导体层的情况下被连接。
为了不使本发明的实施例的呈现不清楚，在下面的具体实施方式中，本领域中已知的一些处理步骤或操作已经出于呈现和出于说明的目的被组合在一起并且在一些实例中可能尚未进行详细描述。在其他实例中，可能根本不描述本领域中已知的一些处理步骤或操作。应当理解，下面的描述更关注于本发明的各种实施例的区别特征或元件。
本发明大体涉及半导体器件制造，并且更具体地涉及III-V半导体光电子器件和硅互补金属氧化物半导体(CMOS)器件在单个芯片上的形成和集成。理想情况下，可能期望将III-V半导体光电子器件和硅CMOS器件形成在相同芯片上以创建针对光学互连件的新通路并减少生产时间和成本。将III-V半导体光电子器件和硅CMOS器件制造在单个芯片上的一种方式可以包括在单个芯片上的第一区域和第二区域中形成硅衬底，在第一区域中形成锗层，使用锗层作为种子层以形成III-V半导体光电子器件，以及使用第二区域中的硅作为种子层以形成硅CMOS器件。下面参考附图图1-10来详细描述通过其以将集成的III-V半导体光电子器件和硅CMOS器件形成在相同芯片上的一个实施例。应当注意，光电子器件可以包括例如光电子发送器件(诸如激光器)或光电子接收器件(例如探测器)，但是其他器件可以被使用。
参考图1，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以以提供绝缘体上半导体(SOI)衬底开始。
SOI衬底可以处在单个芯片的第一区域101中和第二区域103中。SOI衬底可以包括(从底部到顶部)衬底102、第一绝缘体层104和半导体层106。可以使用本领域中已知的任何SOI衬底形成技术(诸如举例而言，注氧隔离(SIMOX)或层转移)来形成SOI衬底。如果采用层转移工艺，则可选的打薄步骤可以跟在将两个半导体晶片粘合在一起之后。可选的打薄步骤能够将层的厚度减小到期望厚度。
衬底102可以包括：大块半导体衬底、分层半导体衬底(例如，Si/SiGe)、绝缘体上硅衬底(SOI)、或者绝缘体上SiGe衬底(SGOI)。衬底102可以包括本领域中已知的任何半导体材料，诸如举例而言，Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP或其他元素或化合物半导体。在实施例中，衬底102是大块硅衬底。衬底102可以包括例如n型、p型或无掺杂半导体材料并且可以具有单晶、多晶或非晶结构。
可以使用本领域中已知的任何沉积技术(诸如举例而言，离子注入、热或等离子氧化或氮化、化学气相沉积、和/或物理气相沉积)来将第一绝缘体层104形成在衬底102上。第一绝缘体层104可以为本领域中已知的任何介电材料，诸如举例而言，氧化物、氮化物或氮氧化物。第一绝缘体层104可以具有范围从约1nm到约500nm的厚度，但是其他厚度可以被使用。在实施例中，第一绝缘体层104是具有约200nm的厚度的SiO2。在另一实施例中，第一绝缘体层104可以包括包含氧化硅层和/或氮化硅层的多个介电层或介电叠层。应当注意，第一绝缘体层104还可以被称为掩埋介电层或掩埋氧化物(BOX)层。
可以使用本领域中已知的任何沉积技术(诸如举例而言，化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将半导体层106形成在第一绝缘体层104上。半导体层106可以是本领域中已知的任何半导体材料，诸如举例而言，Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或其他半导体。半导体层106可以具有范围从约1nm到500nm的厚度，但是其他厚度可以被使用。在实施例中，半导体层106是锗并且具有约100nm的厚度。
在实施例中，III-V半导体层可以随后被形成在(下面进一步描述的)半导体层106上。在硅与III-V半导体之间的晶格失配比在锗与III-V半导体之间更大；因此，锗可以是用作半导体层106以用于III-V半导体光电子器件的后续形成的更好的材料。
参考图2，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以包括从第二区域103去除半导体层106和第一绝缘体层104并且将第二绝缘体层108形成在半导体层106上。
应当注意，锗可以是用于III-V半导体光电子器件的生长的良好材料；然而，硅可以更适合于其他器件(诸如举例而言，CMOS器件)的形成。因此，锗可以从第二区域103被去除以允许硅器件的后续形成。
可以使用本领域中已知的任何蚀刻技术(诸如举例而言，光刻和/或反应离子蚀刻工艺)来从第二区域103去除半导体层106和第一绝缘体层104。衬底102的顶表面可以被暴露在第二区域103中。
可以使用本领域中已知的任何沉积技术(诸如举例而言，化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将第二绝缘体层108形成在半导体层106上。在实施例中，第二绝缘体层108通过将覆盖绝缘体层沉积在第一区域101中的半导体层106和第二区域103中的衬底102之上、随后通过从第二区域103去除覆盖绝缘体层的蚀刻工艺而被形成在半导体层106上。第二绝缘体层108可以保持处在半导体层106上并且保持处在半导体层106和邻近第二区域103的第一绝缘体层104的侧壁上。第二绝缘体层108可以为本领域中已知的任何介电材料，诸如举例而言，氧化物、氮化物或氮氧化物。第二绝缘体层108可以具有范围从约1μm到约5μm的厚度，但是其他厚度可以被使用。在实施例中，第二绝缘体层108是与第一绝缘体层相同的材料(例如，SiO2)，并且具有高于半导体层106约2μm的厚度。
参考图3，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以包括将器件112形成在第二区域103中的衬底延伸层110上。
可以使用本领域中已知的任何沉积技术(诸如举例而言，外延生长、化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将衬底延伸层110形成在第二区域103中的衬底102上。衬底延伸层110可以是本领域中已知的任何半导体材料，诸如举例而言，Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或其他半导体。在实施例中，衬底延伸层110是与衬底102相同的材料(例如，Si)，并且使用外延生长工艺将衬底延伸层110生长在第二区域103中的被暴露的衬底102上。
可以使用本领域中已知的任何器件形成技术(诸如举例而言，沉积、掩膜、和蚀刻工艺)来将器件112形成在衬底延伸层110上。器件112可以是本领域中已知的任何电子器件，诸如举例而言，Si CMOS器件、SiGe、或III-V通道MOSFET、双极结型晶体管、或本领域中使用的任何其他器件。在实施例中，器件112是Si CMOS器件。如本领域中已知的，器件112可以被用于向激光器或探测器发送信号。在图示的实施例中，三个器件112的两个集合被形成在衬底延伸层110上；然而，其他器件配置可以被使用。
可以使用本领域中已知的任何沉积技术(诸如举例而言，化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将器件绝缘体层109形成在器件112上。器件绝缘体层109可以是本领域中已知的任何半导体材料，诸如举例而言，Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或其他半导体。在实施例中，器件绝缘体层109是与第一绝缘体层104和第二绝缘体层108相同的材料(例如，SiO2)。可以使用本领域中已知的任何抛光技术就(诸如举例而言，化学机械抛光工艺)来使第二绝缘体层108和器件绝缘体层109的顶表面平整。
参考图4，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以包括将波导114形成在第一区域101中。
可以通过在第二绝缘体层108中蚀刻沟槽、将波导114形成在沟槽中并且将第二绝缘体层108重新形成在波导114之上来将波导114形成在第一区域101中。可以使用本领域中已知的任何蚀刻技术(诸如举例而言，反应离子蚀刻工艺)来在第二绝缘体108中形成沟槽。第二绝缘体层108的部分可以保持在沟槽之下。第二绝缘体层108的、保持在沟槽之下的部分可以具有约1μm的厚度。沟槽可以不延伸到第二区域103(即，在沟槽与第二区域103之间可以存在第二绝缘体层108的部分)。
可以使用本领域中已知的任何沉积技术(诸如举例而言，化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将波导114沉积在沟槽中。波导114可以是本领域中已知的任何波导材料，诸如举例而言，氮化物、氧化物或氮氧化物。在实施例中，波导114是SiN。
可以使用本领域中已知的任何沉积技术(诸如举例而言，化学气相沉积、等离子增强化学气相沉积、原子层沉积、或物理气相沉积)来将第二绝缘体层108重新形成在波导114上。可以使用本领域中已知的任何抛光技术就(诸如举例而言，化学机械抛光工艺)来使第二绝缘体层108的顶表面平整。在实施例中，第二绝缘体层108具有高于波导114的顶表面约1μm的厚度。
参考图5，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以包括将光电子器件115形成在第一区域101中的半导体层106上。
各种类型的结构已经被提倡用于半导体激光器和探测器；一个典型的结构是双异质结构。双异质结构是这样的结构，使得使用两种类型的不同化合物半导体，具有较小带隙的化合物半导体被夹在具有较大带隙的化合物半导体之间。
光电子器件115可以包括(从底部到顶部)底部熔覆层116、有源区域108以及顶部熔覆层117(例如，双异质结构)。光电子器件115可以具有范围从约1μm到约10μm的宽度(w)和范围从约100μm到约500μm的长度，但是其他尺寸可以被使用。
可以通过使用本领域中已知的任何蚀刻技术(诸如举例而言，光刻和/或反应离子蚀刻工艺)在第二绝缘体层108中蚀刻沟槽来形成光电子器件115。沟槽可以被形成在第一区域101中并且可以暴露半导体层106的顶表面和波导114的侧壁。
可以使用本领域中已知的任何沉积技术(诸如举例而言，外延生长或化学气相沉积)来将底部熔覆层116形成在沟槽中和半导体层106上。底部熔覆层116可以包括本领域中已知的任何半导体材料，诸如举例而言，IV半导体和/或III-V半导体。在实施例中，底部熔覆层116是AlGaAs。底部熔覆层116可以被原位掺杂并且可以是p型或n型的。
可以使用本领域中已知的任何沉积技术(诸如举例而言，外延生长或化学气相沉积)来将有源区域118形成在底部熔覆层116上。有源区域118可以包括本领域中已知的任何半导体材料，诸如举例而言，IV半导体和/或III-V半导体。在实施例中，有源区域118是使用外延生长而形成的GaAs。有源区域118可以具有与底部熔覆层116相同的晶格结构，然而，有源区域118可以具有较低的带隙。有源区域118可以与波导114的侧壁接触，使得信号能够在有源区域118与波导114之间流动。
可以使用本领域中已知的任何沉积技术(诸如举例而言，外延生长或化学气相沉积)来将顶部熔覆层117形成在有源区域118上。顶部熔覆层117可以包括本领域中已知的任何半导体材料，诸如举例而言，IV半导体和/或III-V半导体。顶部熔覆层117可以被原位掺杂并且可以是p型或n型的。在实施例中，顶部熔覆层117是与底部熔覆层116相同的材料(例如，AlGaAs)并且可以具有与底部熔覆层116相反的电荷(例如，p型顶部熔覆层117和n型底部熔覆层116)。顶部熔覆层117和底部熔覆层116可以被用作阻挡层，其可以将电子局限在有源区域118中。
参考图6，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，该方法可以包括穿过顶部绝缘体层形成光电子器件接触122和器件接触124。应当注意，出于说明性目的，第一绝缘体层104、第二绝缘体层108、器件绝缘体层109和顶部绝缘体层可以被示出为组合的绝缘体111。
可以使用本领域中已知的任何沉积技术(诸如举例而言，离子注入、热或等离子氧化或氮化、化学气相沉积、和/或物理气相沉积)来将顶部绝缘体层形成在光电子器件115上、第二绝缘体层108上以及器件绝缘体层109上。顶部绝缘体层可以是本领域中已知的任何介电材料，诸如举例而言，氧化物、氮化物或氮氧化物。在实施例中，顶部绝缘体层是与第一绝缘体层104、第二绝缘体层108以及器件绝缘体层109相同的材料(例如，SiO2)。
可以使用本领域中已知的任何蚀刻技术(诸如举例而言，光刻和/或反应离子蚀刻工艺)来将光电子器件接触沟槽和器件接触沟槽蚀刻在组合的绝缘体111中。光电子器件接触沟槽可以包括两个沟槽(例如，第一沟槽和第二沟槽)。第一沟槽可以延伸穿过组合的绝缘体111并且暴露顶部熔覆层116的顶表面。第二沟槽可以延伸穿过组合的绝缘体111并且暴露底部熔覆层117的顶表面。器件接触沟槽可以包括与使用的器件的数目相对应的沟槽的集合。器件接触沟槽可以延伸穿过组合的绝缘体111并且暴露器件112的顶表面。
可以使用本领域中已知的任何沉积技术(诸如举例而言，原子层沉积、分子层沉积、化学气相沉积、原位自由基辅助沉积、金属有机化学气相沉积、分子束外延、物理气相沉积、溅射、电镀、蒸发、离子束沉积、电子束沉积、激光辅助沉积、化学溶液沉积、或它们的任何组合)来将光电子器件接触122形成在光电子器件中。光电子器件接触122可以是本领域中已知的任何传导材料，诸如举例而言，钨、铝、银、金、它们的合金、或任何其他传导材料。硅化物层113可以排在光电子器件接触122的底部。
可以使用本领域中已知的任何沉积技术(诸如举例而言，原子层沉积、分子层沉积、化学气相沉积、原位自由基辅助沉积、金属有机化学气相沉积、分子束外延、物理气相沉积、溅射、电镀、蒸发、离子束沉积、电子束沉积、激光辅助沉积、化学溶液沉积、或它们的任何组合)来将器件接触124形成在器件接触沟槽中。器件接触124可以是本领域中已知的任何传导材料，诸如举例而言，钨、铝、银、金、它们的合金、或任何其他传导材料。硅化物层119可以排在器件接触124的底部。
参考图7，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构100的说明性图示。更具体地，(以上所描述的)光电子器件115可以包括激光器的集合115a和探测器的集合115b。激光器115a可以连接到探测器115b(即，芯片内连接)或连接到单独的探测器(即，芯片间连接)。在实施例中，存在两个第一区域101，一个区域具有激光器115a并且另一区域具有探测器115b，其中第二区域103处在两个第一区域101之间。应当注意，图7是结构100的顶视图。附加地，图7是可能的配置的示例性图示，但是其他配置可以被使用。
参考图8，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构200的说明性图示。更具体地，该方法可以以包括(从底部到顶部)衬底102、半导体层206，第一绝缘体层204、波导214、第二绝缘体208以及器件基层210的叠层开始。应当注意，结构200是波导在先的实施例(而非如图1-6中图示的器件在先的实施例)的例示。
半导体层206可以被形成在衬底102上。半导体层206可以是与图1中图示的半导体层106类似的材料，并且使用与图1中图示的半导体层106类似的工艺来被形成。第一绝缘体层204可以被形成在半导体层206上。第一绝缘体层204可以是与图1中图示的第一绝缘体层104类似的材料，并且使用与图1中图示的第一绝缘体层104类似的工艺来被形成。波导214可以被形成在第一绝缘体层104上。波导214可以是与图4中图示的波导114类似的材料，并且使用与图4中图示的波导114类似的工艺来被形成。第二绝缘体层208可以被形成在波导214上。第二绝缘体208可以是与图2中图示的第二绝缘体层108类似的材料，并且使用与图2中图示的第二绝缘体层108类似的工艺来被形成。器件基层210可以被形成在第二绝缘体层208上。器件基层210可以是与图3中图示的衬底延伸层110类似的材料，并且使用与图3中图示的衬底延伸层110类似的工艺来被形成。
叠层可以处在第一区域101中和第二区域103中。在实施例中，衬底102是硅，半导体层206是锗，第一绝缘体层204是SiO2，第二绝缘体层208是SiO2，波导214是SiN，并且器件基层210是硅。
参考图9，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构200的说明性图示。更具体地，该方法可以包括将器件212形成在第二区域103中的器件基层210上。器件212可以是与图3中图示的器件112类似的材料，并且使用与图3中图示的器件112类似的工艺来被形成。器件绝缘体层209可以被形成在器件212和器件基层210上。器件绝缘体层209可以是与图3中图示的器件绝缘体层109类似的材料，并且使用与图3中图示的器件绝缘体层109类似的工艺来被形成。
参考图10，根据实施例，在将III-V半导体光电子器件和Si CMOS器件制造在单个芯片上的方法的中间步骤期间提供了结构200的说明性图示。更具体地，该方法可以包括将光电子器件215形成在第一区域101中。
光电子器件215可以是与图5中图示的光电子器件115类似的材料，并且使用与图5中图示的光电子器件115类似的工艺来被形成。光电子器件215可以包括底部熔覆层216、有源区域218以及被形成在半导体层206的顶表面上的沟槽中的顶部熔覆层217。结构200可以类似于结构100；然而，波导214可以延伸到器件212之下。
将激光器/探测器形成在相同芯片上作为一个器件的一个益处可以包括更快的处理时间和更低的处理成本。锗可以被用作针对激光器/探测器的半导体种子层，因为在锗与III-V半导体之间的更紧密的晶格结构可以导致更少的压力和/或错配位错。锗可以被生长在硅衬底或氧化物上，使得锗能够桥接硅衬底与III-V半导体激光器/探测器之间的晶格失配中的间隙。
本发明的各种实施例的描述已经出于说明的目的被呈现，但是不旨在为穷举的或者限于所公开的实施例。在不背离本发明的范围和精神的情况下，许多修改和变型对于本领域技术人员将是显而易见的。本文中使用的术语被选择以最好地解释实施例的原理、市场中找到的技术上的实际应用或技术改进，或者以使得本领域其他普通技术人员能够理解本文中公开的实施例。

Claims (15)

1.一种用于半导体器件制造的方法，包括：
在第一区域和第二区域中形成绝缘体上半导体SOI衬底，所述SOI衬底包括第一绝缘体层上的半导体层，并且所述第一绝缘体层处在衬底上；
从所述第二区域去除所述半导体层和所述绝缘体层，其中所述衬底的顶表面被暴露；
将第二绝缘体层形成在所述第一区域中的所述半导体层上；
将衬底延伸层形成在所述第二区域中的被暴露的衬底上；
将所述器件形成在所述衬底延伸层上；
将覆盖所述器件的器件绝缘体层形成在所述第二区域中；
将波导形成在所述第二绝缘体层中；以及
将光电子器件形成在所述第一区域中，所述光电子器件具有底部熔覆层、有源区域以及顶部熔覆层，其中所述底部熔覆层处在所述半导体层上，所述有源区域处在所述底部熔覆层上，并且所述顶部熔覆层处在所述有源区域上。
2.根据权利要求1所述的方法，其中所述半导体层为SiGe层和SiGeC层中的一种。
3.根据权利要求1所述的方法，其中所述光电子器件包括III-V半导体。
4.根据权利要求1所述的方法，其中所述顶部熔覆层和所述底部熔覆层是AlGaAs，并且所述有源区域是GaAs。
5.根据权利要求1所述的方法，其中所述器件是硅互补金属氧化物半导体CMOS器件。
6.根据权利要求1所述的方法，其中所述光电子器件是使用外延生长来被形成的，并且所述半导体层被用作种子层。
7.根据权利要求1所述的方法，还包括：
形成第一接触、第二接触和器件接触，其中所述第一接触被直接连接到所述顶部熔覆层，所述第二接触被直接连接到所述底部熔覆层，并且所述器件接触被直接连接到所述器件。
8.一种用于半导体器件制造的方法，包括：
将叠层形成在第一区域中和第二区域中的衬底上，所述叠层包括所述衬底上的半导体层、所述半导体层上的第一绝缘体层、所述第一绝缘体层上的波导、所述波导上的第二绝缘体层、以及所述第二绝缘体层上的器件基层；
将所述器件形成在所述第二区域中的所述器件基层上；
将器件绝缘体层形成在所述第二区域中的所述器件上和所述器件基层上；以及
将光电子器件形成在所述第一区域中，所述光电子器件具有底部熔覆层、有源区域以及顶部熔覆层，其中所述底部熔覆层处在所述半导体层上，所述有源区域处在所述底部熔覆层上，并且所述顶部熔覆层处在所述有源区域上。
9.根据权利要求8所述的方法，其中所述半导体层是锗。
10.根据权利要求8所述的方法，其中所述光电子器件包括III-V半导体。
11.根据权利要求8所述的方法，其中所述顶部熔覆层和所述底部熔覆层是AlGaAs，并且所述有源区域是GaAs。
12.根据权利要求8所述的方法，其中所述器件是硅互补金属氧化物半导体CMOS器件。
13.根据权利要求8所述的方法，其中所述光电子器件是使用外延生长来被形成的，并且所述半导体层被用作种子层。
14.根据权利要求8所述的方法，其中所述波导延伸到所述第二区域中的所述器件之下。
15.根据权利要求8所述的方法，还包括：
形成第一接触、第二接触和器件接触，其中所述第一接触被直接连接到所述顶部熔覆层，所述第二接触被直接连接到所述底部熔覆层，并且所述器件接触被直接连接到所述器件。
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