CN105980959B - 低等待时间切换下的动态时钟和电压缩放 - Google Patents
低等待时间切换下的动态时钟和电压缩放 Download PDFInfo
- Publication number
- CN105980959B CN105980959B CN201580007810.2A CN201580007810A CN105980959B CN 105980959 B CN105980959 B CN 105980959B CN 201580007810 A CN201580007810 A CN 201580007810A CN 105980959 B CN105980959 B CN 105980959B
- Authority
- CN
- China
- Prior art keywords
- clock
- module
- mode
- frequency
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/177,073 US9678556B2 (en) | 2014-02-10 | 2014-02-10 | Dynamic clock and voltage scaling with low-latency switching |
| US14/177,073 | 2014-02-10 | ||
| PCT/US2015/014688 WO2015120199A1 (en) | 2014-02-10 | 2015-02-05 | Dynamic clock and voltage scaling with low-latency switching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105980959A CN105980959A (zh) | 2016-09-28 |
| CN105980959B true CN105980959B (zh) | 2019-08-06 |
Family
ID=52577970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580007810.2A Expired - Fee Related CN105980959B (zh) | 2014-02-10 | 2015-02-05 | 低等待时间切换下的动态时钟和电压缩放 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9678556B2 (enExample) |
| EP (1) | EP3105653A1 (enExample) |
| JP (1) | JP6309641B2 (enExample) |
| KR (1) | KR101844424B1 (enExample) |
| CN (1) | CN105980959B (enExample) |
| WO (1) | WO2015120199A1 (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9933845B2 (en) * | 2014-11-24 | 2018-04-03 | Intel Corporation | Apparatus and method to provide multiple domain clock frequencies in a processor |
| US10120408B2 (en) * | 2015-09-30 | 2018-11-06 | Texas Instruments Incorporated | Event controlled clock switching |
| US11068018B2 (en) * | 2016-10-25 | 2021-07-20 | Dolphin Design | System and method for power management of a computing system with a plurality of islands |
| CN106788398B (zh) | 2016-12-06 | 2020-06-02 | 矽力杰半导体技术(杭州)有限公司 | 时钟分频电路、控制电路以及电源管理集成电路 |
| KR102390766B1 (ko) | 2017-05-22 | 2022-04-26 | 삼성에스디아이 주식회사 | 이차 전지 |
| KR102640922B1 (ko) * | 2018-03-05 | 2024-02-27 | 삼성전자주식회사 | 동작 상태에 따라 기능 모듈들을 저전력 상태로 제어하는 집적 회로, 전자 장치 및 그 제어 방법 |
| CN109787625B (zh) * | 2019-03-05 | 2022-04-05 | 上海芷锐电子科技有限公司 | 一种基于双pll的系统超频引起的电压毛刺保护系统 |
| CN113157078B (zh) * | 2020-01-07 | 2023-05-30 | 上海寒武纪信息科技有限公司 | 用于控制处理器的方法、装置及其处理器 |
| US11442495B2 (en) * | 2020-03-06 | 2022-09-13 | Advanced Micro Devices, Inc. | Separate clocking for components of a graphics processing unit |
| GB2597275B (en) * | 2020-07-17 | 2022-09-07 | Graphcore Ltd | Multi-clock control |
| CN112130658A (zh) * | 2020-09-29 | 2020-12-25 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | 程控智能电源与时钟控制方法及系统 |
| US12197264B2 (en) * | 2020-11-10 | 2025-01-14 | Micron Technology, Inc. | Power management for a memory device |
| JP7422066B2 (ja) * | 2020-12-28 | 2024-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US11467622B2 (en) * | 2021-02-23 | 2022-10-11 | Texas Instruments Incorporated | Clock oscillator control circuit |
| KR102851792B1 (ko) | 2021-02-26 | 2025-08-28 | 삼성전자주식회사 | 전력 관리 집적 회로 및 이를 포함하는 전자 장치 |
| CN113572357B (zh) * | 2021-07-23 | 2022-12-27 | 维沃移动通信有限公司 | 电子设备 |
| KR102605288B1 (ko) * | 2023-04-11 | 2023-11-23 | 주식회사 바움디자인시스템즈 | 집적 회로에 대한 소비 전력을 예측하기 위한 시뮬레이션 방법 및 이를 수행하는 집적 회로 시뮬레이션 시스템 |
| US20240413962A1 (en) * | 2023-06-12 | 2024-12-12 | Qualcomm Incorporated | Programmable clock divider for radio frequency (rf) mixers |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040193934A1 (en) * | 2003-03-24 | 2004-09-30 | Opher Kahn | Reducing CPU and bus power when running in power-save modes |
| CN103163940A (zh) * | 2011-12-12 | 2013-06-19 | 三星电子株式会社 | 片上系统时钟控制方法、片上系统及包括其的半导体系统 |
| CN103248358A (zh) * | 2013-05-30 | 2013-08-14 | 上海贝岭股份有限公司 | 实时时钟补偿装置及方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215725B1 (en) | 1997-07-23 | 2001-04-10 | Sharp Kabushiki Kaisha | Clock-synchronized memory |
| US6425086B1 (en) | 1999-04-30 | 2002-07-23 | Intel Corporation | Method and apparatus for dynamic power control of a low power processor |
| US6988211B2 (en) | 2000-12-29 | 2006-01-17 | Intel Corporation | System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field |
| US7171577B2 (en) * | 2003-10-06 | 2007-01-30 | Texas Instruments Incorporated | Methods and apparatus for a system clock divider |
| CN100501748C (zh) | 2003-10-31 | 2009-06-17 | 国际商业机器公司 | 用于动态系统级频率缩放的方法和装置 |
| US7605622B2 (en) * | 2005-09-29 | 2009-10-20 | Hynix Semiconductor Inc. | Delay locked loop circuit |
| US7539278B2 (en) | 2005-12-02 | 2009-05-26 | Altera Corporation | Programmable transceivers that are able to operate over wide frequency ranges |
| WO2007148159A1 (en) | 2006-06-22 | 2007-12-27 | Freescale Semiconductor, Inc. | A method and device for power management |
| US20080307240A1 (en) | 2007-06-08 | 2008-12-11 | Texas Instruments Incorporated | Power management electronic circuits, systems, and methods and processes of manufacture |
| US8028181B2 (en) | 2008-09-19 | 2011-09-27 | Intel Corporation | Processor power consumption control and voltage drop via micro-architectural bandwidth throttling |
| US8448001B1 (en) | 2009-03-02 | 2013-05-21 | Marvell International Ltd. | System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device |
| US8190931B2 (en) | 2009-04-30 | 2012-05-29 | Texas Instruments Incorporated | Power management events profiling |
| KR101897050B1 (ko) * | 2012-05-04 | 2018-09-12 | 에스케이하이닉스 주식회사 | 반도체 장치 |
-
2014
- 2014-02-10 US US14/177,073 patent/US9678556B2/en active Active
-
2015
- 2015-02-05 WO PCT/US2015/014688 patent/WO2015120199A1/en not_active Ceased
- 2015-02-05 JP JP2016550710A patent/JP6309641B2/ja not_active Expired - Fee Related
- 2015-02-05 KR KR1020167023537A patent/KR101844424B1/ko not_active Expired - Fee Related
- 2015-02-05 CN CN201580007810.2A patent/CN105980959B/zh not_active Expired - Fee Related
- 2015-02-05 EP EP15706320.7A patent/EP3105653A1/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040193934A1 (en) * | 2003-03-24 | 2004-09-30 | Opher Kahn | Reducing CPU and bus power when running in power-save modes |
| CN103163940A (zh) * | 2011-12-12 | 2013-06-19 | 三星电子株式会社 | 片上系统时钟控制方法、片上系统及包括其的半导体系统 |
| CN103248358A (zh) * | 2013-05-30 | 2013-08-14 | 上海贝岭股份有限公司 | 实时时钟补偿装置及方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3105653A1 (en) | 2016-12-21 |
| US9678556B2 (en) | 2017-06-13 |
| JP6309641B2 (ja) | 2018-04-11 |
| US20150227185A1 (en) | 2015-08-13 |
| JP2017506458A (ja) | 2017-03-02 |
| KR101844424B1 (ko) | 2018-04-02 |
| CN105980959A (zh) | 2016-09-28 |
| KR20160119121A (ko) | 2016-10-12 |
| WO2015120199A1 (en) | 2015-08-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190806 Termination date: 20220205 |
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| CF01 | Termination of patent right due to non-payment of annual fee |