US6425086B1 - Method and apparatus for dynamic power control of a low power processor - Google Patents

Method and apparatus for dynamic power control of a low power processor Download PDF

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US6425086B1
US6425086B1 US09/302,560 US30256099A US6425086B1 US 6425086 B1 US6425086 B1 US 6425086B1 US 30256099 A US30256099 A US 30256099A US 6425086 B1 US6425086 B1 US 6425086B1
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processor
voltage
operating
operating voltage
system
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Lawrence T. Clark
Bart McDaniel
Jay Heeb
Tom J. Adelmeyer
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Intel Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3296Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/12Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon the main processing unit
    • Y02D10/126Frequency modification
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/17Power management
    • Y02D10/172Controlling the supply voltage

Abstract

Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Description

BACKGROUND

1. Field

The present invention is related to processors, and, more particularly, to dynamic power control of low power processors.

2. Background Information

Achieving significant power savings in embedded processors, such as microprocessors, for example, and other digital systems is becoming increasingly desirable. One reason is the increase in the use of cell phones and other hand-held portable devices having limited battery capacity. In addition, the computing power of such hand-held devices is increasing as the technology evolves, and will continue to increase for the foreseeable future. This is particularly likely with the addition of digital signal processing and communications capability to such devices and systems, as well as software applications, such as voice recognition, which will predictably utilize and potentially drive this increasing computational demand.

In systems that employ such processors, it is not unusual for the battery voltage to tend to be higher than a particular voltage level employed for successful operation and, therefore, voltages provided by the battery are often stepped down, such as via a voltage regulator. Another reason a higher voltage may be provided is that modern high frequency silicon fabrication processes for processors, such as microprocessors, tend to tolerate lower voltages than the processes employed to fabricate other components. Therefore, typically the regulators provide multiple output levels of voltage for different components of the system. Furthermore, as the batteries wear out, typically the voltage output level drifts downward and, therefore, voltage regulators are also employed in this context to provide a substantially consistent operating voltage over the battery life. Recently, more complex regulators that provide the capability to switch between step down and step up operation have become available and may be useful in this environment. Such a regulator steps the battery voltage down when the battery is relatively new or recharged, and steps the voltage up when that voltage has degraded over time to a level which is insufficient to proper operation of the system, thereby extending the useful battery lifetime.

As is well known, power consumption is related to the voltage level of the voltage supply by the following equation: P=C(Vdd)2 F, where F is the operating frequency, C is the switched capacitance, and Vdd is the power supply voltage. As this equation demonstrates, power may be significantly reduced by lowering the voltage level of the supply voltage. Unfortunately, the maximum performance obtainable for a given operating frequency F is also related to the supply voltage as follows: Id(sat)=β(Vdd−Vt)α, where Id(sat) is the drain current at saturation, Vdd is the drain-to-source voltage, and Vt is the threshold voltage. α is a process dependent parameter and is typically taken to be 2, but may be between one and two and β has its usual meaning, well known in the art, including the width and length parameters for an metal-oxide semiconductor (MOS) transistor. Consequently, because systems are designed to operate at a voltage level that meets their peak computational performance demands, they consume significant amounts of power which is not useful at times when the peak computational capability is not required. In such systems, power is typically saved by “clock gating.” In this approach, the sections of the device or system which are unused have the clocks that drive those sections turned “off.” This lowers the effective frequency of operation, resulting in a linear improvement, as indicated by the equation above, essentially by lowering the average frequency by including zero frequency time spans into the average. A need, therefore, exists for a technique that improves the reduction in power consumption for these low power devices, while still delivering sufficient computational performance to complete the tasks desired.

SUMMARY

Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a schematic diagram illustrating an embodiment of a system in accordance with the present invention;

FIG. 2 is a schematic diagram illustrating another embodiment of a system in accordance with the present invention;

FIG. 3 is a schematic diagram illustrating yet another embodiment of a system in accordance with the present invention;

FIG. 4 is a schematic diagram illustrating still another embodiment of a system in accordance with the present invention;

FIG. 5 is a graph illustrating the Fmax versus Vdd curve for an embodiment in accordance with the present invention;

FIG. 6 is a plot illustrating one approach to raising and lowering voltage and frequency for an embodiment in accordance with the invention;

FIG. 7 is a plot illustrating another approach to raising and lowering voltage and frequency for an embodiment in accordance with the invention.

DETAILED DESCRIPTION

In the following detailed description, specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the relevant art that the present invention may be practiced without the specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

As previously discussed, cell phones and other hand-held portable devices, such as, for example, a personal digital assistant or a global positioning system (GPS) receiver, typically have limited battery capability, making power savings particularly desirable. For example, the batteries employed in devices or systems that weigh no more than approximately several pounds typically have limited capability. Likewise, the trend has been toward an increase in the computing power of such devices. Employing this increased computing power may result in significant power consumption and/or significant additional power consumption. However, a hand-held device may not be consistently called upon to deliver peak performance the entire time that it is being used. For example, such devices may at times be operating in a mode which demands relatively little computational capability, such as, for example, dealing with keyboard input/output, such as key strokes. Likewise, as previously indicated, more complex voltage regulators have become available, particularly in the form of a integrated circuit or embodied on an integrated circuit chip with other circuitry. These regulators may include the capability to both step down the operating voltage or step up the operating voltage for a particular component, such as a processor. This capability provides the opportunity to efficiently provide the desired voltages above or below the battery voltage and, thereby, effectively lengthen the battery lifetime or time between recharges. More specifically, the capability may be provided to supply the desired voltage level dynamically, based at least in part on changes in processor capability utilization, and when these voltage levels are, therefore, desirable, such as when a particular computational task is being executed at the particular time.

As previously indicated, power consumption is related to the operating frequency of a processor in a linear fashion and to its operating voltage level in a square law relationship. Therefore, a technique may be employed that allows a combined linear (eg, frequency) and square law (eg, voltage) reduction improvement in power consumption when the computational demand of a component, such as a processor, for example, is relatively high or relatively low. More specifically, a hand-held device may utilize switched power regulation or the output voltage level may be made programmable. Where this approach is employed, the operating voltage for the processor, for example, and, hence, the power consumption, may be controlled by the processor itself, through the execution of processor instructions. In addition to the processor operating voltage level, the operating frequency of the processor may likewise be controlled in a dynamic, on-demand, fashion. In this context, the term dynamic changes in the processing load of the processor refers to measured or predicted changes in processing load that have the potential for a sufficient enough impact on the power consumption and/or performance by the processor to make modifications in the operating frequency or adjustments in the operating voltage desirable. In one particular embodiment, although the invention is not limited in scope in this respect, the processor instructions, while being executed by the processor, may determine that a computationally intensive task is beginning or is about to be begun. For example, the executable code of an application may include information for the operating system (OS) “loader,” in this context the portion of the OS which places new application programs in memory and begins their operation by the processor, so that the loader may execute a subroutine which increases or decreases the power and frequency state of the system to match the performance level intended for this application. In this case the frequency intended for the application to run correctly may be determined by the application programmer via several means, and stored as part of the program. Alternatively, the application may call a predetermined subroutine or OS service to increase or decrease the power and frequency itself either directly or through the OS. The latter may provide an advantage in that it may afford protection of the system from errant applications or where more than one application is running simultaneously. Note that in such a case, where multiple applications are running, the OS can determine the sum of performance demands and deliver the power and frequency for this sum correctly. Of course, this is just one example of how this might be accomplished and the invention is not limited to any particular approach. Therefore, in one embodiment, the execution of these instructions may result, for example, in the setting of binary digital signals or bits within specific registers which control the operating frequency and the operating voltage level, thus allowing the power consumption to be reduced for those tasks which are not particularly computationally intensive, while still delivering the desired high computational performance. In this particular embodiment, when the computationally intensive task has been completed by the processor, the processor instructions being executed may then, by setting binary digital signals or bits, which again control the operating frequency and the operating voltage level of the processor, reduce power consumption to a relatively low state. In one particular embodiment, although, again, the invention is not limited in scope in this respect, as will become more clear later, the clock driving the processor may be permitted to continue to operate, thus allowing the processor to successfully execute processor instructions soon after such voltage/frequency changes, while still saving significant amounts of power.

FIG. 1 is a schematic diagram illustrating one embodiment of a system in accordance with the present invention. Of course, as previously indicated, and as will be explained in more detail hereinafter, the invention is not limited in scope to this particular embodiment. Nonetheless, embodiment 100 shown in FIG. 1 includes a processor 110, such as a microprocessor, a voltage regulator 120, and a memory 130. As illustrated, memory 130 is coupled to processor 110 via a memory bus 140. Furthermore, power is supplied to the system via a battery 150, although it will, of course, be understood that such a system is to typically be provided without battery 150, because conventionally batteries may be obtained from a variety of sources. Furthermore, specific components of some embodiments of a system in accordance with the invention, such as the processor, may likewise be provided or sold separately for later incorporation into a system, for example, and still fall within the scope of the invention.

In this particular embodiment, voltage regulator 120 is coupled to processor 110 to adjust the operating voltage, Vdd in FIG. 1, of processor 110. In this embodiment, this occurs based, at least in part, on binary digital signals that are provided to the voltage regulator, as explained in more detail below. As illustrated in FIG. 1, these binary digital signals are provided via a control word which is loaded into control register 125 in this particular embodiment. Memory 130, which may comprise, for example, a dynamic random access memory (DRAM), has stored processor instructions, that, when executed by processor 110, result in modification of the operating frequency of processor 110 and result in adjustment of the operating frequency of processor 110 based, at least in part, on dynamic changes in the processing load of the processor.

In this particular embodiment, a control word is provided by microprocessor 110 to voltage regulator 120 via a control bus 160, although, again, the invention is not limited in scope in this respect. Nonetheless, in this specific embodiment, the “control register” may be “memory mapped.” More specifically, one or more selected or designated addressable memory locations that do not correspond with any actual memory locations within memory 130, may function or operate as a portion of memory 130. That is, it is transparent to the processor that it is addressing the control register when the processor reads or writes to this selected memory address location or memory address locations. In such an embodiment, voltage regulator 120 may be coupled to the control register located in memory 130 by a memory bus 140(not shown in FIG. 1). Therefore, a write operation to the selected or designated locations may signal a change in the control register. Of course, again, the invention is not limited in scope to this embodiment, for example, the voltage regulator control voltage may correspond to an input/output (I/O) port rather than a memory location.

In this particular embodiment, the voltage level delivered to microprocessor 110 by voltage regulator 120 may be adjusted by setting the control register binary digital signals based on the frequency desirable to complete the specific microprocessor application in real time. Thus, in such an embodiment, the processor instructions stored on memory 130 and being executed by processor 110 may assess the computational intensity or processing load of a particular task and adjust the bits of control register 125 accordingly. Therefore, in this particular embodiment, voltage regulator 120 is programmable. As illustrated in FIG. 1, memory 130, microprocessor 110 and voltage regulator 120 are each on separate integrated circuit chips, although, the invention is not limited in scope in this respect. Furthermore, system 100 may include a nominal operating voltage for a large percentage of the tasks to be executed by the microprocessor. Voltage regulator 120 is coupled to processor 110 and is capable in this embodiment of adjusting the operating voltage of processor 110 up and/or down from this nominal operating voltage based, at least in part, on the binary digital signals provided to voltage regulator 120, such as those provided to control register 120 in this particular embodiment. For example, tasks may be on a continuum from computationally intensive to not computationally intensive. At one end of this continuum, voice recognition, might be an example of a computationally intensive task, and at the other end, keyboard input/output, such as key strokes, might be an example of a not computationally intensive task. Likewise, an example of a task between the two extremes, where a nominal operating voltage may be employed, might include performing network operations. Of course, these tasks are merely provided as examples, and the invention is not limited to these tasks or to this continuum, or to employing a continuum at all. As previously indicated, in one embodiment, the binary digital signals may be written to one or more selected or designated memory location addresses that have been mapped to the control register.

In one embodiment, although, again, the invention is not limited in scope in this respect, memory 130 has stored thereon processor instructions that, when executed by processor 110, result in the processor being placed in sleep mode before adjustment of the operating voltage of the processor by voltage regulator 120. In this embodiment, placing the microprocessor in sleep mode comprises finishing current operations, stopping the internal clocks, and stopping the microprocessor phase locked loop (PLL) or similar circuit. Once this has occurred, as previously indicated, the processor instructions being executed by the processor may provide binary digital signals to a control register, such as control register 125, which results in the operating voltage of processor 110 being changed by voltage regulator 120. In one embodiment, although the invention is not limited in scope in this respect, the processor instructions may result in the processor waiting an amount of time sufficient after this adjustment of the operating voltage to permit the voltage adjustment to have been successfully accomplished. One skilled in the art will appreciate that there are a number of ways to specify this amount of time and the various alternative ways shall not be enumerated here, however, it is contemplated that all fall within the scope of the invention. Likewise, in an alternative embodiment, the processor instructions, when executed by the processor, may result in the processor verifying, after adjustment of the operating voltage, that the voltage adjustment has been successfully accomplished. As one example, this could be accomplished by reading another register which stores the output signal of an analog to digital (A to D) converter which monitors the voltage reference. Such a device may substantially use portions of the voltage regulator control mechanism, eg., an A to D converter is part of some digital to analog (D to A) converters which may be employed to generate the digital control of the supply voltage as part of the voltage regulator. Modern PC motherboard designs have a number of such A to D ports which can be read by the operating system and basic input-output system (BIOS) to monitor that system voltages and temperatures are within their nominal settings. For example, they are presently used primarily to signal the system to halt if a component fails. This is just one example of an approach and the invention is not restricted in scope to this particular technique. In any event, the operating frequency of the processor may then be modified by initiating operation of the processor at a modified frequency after the prior events have been successfully completed, that is, in this particular embodiment, after placing the processor in sleep mode and successfully modifying the operating voltage of the processor. This may be implemented, for example, by renewing operation of the phase locked loop of the microprocessor so that it locks onto this modified frequency, where a PLL is employed. This may be accomplished by any one of a number of techniques and the invention is not limited in scope to any particular technique. For example, the divider ratio for the input signal of the phase locked loop may be modified although, again, the invention is not limited in scope in this respect. Furthermore, as with the voltage regulator, this may be signaled by writing to a memory location that is mapped to a particular processor register for this purpose, such as register 112 in FIG. 1. Once the PLL has locked onto the modified frequency, the internal clocks of the microprocessor may be restarted and normal operation of the system may be resumed from the point at which it stopped. After the PLL has been stopped, restarting the PLL and having it lock onto the modified frequency in one embodiment may take on the order of 10 microseconds, for example. Of course, this is dependent, at least in part, on the range of frequencies of interest and the voltage, so this is provided simply as an example. However, relative to clock speed, for example, this may in some cases be a time consuming operation.

Once the operation that resulted in the modification of the operating voltage level and operating frequency level has been completed by the processor, the same approach or technique may then be employed to again change the operating voltage level and the operating frequency level back to the previous level. Thus, it will be appreciated that where a nominal voltage level and a nominal operating frequency exists for a particular embodiment, this technique may be employed to reduce the operating frequency and operating voltage level where a particularly less computationally intensive task is sensed or recognized and likewise the operating voltage level and operating frequency may be increased where a particularly computationally task is sensed or recognized. As previously described, examples include voice recognition for a computationally intensive task, network processing for a nominal task, and keyboard input/output for a low or not computationally intensive task, although these are merely illustrative examples. Therefore, the invention is not limited in scope to only a step up in voltage and frequency or only a step down in voltage and frequency, although, such embodiments are also possible and within the scope of the invention.

In another embodiment, in accordance with the invention, a phase locked loop of the microprocessor, where a microprocessor and PLL are employed, may continue operating while the operating voltage level is varied. One advantage of this particular embodiment is that operations may be completed sooner after the voltage/frequency levels are being changed. For example, as previously explained, where the PLL is stopped, it may take some time for the PLL to reestablish lock at the modified frequency; however, where the PLL continues to operate and the internal clocks have been stopped, the internal clocks may be restarted in a single clock pulse, which is advantageously less time. In this particular embodiment, memory 130 has stored processor instructions that, when executed by the processor, result in the processor being placed in idle mode before adjusting the operating voltage of the processor and before modifying the operating frequency of the processor. In an alternative embodiment, the internal clock may be driven directly from the PLL reference clock during PLL frequency changes, where a PLL is employed. In this manner, the processor continues to process information and can react to external events, eg., interrupts, albeit at the slower rate of the reference clock. This mode is a power saving means when the processor is waiting to process information coming in from the bus. In this particular environment, in idle mode, the processor finishes current operations and then stops the internal clocks. However, the phase locked loop (PLL) of the processor, in this embodiment, for example, continues to operate. In this particular approach, while the phase locked loop continues to operate, the operating voltage of the processor is adjusted by the voltage regulator and the operating frequency of the processor is modified, as previously described, for example. The dynamic processing load, as previously indicated, may be recognized or determined by the processor as it executes the stored processor instructions. For example, a processor may recognize that a significantly more computationally intensive or significantly less computationally task is about to begin for a particular period of time. For example, although the invention is not limited in scope in this respect, where the processor is performing voice recognition, this may result in some computationally intensive tasks being performed for a relatively short period of time.

There are also a number of different approaches to adjusting the operating voltage and modifying the operating frequency in this particular embodiment. For example, this may be accomplished sequentially or alternatively, depending on certain parameters, these may be executed concurrently. For example, the amount of time it takes to raise the operating voltage may be relatively short in comparison with the amount of time it takes to increase the frequency of the phase locked loop. Therefore, if these operations are performed concurrently, by the time the operating frequency has been raised, both operations will have been successfully completed. Alternatively, the time constant for lowering the operating voltage may be made relatively larger than the time constant for lowering the operating frequency of the PLL. Again, this may represent a situation in which it may be desirable to perform these operations concurrently so that by the time the operating voltage has been lowered to the desired level, both operations will have been successfully completed. FIG. 7 illustrates where these operations are performed concurrently for an embodiment of the invention. It will, of course, be understood that in this context, concurrently does not mean that both operations are being performed for the entire time, but rather that the operations overlap for at least a portion of the time. It will, furthermore, be appreciated by one of ordinary skill in the art that the particular details to successfully accomplish this may vary with the particular task or tasks being executed, as well as a variety of other factors. Therefore, the invention is not limited in scope to one particular approach. Furthermore, in an alternative embodiment, it may be desirable to modify the operating frequency and adjust the operating voltage sequentially. Therefore, once the microprocessor has been placed in idle mode, the processor PLL is signaled to reduce the output clock frequency. As previously indicated this may be accomplished by any one of a number of techniques, such as by modifying the divider ratio for the input signal applied to the PLL, where a PLL is employed. Likewise, depending on the particular embodiment, the processor instructions being executed may either indicate that the processor wait a sufficient period of time to ensure that the desired operating frequency has been achieved or, alternatively, the processor determines whether the appropriate operating frequency has been reached. As one example, possibly through a timer which takes the same length of time as the nominal lock time of the PLL under predictable changes, such as, a table look up programmed timer, or alternatively, by receiving a signal from the PLL which, based on the activity in the charge pump, based on information from the a frequency detector may send a signal to the processor, which indicates a locked or not locked condition. Such a frequency lock detector is well known to those skilled in the art and will not be describe in detail here. However, again, the invention is not limited in scope to a particular approach to accomplish this. In any event, once the desired operating frequency has been achieved, as previously described, the processor may execute processor instructions that signal the voltage regulator to adjust the operating voltage. In this particular embodiment, it is desirable to employ the previously described order, that is modifying the operating frequency and then adjusting the operating voltage, where it is desired to reduce power consumption. Alternatively, where it is desired to increase power consumption, such as when a computationally intensive task is to be completed, as previously described, then it may be desirable to signal the voltage regulator to move to a higher voltage and then signal the microprocessor to increase the output clock frequency. FIG. 6 illustrates raising the operating voltage before the operating frequency and then lowering the operating frequency before the operating voltage for a particular embodiment of the invention. Here, computation need not cease while the voltage and frequency changes are made, so long as the operation runs under the curve illustrated in FIG. 5. Therefore, the processor does not violate its circuit speed/voltage operating envelope during the changes. This may be implemented, for example, by forcing the time constants by circuit design to be maintained as in the figure during increases or decreases in frequency and voltage.

In this particular embodiment, as illustrated by the graph in FIG. 5, the operating frequency is maintained below a maximum frequency level that may be successfully delivered at the given voltage level. By maintaining the operating frequency below this level for a given operating voltage, although operation of the microprocessor is halted in this particular embodiment, there is little or no risk of a functional failure in the rest of the circuitry due to the internal circuitry maintaining state being idle. Alternatively, the internal circuitry may be run at the reference frequency as stated above, which will allow work to be accomplished with little or no possibility of operating at a frequency above the frequency available at the given (temporally varying) operating voltage. More specifically, the operating frequency is maintained below a level so that the internal circuitry will successfully keep pace with the clock at that particular operating voltage level. Therefore, there is little or no risk of a cycle produced by the clock generator being shorter than the circuitry is capable of performing at the internal voltage.

Of course, in alternative embodiments, these various system components may be integrated. FIG. 2 is, therefore, an example of another embodiment of a system in accordance with the present invention. In this particular embodiment, 200, the voltage regulator and the flash memory are integrated on a single integrated circuit chip 210. One desirable aspect is that the manufacturing processes employed to produce flash memory allow higher voltages, which is employed, as is well known by those skilled in the art, at least in part for proper flash programming and erasing, and are, therefore, more amenable to the fabrication of relatively efficient voltage regulators. Further, the additional processing and the nature of that processing, specifically the use of two polysilicon gate layers, supports the ability of such processes to include passive analog components, for example, more easily than a conventional logic process as is typically employed for microprocessor fabrication. Likewise, employing flash memory is not a significant restriction in typical state of the art systems as it is typically used as a means of program storage in such hand-held systems. As illustrated in FIG. 2, in this particular embodiment, control register 217 which is integrated on chip 210, is accessed in substantially the same manner as the flash memory control circuitry. Therefore, the control register is accessed by the same circuitry which controls the read and write operations to flash memory 215. Thus, another advantage of this approach is that no additional bus is employed on the microprocessor side of the system, as illustrated in FIG. 2. This approach is similar to that previously described in which a control register is “mmr mapped” so that the memory bus may be employed to transfer the binary digital control signals used to program the voltage regulator. However, in this particular embodiment, this is accomplished by integrating the voltage regulator with the flash memory on a single integrated circuit chip. Likewise, the voltage regulator may also provide other voltage signal levels, such as for static-dynamic random access memory (SDRAM) or other system level devices, in addition to the operation it performs with respect to processor 230 in FIG. 2.

FIG. 4 is a schematic diagram of yet still another embodiment. As illustrated, in this embodiment, the processor and voltage regulator are integrated on a single integrated circuit chip. FIG. 3 is a schematic diagram of still another embodiment that employs an even higher level of integration than the embodiments illustrated in FIGS. 2 and 4. In this particular embodiment, processor 310, flash memory 320 and voltage regulator 330 are integrated on a single integrated circuit chip. As illustrated in FIG. 3, this particular embodiment may supply voltage signal levels for external devices, such a DRAM 340 illustrated in FIG. 3. One advantage of this particular embodiment is that control register 312 in FIG. 3 may be integrated onto microprocessor 310 directly. For example, although the invention is not limited in scope in this respect, in the well-known ARM architecture, the co-processor control registers may be utilized to control the voltage operating levels in substantially the same manner as they may be employed to control the clock frequency, and other power-down modes, such as idle and other possible modes. In one particular embodiment, the register used comprises the ARM® co-processor register (CP) CP-14 register 7, which contains the clock and power management functions, although the invention is not restricted in scope in this respect. In this register, some bits control the voltage state and some control the clock frequency (PLL multiplier). For example, a change operation may be initiated upon detection of a write to this register in a manner which will be familiar to one skilled in the art. Therefore, a single register may be employed in this embodiment in which the adjustment of the operating voltage and the modification of the operating frequency is accomplished in a single, atomic operation, although, of course, the invention is not limited in scope in this respect. It is noted that the embodiment illustrated in FIG. 4 provides this advantage as well.

Furthermore, other embodiments may comprise, rather than a system, alternatively, an article including a storage medium, such as, for example a computer- or machine-readable storage medium, such as a hard disk, a compact disk(CD), or a diskette. In such an embodiment, the storage medium may have stored thereon instructions, such as processor instructions. The processor instructions may be such that when executed in a system, such as one including a voltage regulator coupled to the processor, modification of the operating frequency and adjustment of the operating voltage of the processor results, based, at least in part, on dynamic changes in the processing load of the processor. Such embodiments may include additional features, such as those previously described and illustrated with respect to the figures, although the invention is not limited in scope in this respect. Furthermore, an embodiment may alternatively include a method of reducing the power consumption of a processor in accordance with the invention, such as by modifying the operating frequency and adjusting the operating voltage of a processor in the manner described in the previously discussed embodiments, although, again, the invention is not limited in scope in this respect.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents thereof will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims (12)

What is claimed is:
1. A system comprising:
a processor, a voltage regulator, a flash memory and a non-flash memory;
wherein said voltage regulator is coupled to said processor to adjust the operating voltage of said processor;
said non-flash memory being coupled to said processor via a memory bus and said non-flash memory having stored thereon processor instructions that, when executed by said processor, result in modification of the operating frequency of said processor and result in adjustment of said operating voltage of said processor based, at least in part, on dynamic changes in the processing load of said processor.
2. The system of claim 1, wherein said processor comprises a microprocessor.
3. The system of claim 1, wherein said non-flash memory comprises a dynamic random access memory (DRAM).
4. The system of claim 3, wherein said voltage regulator and said processor are integrated on one integrated circuit chip.
5. The system of claim 1, wherein said voltage regulator is coupled to said processor to be capable of adjusting the operating voltage of said processor up and down from a nominal operating voltage based at least in part on binary digital signals provided to said voltage regulator.
6. The system of claim 1, wherein said non-flash memory further includes processor instructions stored thereon that, when executed by said processor, result in modification of the operating frequency of said processor up and down from a nominal operating frequency based, at least in part, on dynamic changes in the processing load of said processor.
7. An article comprising:
a storage medium, said storage medium having stored thereon, instructions that, when executed by a processor in a system, said system including a voltage regulator coupled to said processor to adjust the operating voltage of said processor,
result in completion of current operations;
result in modification of the operating frequency of said processor and
result in adjustment of said operating voltage of said processor based, at least in part, on dynamic changes in the processing load of said processor.
8. The article of claim 7, wherein said instructions include the capability, when executed by said processor, to result in said voltage regulator adjusting the operating voltage of said processor up and down from a nominal operating voltage based at least in part on binary digital signals provided to said voltage regulator.
9. The article of claim 7, wherein said instructions , when executed by said processor, result in the processor adjusting the operating voltage of said processor and modifying the operating frequency of said processor concurrently.
10. A method of reducing the power consumption of a processor comprising:
allowing the processor to finish current operations before,
modifying the operating frequency of said processor; and
adjusting the operating voltage of said processor;
wherein said modification and said adjustment is based, at least in part, on dynamic changes in the processing load of said processor.
11. The method of claim 10, wherein adjusting the operating voltage of said processor comprises adjusting the operating voltage of said processor up and down from a nominal operating voltage based at least in part on said dynamic changes.
12. The method of claim 10, wherein said adjustment of the operating voltage and said modification of said operating frequency occurs concurrently.
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DE10084547T DE10084547B4 (en) 1999-04-30 2000-04-20 A method for dynamic power control of a processor low power consumption
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Cited By (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020083356A1 (en) * 2000-09-30 2002-06-27 Xia Dai Method and apparatus to enhance processor power management
US20020087896A1 (en) * 2000-12-29 2002-07-04 Cline Leslie E. Processor performance state control
US20020104029A1 (en) * 2001-01-02 2002-08-01 Windbond Electronics Corp. Method and device for adjusting executing efficiency
US20020116650A1 (en) * 2000-01-18 2002-08-22 Sameer Halepete Adaptive power control
US20020194513A1 (en) * 2001-06-19 2002-12-19 Hitachi, Ltd. Semiconductor device and an operation control method of the semiconductor device
US20030009702A1 (en) * 2001-07-05 2003-01-09 Park Sung Jin Power supply for central processing unit
US20030020821A1 (en) * 2001-07-27 2003-01-30 Tohru Watanabe Imaging apparatus
US6519707B2 (en) * 1999-04-30 2003-02-11 Intel Corporation Method and apparatus for dynamic power control of a low power processor
US20030071657A1 (en) * 2001-08-29 2003-04-17 Analog Devices, Inc. Dynamic voltage control method and apparatus
US20030115239A1 (en) * 2000-09-22 2003-06-19 Atsushi Togawa Arithmetic processing system and arithmetic processing control method, task managemnt system and task management method, and storage medium
US20030120958A1 (en) * 2001-12-26 2003-06-26 Zhang Kevin X. Method and apparatus for providing supply voltages for a processor
US20030122530A1 (en) * 2001-12-05 2003-07-03 Takahiro Hikita Voltage regulator
US20040025069A1 (en) * 2002-08-01 2004-02-05 Gary Scott P. Methods and systems for performing dynamic power management via frequency and voltage scaling
US6697952B1 (en) * 2000-07-24 2004-02-24 Dell Products, L.P. Margining processor power supply
US20040039954A1 (en) * 2002-08-22 2004-02-26 Nvidia, Corp. Method and apparatus for adaptive power consumption
US20040057324A1 (en) * 2002-08-08 2004-03-25 Hiroyuki Abe Semiconductor integrated circuit having controllable internal supply voltage
EP1422595A2 (en) * 2002-11-25 2004-05-26 Texas Instruments Inc. Adjusting voltage supplied to a processor in response to clock frequency
US20040128567A1 (en) * 2002-12-31 2004-07-01 Tom Stewart Adaptive power control based on post package characterization of integrated circuits
US20040128566A1 (en) * 2002-12-31 2004-07-01 Burr James B. Adaptive power control
US20040138833A1 (en) * 2003-01-13 2004-07-15 Arm Limited Data processing performance control
US6826702B1 (en) * 1999-09-28 2004-11-30 Nec Corporation Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load
US20050003764A1 (en) * 2003-06-18 2005-01-06 Intel Corporation Current control circuit
US20050144355A1 (en) * 2002-10-15 2005-06-30 Remote Data Systems, Inc. Computerized methods for data loggers
US20050188230A1 (en) * 2004-02-20 2005-08-25 International Business Machines Corporation System and method of controlling power consumption in an electronic system
US20050223259A1 (en) * 2004-03-31 2005-10-06 Lehwalder Philip R Method, apparatus and system for enabling and disabling voltage regulator controllers
US20050223251A1 (en) * 2004-04-06 2005-10-06 Liepe Steven F Voltage modulation for increased reliability in an integrated circuit
WO2005094405A2 (en) * 2004-03-18 2005-10-13 Analog Devices, Inc. Closed loop dynamic power management
US20050278561A1 (en) * 2004-06-11 2005-12-15 Samsung Electronics Co., Ltd. Electronic devices and operational methods that change clock frequencies that are applied to a central processing unit and a main system bus
US7050478B1 (en) * 2000-08-03 2006-05-23 International Business Machines Corporation Apparatus and method for synchronizing clock modulation with power supply modulation in a spread spectrum clock system
US20060129852A1 (en) * 2004-12-10 2006-06-15 Bonola Thomas J Bios-based systems and methods of processor power management
US20060193113A1 (en) * 2005-02-28 2006-08-31 International Business Machines Corporation Controlling a surface temperature of a portable computer for user comfort in response to motion detection
US7129763B1 (en) 2004-11-08 2006-10-31 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay
US20070005910A1 (en) * 2005-06-30 2007-01-04 Alon Naveh Device, system and method of generating an execution instruction based on a memory-access instruction
US20070006003A1 (en) * 2002-04-29 2007-01-04 Youngs Lynn R Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
CN1300660C (en) * 2003-12-05 2007-02-14 宏碁股份有限公司 Structure of dynamic management device power source and its method
US7205805B1 (en) 2004-11-02 2007-04-17 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
US20070085712A1 (en) * 2005-02-09 2007-04-19 Sony Corporation Decoding method, decoding device, and program for the same
CN1312546C (en) * 2002-12-30 2007-04-25 英特尔公司 Dynamic voltage transition
WO2007073632A1 (en) * 2005-12-29 2007-07-05 Lenovo (Beijing) Limited Method for reducing power consumption of processor
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US7330019B1 (en) 2006-10-31 2008-02-12 Western Digital Technologies, Inc. Adjusting on-time for a discontinuous switching voltage regulator
US7346048B1 (en) 2001-07-31 2008-03-18 Lsi Logic Corporation Efficient high density voice processor
US20080143372A1 (en) * 2002-04-16 2008-06-19 Transmeta Corporation Closed loop feedback control of integrated circuits
US20080170153A1 (en) * 2001-08-01 2008-07-17 Sanyo Electric Co., Ltd. Image signal processor for use with a solid-state imaging device
US20080224685A1 (en) * 2004-12-20 2008-09-18 Amit Dor Method and apparatus to manage power consumption of a semiconductor device
US7479753B1 (en) 2004-02-24 2009-01-20 Nvidia Corporation Fan speed controller
US20090031155A1 (en) * 2007-07-26 2009-01-29 Qualcomm Incorporated Method and Apparatus for Adaptive Voltage Scaling Based on Instruction Usage
US7486060B1 (en) 2006-03-30 2009-02-03 Western Digital Technologies, Inc. Switching voltage regulator comprising a cycle comparator for dynamic voltage scaling
US20090037752A1 (en) * 2005-09-13 2009-02-05 Sony Computer Entertainment Inc. Power Supply Apparatus with System Controller
US20090079460A1 (en) * 2002-04-16 2009-03-26 Transmeta Corporation Systems and method for measuring negative bias thermal instability with a ring oscillator
US20090089604A1 (en) * 2007-09-28 2009-04-02 Malik Randhir S Apparatus, system, and method for event, time, and failure state recording mechanism in a power supply
US7551383B1 (en) 2006-06-28 2009-06-23 Western Digital Technologies, Inc. Adjusting voltage delivered to disk drive circuitry based on a selected zone
US7562233B1 (en) 2004-06-22 2009-07-14 Transmeta Corporation Adaptive control of operating and body bias voltages
US20090249088A1 (en) * 2008-03-28 2009-10-01 Samsung Electronics Co., Ltd. Semiconductor apparatus including power management integrated circuit
US7598731B1 (en) 2004-02-02 2009-10-06 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US20090307509A1 (en) * 2008-06-04 2009-12-10 Dell Products L.P. Dynamic cpu voltage regulator phase shedding
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US20100017636A1 (en) * 2006-12-07 2010-01-21 Renesas Technology Corp. Power supply system
US20100030500A1 (en) * 2008-07-29 2010-02-04 Gamal Refai-Ahmed Regulation of Power Consumption for Application-Specific Integrated Circuits
US20100083021A1 (en) * 2008-09-29 2010-04-01 Jose Allarey Voltage stabilization for clock signal frequency locking
US7692477B1 (en) 2003-12-23 2010-04-06 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US7719344B1 (en) 2003-12-23 2010-05-18 Tien-Min Chen Stabilization component for a substrate potential regulation circuit
US7730330B1 (en) 2000-06-16 2010-06-01 Marc Fleischmann System and method for saving and restoring a processor state without executing any instructions from a first instruction set
US7733189B1 (en) 2007-09-14 2010-06-08 Western Digital Technologies, Inc. Oscillator comprising foldover detection
US20100142075A1 (en) * 2007-08-20 2010-06-10 Sumeet Sanghvi Data Storage Drive with Reduced Power Consumption
US7739531B1 (en) 2005-03-04 2010-06-15 Nvidia Corporation Dynamic voltage scaling
US20100191991A1 (en) * 2009-01-29 2010-07-29 Dell Products, Lp System and Method for Using an On-DIMM Remote Sense for Performance and Power Optimization
US7774625B1 (en) 2004-06-22 2010-08-10 Eric Chien-Li Sheng Adaptive voltage control by accessing information stored within and specific to a microprocessor
US7786756B1 (en) 2002-12-31 2010-08-31 Vjekoslav Svilan Method and system for latchup suppression
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7849332B1 (en) * 2002-11-14 2010-12-07 Nvidia Corporation Processor voltage adjustment system and method
US7847619B1 (en) 2003-12-23 2010-12-07 Tien-Min Chen Servo loop for well bias voltage source
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7882369B1 (en) 2002-11-14 2011-02-01 Nvidia Corporation Processor performance adjustment system and method
US7886164B1 (en) 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
US20110055597A1 (en) * 2009-09-01 2011-03-03 Nvidia Corporation Regulating power using a fuzzy logic control system
US20110055596A1 (en) * 2009-09-01 2011-03-03 Nvidia Corporation Regulating power within a shared budget
US20110068859A1 (en) * 2009-09-18 2011-03-24 Sony Corporation Semiconductor device
US7949864B1 (en) 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
US8085020B1 (en) 2008-06-13 2011-12-27 Western Digital Technologies, Inc. Switching voltage regulator employing dynamic voltage scaling with hysteretic comparator
US20120117357A1 (en) * 2010-11-08 2012-05-10 Electronics And Telecommunications Research Institute Energy tile processor
US8370663B2 (en) 2008-02-11 2013-02-05 Nvidia Corporation Power management with dynamic frequency adjustments
US20130047007A1 (en) * 2002-12-30 2013-02-21 Stephen H. Gunther Dynamic voltage transitions
US8442784B1 (en) 2002-12-31 2013-05-14 Andrew Read Adaptive power control based on pre package characterization of integrated circuits
TWI405070B (en) * 2008-12-24 2013-08-11 Tatung Co Method for adjusting frequency and electronic apparatus and computer program product and computer accessible storage media to store program using the method
US20130297950A1 (en) * 2012-05-07 2013-11-07 Advanced Micro Devices, Inc., Voltage adjustment based on load line and power estimates
US20140063982A1 (en) * 2009-12-15 2014-03-06 Christopher P. Mozak Method and apparatus for dynamically adjusting voltage reference to optimize an i/o system
USRE44804E1 (en) 2000-05-09 2014-03-11 Palm, Inc. Dynamic performance adjustment of computation means
US8839006B2 (en) 2010-05-28 2014-09-16 Nvidia Corporation Power consumption reduction systems and methods
US8937404B1 (en) 2010-08-23 2015-01-20 Western Digital Technologies, Inc. Data storage device comprising dual mode independent/parallel voltage regulators
US8988140B2 (en) 2013-06-28 2015-03-24 International Business Machines Corporation Real-time adaptive voltage control of logic blocks
US8994346B2 (en) 2012-02-09 2015-03-31 Dell Products Lp Systems and methods for dynamic management of switching frequency for voltage regulation
US9134782B2 (en) 2007-05-07 2015-09-15 Nvidia Corporation Maintaining optimum voltage supply to match performance of an integrated circuit
US9256265B2 (en) 2009-12-30 2016-02-09 Nvidia Corporation Method and system for artificially and dynamically limiting the framerate of a graphics processing unit
US9471072B1 (en) 2013-11-14 2016-10-18 Western Digital Technologies, Inc Self-adaptive voltage scaling
US9830889B2 (en) 2009-12-31 2017-11-28 Nvidia Corporation Methods and system for artifically and dynamically limiting the display resolution of an application

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6816978B1 (en) * 2000-06-07 2004-11-09 Hewlett-Packard Development Company, L.P. System and method for adjusting an input voltage to a switching power supply while keeping the output voltage constant
US6766460B1 (en) * 2000-08-23 2004-07-20 Koninklijke Philips Electronics N.V. System and method for power management in a Java accelerator environment
US7111178B2 (en) * 2001-09-28 2006-09-19 Intel Corporation Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
JP2003186567A (en) * 2001-12-19 2003-07-04 Matsushita Electric Ind Co Ltd Microprocessor
CN100593158C (en) 2002-03-28 2010-03-03 华邦电子股份有限公司 Method and apparatus for adjusting execution performance adapted for electronic installation
EP1351117A1 (en) * 2002-04-03 2003-10-08 Hewlett-Packard Company Data processing system and method
US7210054B2 (en) * 2002-06-25 2007-04-24 Intel Corporation Maintaining processor execution during frequency transitioning
EP1387258A3 (en) * 2002-07-31 2008-01-02 Texas Instruments Incorporated Processor-processor synchronization
US7174468B2 (en) * 2002-08-01 2007-02-06 Texas Instruments Incorporated Methodology for coordinating and tuning application power
US7080267B2 (en) * 2002-08-01 2006-07-18 Texas Instruments Incorporated Methodology for managing power consumption in an application
US7013406B2 (en) * 2002-10-14 2006-03-14 Intel Corporation Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device
US7366932B2 (en) 2002-10-30 2008-04-29 Stmicroelectronics, Inc. Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation
US7080268B2 (en) * 2002-12-03 2006-07-18 Intel Corporation Method and apparatus for regulating power to electronic circuits
US8086884B2 (en) 2002-12-16 2011-12-27 Hewlett-Packard Development Company, L.P. System and method for implementing an integrated circuit having dynamically variable power limit
US7120804B2 (en) * 2002-12-23 2006-10-10 Intel Corporation Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency
US7206949B2 (en) 2003-03-18 2007-04-17 Matsushita Electric Industrial Co., Ltd. System and method for controlling a clock oscillator and power supply voltage based on the energy consumed for processing a predetermined amount of data
US7346791B2 (en) * 2003-03-26 2008-03-18 Matsushita Electric Industrial Co., Ltd. Method for controlling a clock frequency of an information processor in accordance with the detection of a start and a end of a specific processing section
US7024544B2 (en) * 2003-06-24 2006-04-04 Via-Cyrix, Inc. Apparatus and method for accessing registers in a processor
US20050108591A1 (en) * 2003-11-13 2005-05-19 Mendelson Geoffrey S. Method for reduced power consumption
GB2408357A (en) * 2003-11-18 2005-05-25 Motorola Inc Regulating a voltage supply to a semiconductor device
KR101136036B1 (en) 2003-12-24 2012-04-18 삼성전자주식회사 Processor system and method for reducing power consumption in idle mode
JP4524566B2 (en) * 2004-01-30 2010-08-18 セイコーエプソン株式会社 Asynchronous processor, an electro-optical device, and electronic apparatus
US7123522B2 (en) * 2004-03-10 2006-10-17 Micron Technology, Inc. Method and apparatus for achieving low power consumption during power down
JP4198644B2 (en) 2004-06-21 2008-12-17 富士通マイクロエレクトロニクス株式会社 The semiconductor integrated circuit
JP4623494B2 (en) * 2004-08-03 2011-02-02 ルネサスエレクトロニクス株式会社 Micro computer
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
JPWO2006087806A1 (en) * 2005-02-18 2008-07-03 富士通株式会社 Clock generator, a clock generating method, a clock generator, operation verification apparatus, operation verification method and operation verification program
KR100736748B1 (en) * 2005-09-14 2007-07-09 삼성전자주식회사 Computer and control method thereof
KR101354908B1 (en) * 2006-02-01 2014-01-22 삼성전자주식회사 Computer system
CN100485633C (en) * 2006-03-23 2009-05-06 鸿富锦精密工业(深圳)有限公司;鸿海精密工业股份有限公司 CPU frequency regulation circuit
US7685441B2 (en) * 2006-05-12 2010-03-23 Intel Corporation Power control unit with digitally supplied system parameters
TWI326818B (en) * 2006-12-15 2010-07-01 Inst Information Industry Dynamic voltage scheduling method, system thereof and record medium
DE102006061704B3 (en) * 2006-12-28 2008-03-27 Infineon Technologies Ag Integrated circuit operating method for use in applications with smart cards, involves increasing or reducing operating frequency of circuit such that during connection or disconnection of circuit part flow of entire circuit is not changing
US7853745B2 (en) * 2007-02-23 2010-12-14 Sony Corporation Electronic system with removable computing device and mutable functions
US7724149B2 (en) * 2007-06-11 2010-05-25 Hewlett-Packard Development Company, L.P. Apparatus, and associated method, for selecting distribution of processing tasks at a multi-processor data center
US20090049314A1 (en) * 2007-08-13 2009-02-19 Ali Taha Method and System for Dynamic Voltage and Frequency Scaling (DVFS)
US8064280B1 (en) * 2008-06-10 2011-11-22 Altera Corporation Scaleable look-up table based memory
CN101673232A (en) * 2008-09-11 2010-03-17 鸿富锦精密工业(深圳)有限公司;鸿海精密工业股份有限公司 Voltage regulation system
US8171319B2 (en) * 2009-04-16 2012-05-01 International Business Machines Corporation Managing processor power-performance states
KR101533572B1 (en) 2009-05-20 2015-07-03 삼성전자주식회사 Method of Power Management
FR2947924A1 (en) * 2009-07-07 2011-01-14 Thales Sa Method and apparatus for dynamic power management in a processor
DE102009047538B4 (en) * 2009-12-04 2018-02-22 Endress + Hauser Process Solutions Ag A method for optimizing the parameters setting from power supply parameters of a field device power supply module
US8438410B2 (en) * 2010-06-23 2013-05-07 Intel Corporation Memory power management via dynamic memory operation states
WO2012004863A1 (en) * 2010-07-07 2012-01-12 ルネサスエレクトロニクス株式会社 Data processing device and data processing system
US8665663B2 (en) * 2011-04-27 2014-03-04 Nanya Technology Corporation Memory circuit and control method thereof
FR3014215B1 (en) * 2013-12-03 2015-12-11 Thales Sa Method for computing resource management software applications
KR101842016B1 (en) 2013-12-10 2018-03-28 한국전자통신연구원 Method for dynamically controlling power in multicore environment
US9678556B2 (en) * 2014-02-10 2017-06-13 Qualcomm Incorporated Dynamic clock and voltage scaling with low-latency switching
US9496852B2 (en) * 2014-12-04 2016-11-15 Intel Corporation Digital current sensing in power controller

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0632360A1 (en) 1993-06-29 1995-01-04 Xerox Corporation Reducing computer power consumption by dynamic voltage and frequency variation
JPH0781186A (en) 1993-06-30 1995-03-28 Canon Inc Power-saving device for information-processing system
US5440520A (en) 1994-09-16 1995-08-08 Intel Corporation Integrated circuit device that selects its own supply voltage by controlling a power supply
US5727208A (en) * 1995-07-03 1998-03-10 Dell U.S.A. L.P. Method and apparatus for configuration of processor operating parameters
US5745375A (en) 1995-09-29 1998-04-28 Intel Corporation Apparatus and method for controlling power usage
JPH10149237A (en) 1996-11-20 1998-06-02 Kyushu Syst Joho Gijutsu Kenkyusho Semiconductor circuit
US5760636A (en) * 1996-06-28 1998-06-02 Intel Corporation Adjusting clock frequency and voltage supplied to a processor in a computer system
US5774704A (en) * 1996-07-29 1998-06-30 Silicon Graphics, Inc. Apparatus and method for dynamic central processing unit clock adjustment
US5812860A (en) 1996-02-12 1998-09-22 Intel Corporation Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption
US6141762A (en) * 1998-08-03 2000-10-31 Nicol; Christopher J. Power reduction in a multiprocessor digital signal processor based on processor load

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03224019A (en) * 1990-01-30 1991-10-03 Hitachi Ltd Clock card and information processor
JP3135718B2 (en) * 1992-11-11 2001-02-19 株式会社東芝 Switching control method of the electronic equipment system and cpu clock
US5430393A (en) * 1993-05-10 1995-07-04 Motorola, Inc. Integrated circuit with a low-power mode and clock amplifier circuit for same
JPH09231195A (en) * 1996-02-26 1997-09-05 Hitachi Ltd Micro computer
JP3472086B2 (en) * 1997-06-25 2003-12-02 キヤノン株式会社 Network interface devices and network interface process
JPH11110085A (en) * 1997-09-30 1999-04-23 Toshiba Corp Portable computer
US6425086B1 (en) * 1999-04-30 2002-07-23 Intel Corporation Method and apparatus for dynamic power control of a low power processor

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0632360A1 (en) 1993-06-29 1995-01-04 Xerox Corporation Reducing computer power consumption by dynamic voltage and frequency variation
JPH0781186A (en) 1993-06-30 1995-03-28 Canon Inc Power-saving device for information-processing system
US5440520A (en) 1994-09-16 1995-08-08 Intel Corporation Integrated circuit device that selects its own supply voltage by controlling a power supply
US5727208A (en) * 1995-07-03 1998-03-10 Dell U.S.A. L.P. Method and apparatus for configuration of processor operating parameters
US5745375A (en) 1995-09-29 1998-04-28 Intel Corporation Apparatus and method for controlling power usage
US5812860A (en) 1996-02-12 1998-09-22 Intel Corporation Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption
US5760636A (en) * 1996-06-28 1998-06-02 Intel Corporation Adjusting clock frequency and voltage supplied to a processor in a computer system
US5774704A (en) * 1996-07-29 1998-06-30 Silicon Graphics, Inc. Apparatus and method for dynamic central processing unit clock adjustment
JPH10149237A (en) 1996-11-20 1998-06-02 Kyushu Syst Joho Gijutsu Kenkyusho Semiconductor circuit
US6141762A (en) * 1998-08-03 2000-10-31 Nicol; Christopher J. Power reduction in a multiprocessor digital signal processor based on processor load

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Kaenel, Macken, DeGrauwe, "A Voltage Reduction Technique For Battery-Operated Systems", IEEE Journal of Solid State Circuits, vol. 25, No. 5, Oct. 1990, 5 pgs.
Microsoft Press Computer Dictionary, Second Edition, 1994, Microsoft Press, pp. 138 and 296.* *

Cited By (207)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519707B2 (en) * 1999-04-30 2003-02-11 Intel Corporation Method and apparatus for dynamic power control of a low power processor
US6826702B1 (en) * 1999-09-28 2004-11-30 Nec Corporation Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load
US7100061B2 (en) 2000-01-18 2006-08-29 Transmeta Corporation Adaptive power control
US8566627B2 (en) 2000-01-18 2013-10-22 Sameer Halepete Adaptive power control
US20020116650A1 (en) * 2000-01-18 2002-08-22 Sameer Halepete Adaptive power control
US8806247B2 (en) 2000-01-18 2014-08-12 Intellectual Venture Funding Llc Adaptive power control
USRE44804E1 (en) 2000-05-09 2014-03-11 Palm, Inc. Dynamic performance adjustment of computation means
US7730330B1 (en) 2000-06-16 2010-06-01 Marc Fleischmann System and method for saving and restoring a processor state without executing any instructions from a first instruction set
US8140872B1 (en) 2000-06-16 2012-03-20 Marc Fleischmann Restoring processor context in response to processor power-up
US6697952B1 (en) * 2000-07-24 2004-02-24 Dell Products, L.P. Margining processor power supply
US7050478B1 (en) * 2000-08-03 2006-05-23 International Business Machines Corporation Apparatus and method for synchronizing clock modulation with power supply modulation in a spread spectrum clock system
US6986068B2 (en) * 2000-09-22 2006-01-10 Sony Corporation Arithmetic processing system and arithmetic processing control method, task management system and task management method
US20030115239A1 (en) * 2000-09-22 2003-06-19 Atsushi Togawa Arithmetic processing system and arithmetic processing control method, task managemnt system and task management method, and storage medium
US7155621B2 (en) * 2000-09-30 2006-12-26 Intel Corporation Method and apparatus to enhance processor power management
US20020083356A1 (en) * 2000-09-30 2002-06-27 Xia Dai Method and apparatus to enhance processor power management
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US9436264B2 (en) 2000-10-23 2016-09-06 Intellectual Ventures Holding 81 Llc Saving power when in or transitioning to a static mode of a processor
US9690366B2 (en) 2000-10-23 2017-06-27 Intellectual Ventures Holding 81 Llc Saving power when in or transitioning to a static mode of a processor by using feedback-configured voltage regulator
US7870404B2 (en) * 2000-10-23 2011-01-11 Andrew Read Transitioning to and from a sleep state of a processor
US20070294555A1 (en) * 2000-10-23 2007-12-20 Andrew Read Saving power when in or transitioning to a static mode of a processor
US6988211B2 (en) * 2000-12-29 2006-01-17 Intel Corporation System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field
US20020087896A1 (en) * 2000-12-29 2002-07-04 Cline Leslie E. Processor performance state control
US20020104029A1 (en) * 2001-01-02 2002-08-01 Windbond Electronics Corp. Method and device for adjusting executing efficiency
US6907535B2 (en) * 2001-01-02 2005-06-14 Windbond Electronics Corp. Method and device for adjusting the executing efficiency of an electronic apparatus comprising a CPU
US7149910B2 (en) * 2001-06-19 2006-12-12 Hitachi, Ltd. Apparatus for processing a set of instructions initially at a low speed for a predetermined time then processing the set of instructions at a higher speed until completion
US20020194513A1 (en) * 2001-06-19 2002-12-19 Hitachi, Ltd. Semiconductor device and an operation control method of the semiconductor device
US20030009702A1 (en) * 2001-07-05 2003-01-09 Park Sung Jin Power supply for central processing unit
US7203847B2 (en) * 2001-07-05 2007-04-10 Lg Electronics Inc. Power supply for central processing unit
US20030020821A1 (en) * 2001-07-27 2003-01-30 Tohru Watanabe Imaging apparatus
US8004601B2 (en) * 2001-07-27 2011-08-23 Sanyo Electric Co., Ltd. Imaging apparatus using multiple regulators to decrease overall power consumption
US7633936B1 (en) 2001-07-31 2009-12-15 Lsi Corporation Time-slot interchange circuit
US8451827B2 (en) 2001-07-31 2013-05-28 Lsi Corporation Time-slot interchange circuit
US7346048B1 (en) 2001-07-31 2008-03-18 Lsi Logic Corporation Efficient high density voice processor
US20100046508A1 (en) * 2001-07-31 2010-02-25 Vogel Danny C Time-slot interchange circuit
US20080170153A1 (en) * 2001-08-01 2008-07-17 Sanyo Electric Co., Ltd. Image signal processor for use with a solid-state imaging device
US8045049B2 (en) 2001-08-01 2011-10-25 Semiconductor Components Industries, Llc Signal processor configured to process a first signal to generate a second signal
US6889331B2 (en) * 2001-08-29 2005-05-03 Analog Devices, Inc. Dynamic voltage control method and apparatus
US20030071657A1 (en) * 2001-08-29 2003-04-17 Analog Devices, Inc. Dynamic voltage control method and apparatus
US7245465B2 (en) * 2001-12-05 2007-07-17 Rohm Co., Ltd. Voltage regulator
US20030122530A1 (en) * 2001-12-05 2003-07-03 Takahiro Hikita Voltage regulator
US20030120958A1 (en) * 2001-12-26 2003-06-26 Zhang Kevin X. Method and apparatus for providing supply voltages for a processor
US6948079B2 (en) * 2001-12-26 2005-09-20 Intel Corporation Method and apparatus for providing supply voltages for a processor
US8593169B2 (en) 2002-04-16 2013-11-26 Kleanthes G. Koniaris Frequency specific closed loop feedback control of integrated circuits
US20080143372A1 (en) * 2002-04-16 2008-06-19 Transmeta Corporation Closed loop feedback control of integrated circuits
US20100060306A1 (en) * 2002-04-16 2010-03-11 Koniaris Kleanthes G Frequency specific closed loop feedback control of integrated circuits
US9407241B2 (en) 2002-04-16 2016-08-02 Kleanthes G. Koniaris Closed loop feedback control of integrated circuits
US9548725B2 (en) 2002-04-16 2017-01-17 Intellectual Ventures Holding 81 Llc Frequency specific closed loop feedback control of integrated circuits
US7671621B2 (en) 2002-04-16 2010-03-02 Koniaris Kleanthes G Closed loop feedback control of integrated circuits
US7667478B2 (en) 2002-04-16 2010-02-23 Shingo Suzuki System and method for measuring negative bias thermal instability with a ring oscillator
US20090079460A1 (en) * 2002-04-16 2009-03-26 Transmeta Corporation Systems and method for measuring negative bias thermal instability with a ring oscillator
US7626409B1 (en) 2002-04-16 2009-12-01 Koniaris Kleanthes G Frequency specific closed loop feedback control of integrated circuits
US8040149B2 (en) 2002-04-16 2011-10-18 Koniaris Kleanthes G Frequency specific closed loop feedback control of integrated circuits
US7868638B2 (en) 2002-04-16 2011-01-11 Shingo Suzuki System and method for measuring negative bias thermal instability with a ring oscillator
US20080195877A1 (en) * 2002-04-29 2008-08-14 Apple Inc. Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
US20070006003A1 (en) * 2002-04-29 2007-01-04 Youngs Lynn R Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
US7694162B2 (en) * 2002-04-29 2010-04-06 Apple Inc. Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
US8433940B2 (en) 2002-04-29 2013-04-30 Apple Inc. Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
US8166324B2 (en) 2002-04-29 2012-04-24 Apple Inc. Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
US20040025069A1 (en) * 2002-08-01 2004-02-05 Gary Scott P. Methods and systems for performing dynamic power management via frequency and voltage scaling
US7155617B2 (en) * 2002-08-01 2006-12-26 Texas Instruments Incorporated Methods and systems for performing dynamic power management via frequency and voltage scaling
US20040057324A1 (en) * 2002-08-08 2004-03-25 Hiroyuki Abe Semiconductor integrated circuit having controllable internal supply voltage
US7071768B2 (en) * 2002-08-08 2006-07-04 Fujitsu Limited Semiconductor integrated circuit having controllable internal supply voltage
US7653825B1 (en) * 2002-08-22 2010-01-26 Nvidia Corporation Method and apparatus for adaptive power consumption
US7634668B2 (en) 2002-08-22 2009-12-15 Nvidia Corporation Method and apparatus for adaptive power consumption
US20040039954A1 (en) * 2002-08-22 2004-02-26 Nvidia, Corp. Method and apparatus for adaptive power consumption
US20100131787A1 (en) * 2002-08-22 2010-05-27 Nvidia Corporation Adaptive Power Consumption Techniques
US20050144355A1 (en) * 2002-10-15 2005-06-30 Remote Data Systems, Inc. Computerized methods for data loggers
US7882369B1 (en) 2002-11-14 2011-02-01 Nvidia Corporation Processor performance adjustment system and method
US7849332B1 (en) * 2002-11-14 2010-12-07 Nvidia Corporation Processor voltage adjustment system and method
US7886164B1 (en) 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
US6996730B2 (en) * 2002-11-25 2006-02-07 Texas Instruments Incorporated Adjusting voltage supplied to a processor in response to clock frequency
US20040103330A1 (en) * 2002-11-25 2004-05-27 Bonnett William B. Adjusting voltage supplied to a processor in response to clock frequency
EP1422595A3 (en) * 2002-11-25 2005-02-09 Texas Instruments Inc. Adjusting voltage supplied to a processor in response to clock frequency
EP1422595A2 (en) * 2002-11-25 2004-05-26 Texas Instruments Inc. Adjusting voltage supplied to a processor in response to clock frequency
US7444524B2 (en) * 2002-12-30 2008-10-28 Intel Corporation Dynamic voltage transitions
US20110133720A1 (en) * 2002-12-30 2011-06-09 Gunther Stephen H Dynamic voltage transitions
US7890781B2 (en) 2002-12-30 2011-02-15 Intel Corporation Dynamic voltage transitions
US8707064B2 (en) 2002-12-30 2014-04-22 Intel Corporation Dynamic voltage transitions
US8719600B2 (en) 2002-12-30 2014-05-06 Intel Corporation Dynamic voltage transitions
CN1312546C (en) * 2002-12-30 2007-04-25 英特尔公司 Dynamic voltage transition
US20090015233A1 (en) * 2002-12-30 2009-01-15 Stephen H Gunther Dynamic voltage transitions
US8935546B2 (en) * 2002-12-30 2015-01-13 Intel Corporation Dynamic voltage transitions
US20130047007A1 (en) * 2002-12-30 2013-02-21 Stephen H. Gunther Dynamic voltage transitions
US7786756B1 (en) 2002-12-31 2010-08-31 Vjekoslav Svilan Method and system for latchup suppression
CN1745358B (en) 2002-12-31 2010-05-12 知识风险基金有限责任公司 Adaptive power control
US20040128566A1 (en) * 2002-12-31 2004-07-01 Burr James B. Adaptive power control
WO2004061634A2 (en) * 2002-12-31 2004-07-22 Transmeta Corporation Manufacture and operation of integrated circuit
US7941675B2 (en) 2002-12-31 2011-05-10 Burr James B Adaptive power control
US7949864B1 (en) 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
WO2004061634A3 (en) * 2002-12-31 2004-11-18 Transmeta Corp Manufacture and operation of integrated circuit
JP2009217830A (en) * 2002-12-31 2009-09-24 Transmeta Corp Microprocessor, integrated circuit module including microprocessor, electronic device, computer, method for operating and manufacturing microprocessor, and data structure for microprocessor
WO2004061635A2 (en) * 2002-12-31 2004-07-22 Transmeta Corporation Adaptive power control
WO2004061635A3 (en) * 2002-12-31 2004-11-11 Transmeta Corp Adaptive power control
US8442784B1 (en) 2002-12-31 2013-05-14 Andrew Read Adaptive power control based on pre package characterization of integrated circuits
US20040128567A1 (en) * 2002-12-31 2004-07-01 Tom Stewart Adaptive power control based on post package characterization of integrated circuits
US7953990B2 (en) 2002-12-31 2011-05-31 Stewart Thomas E Adaptive power control based on post package characterization of integrated circuits
US7194647B2 (en) * 2003-01-13 2007-03-20 Arm Limited Data processing performance control
US20040138833A1 (en) * 2003-01-13 2004-07-15 Arm Limited Data processing performance control
US20050003764A1 (en) * 2003-06-18 2005-01-06 Intel Corporation Current control circuit
CN1300660C (en) * 2003-12-05 2007-02-14 宏碁股份有限公司 Structure of dynamic management device power source and its method
US8629711B2 (en) 2003-12-23 2014-01-14 Tien-Min Chen Precise control component for a substarate potential regulation circuit
US8193852B2 (en) 2003-12-23 2012-06-05 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US8436675B2 (en) 2003-12-23 2013-05-07 Tien-Min Chen Feedback-controlled body-bias voltage source
US7692477B1 (en) 2003-12-23 2010-04-06 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US7719344B1 (en) 2003-12-23 2010-05-18 Tien-Min Chen Stabilization component for a substrate potential regulation circuit
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7847619B1 (en) 2003-12-23 2010-12-07 Tien-Min Chen Servo loop for well bias voltage source
US9100003B2 (en) 2004-02-02 2015-08-04 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US8222914B2 (en) 2004-02-02 2012-07-17 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US8319515B2 (en) 2004-02-02 2012-11-27 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US20090322412A1 (en) * 2004-02-02 2009-12-31 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US20090309626A1 (en) * 2004-02-02 2009-12-17 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US20100321098A1 (en) * 2004-02-02 2010-12-23 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US8420472B2 (en) 2004-02-02 2013-04-16 Kleanthes G. Koniaris Systems and methods for integrated circuits comprising multiple body biasing domains
US8697512B2 (en) 2004-02-02 2014-04-15 Kleanthes G. Koniaris Systems and methods for integrated circuits comprising multiple body biasing domains
US20110086478A1 (en) * 2004-02-02 2011-04-14 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7598731B1 (en) 2004-02-02 2009-10-06 Robert Paul Masleid Systems and methods for adjusting threshold voltage
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7782110B1 (en) 2004-02-02 2010-08-24 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body bias domains
US20050188230A1 (en) * 2004-02-20 2005-08-25 International Business Machines Corporation System and method of controlling power consumption in an electronic system
US7577859B2 (en) 2004-02-20 2009-08-18 International Business Machines Corporation System and method of controlling power consumption in an electronic system by applying a uniquely determined minimum operating voltage to an integrated circuit rather than a predetermined nominal voltage selected for a family of integrated circuits
US7479753B1 (en) 2004-02-24 2009-01-20 Nvidia Corporation Fan speed controller
WO2005094405A3 (en) * 2004-03-18 2005-12-29 Analog Devices Inc Closed loop dynamic power management
WO2005094405A2 (en) * 2004-03-18 2005-10-13 Analog Devices, Inc. Closed loop dynamic power management
CN100470448C (en) 2004-03-31 2009-03-18 英特尔公司 Method, apparatus and system for enabling and disabling voltage regulator controllers
WO2005098577A3 (en) * 2004-03-31 2005-12-22 Intel Corp Method, apparatus and system for enabling and disabling voltage regulator controllers
US20050223259A1 (en) * 2004-03-31 2005-10-06 Lehwalder Philip R Method, apparatus and system for enabling and disabling voltage regulator controllers
WO2005098577A2 (en) * 2004-03-31 2005-10-20 Intel Corporation Method, apparatus and system for enabling and disabling voltage regulator controllers
US7376854B2 (en) 2004-03-31 2008-05-20 Intel Corporation System for enabling and disabling voltage regulator controller of electronic appliance according to a series of delay times assigned to voltage regulator controllers
KR100860145B1 (en) * 2004-03-31 2008-09-24 인텔 코오퍼레이션 Method, apparatus and system for enabling and disabling voltage regulator controllers
US7447919B2 (en) 2004-04-06 2008-11-04 Hewlett-Packard Development Company, L.P. Voltage modulation for increased reliability in an integrated circuit
GB2412982A (en) * 2004-04-06 2005-10-12 Hewlett Packard Development Co Method of decreasing the soft errors produced by an integrated circuit by identifying the required power supply voltage
US20050223251A1 (en) * 2004-04-06 2005-10-06 Liepe Steven F Voltage modulation for increased reliability in an integrated circuit
US20050278561A1 (en) * 2004-06-11 2005-12-15 Samsung Electronics Co., Ltd. Electronic devices and operational methods that change clock frequencies that are applied to a central processing unit and a main system bus
US7500124B2 (en) * 2004-06-11 2009-03-03 Samsung Electronics Co., Ltd. Electronic devices and operational methods that change clock frequencies that are applied to a central processing unit and a main system bus
US8370658B2 (en) 2004-06-22 2013-02-05 Eric Chen-Li Sheng Adaptive control of operating and body bias voltages
US9026810B2 (en) * 2004-06-22 2015-05-05 Intellectual Venture Funding Llc Adaptive control of operating and body bias voltages
US7774625B1 (en) 2004-06-22 2010-08-10 Eric Chien-Li Sheng Adaptive voltage control by accessing information stored within and specific to a microprocessor
US7562233B1 (en) 2004-06-22 2009-07-14 Transmeta Corporation Adaptive control of operating and body bias voltages
US20100257389A1 (en) * 2004-06-22 2010-10-07 Eric Chen-Li Sheng Adaptive control of operating and body bias voltages
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7205805B1 (en) 2004-11-02 2007-04-17 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
US7129763B1 (en) 2004-11-08 2006-10-31 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay
US20060129852A1 (en) * 2004-12-10 2006-06-15 Bonola Thomas J Bios-based systems and methods of processor power management
US7536567B2 (en) 2004-12-10 2009-05-19 Hewlett-Packard Development Company, L.P. BIOS-based systems and methods of processor power management
US8112048B2 (en) * 2004-12-20 2012-02-07 Marvell World Trade Ltd. Method and apparatus to manage power consumption of a semiconductor device
US20080224685A1 (en) * 2004-12-20 2008-09-18 Amit Dor Method and apparatus to manage power consumption of a semiconductor device
US20070085712A1 (en) * 2005-02-09 2007-04-19 Sony Corporation Decoding method, decoding device, and program for the same
US7307550B2 (en) * 2005-02-09 2007-12-11 Sony Corporation Decoding method, decoding device, and program for the same
US20060193113A1 (en) * 2005-02-28 2006-08-31 International Business Machines Corporation Controlling a surface temperature of a portable computer for user comfort in response to motion detection
US7739531B1 (en) 2005-03-04 2010-06-15 Nvidia Corporation Dynamic voltage scaling
US9063729B2 (en) 2005-06-30 2015-06-23 Intel Corporation Device, system and method of generating an execution instruction based on a memory-access instruction
US8281083B2 (en) 2005-06-30 2012-10-02 Intel Corporation Device, system and method of generating an execution instruction based on a memory-access instruction
US20070005910A1 (en) * 2005-06-30 2007-01-04 Alon Naveh Device, system and method of generating an execution instruction based on a memory-access instruction
US20090037752A1 (en) * 2005-09-13 2009-02-05 Sony Computer Entertainment Inc. Power Supply Apparatus with System Controller
US8051304B2 (en) 2005-09-13 2011-11-01 Sony Computer Entertainment Inc. Power supply apparatus with system controller
US8051310B2 (en) 2005-12-29 2011-11-01 Lenovo (Beijing) Limited Method for reducing power consumption of processor
WO2007073632A1 (en) * 2005-12-29 2007-07-05 Lenovo (Beijing) Limited Method for reducing power consumption of processor
US20090013201A1 (en) * 2005-12-29 2009-01-08 Lenovo (Beijing) Limited Method for Reducing Power Consumption of Processor
US7486060B1 (en) 2006-03-30 2009-02-03 Western Digital Technologies, Inc. Switching voltage regulator comprising a cycle comparator for dynamic voltage scaling
US8912778B1 (en) 2006-03-30 2014-12-16 Western Digital Technologies, Inc. Switching voltage regulator employing current pre-adjust based on power mode
US7551383B1 (en) 2006-06-28 2009-06-23 Western Digital Technologies, Inc. Adjusting voltage delivered to disk drive circuitry based on a selected zone
US7330019B1 (en) 2006-10-31 2008-02-12 Western Digital Technologies, Inc. Adjusting on-time for a discontinuous switching voltage regulator
US20100017636A1 (en) * 2006-12-07 2010-01-21 Renesas Technology Corp. Power supply system
US9134782B2 (en) 2007-05-07 2015-09-15 Nvidia Corporation Maintaining optimum voltage supply to match performance of an integrated circuit
US8725488B2 (en) 2007-07-26 2014-05-13 Qualcomm Incorporated Method and apparatus for adaptive voltage scaling based on instruction usage
US20090031155A1 (en) * 2007-07-26 2009-01-29 Qualcomm Incorporated Method and Apparatus for Adaptive Voltage Scaling Based on Instruction Usage
US7872825B2 (en) * 2007-08-20 2011-01-18 Agere Systems Inc. Data storage drive with reduced power consumption
US20100142075A1 (en) * 2007-08-20 2010-06-10 Sumeet Sanghvi Data Storage Drive with Reduced Power Consumption
US7733189B1 (en) 2007-09-14 2010-06-08 Western Digital Technologies, Inc. Oscillator comprising foldover detection
US20090089604A1 (en) * 2007-09-28 2009-04-02 Malik Randhir S Apparatus, system, and method for event, time, and failure state recording mechanism in a power supply
US7908505B2 (en) * 2007-09-28 2011-03-15 International Business Machines Corporation Apparatus, system, and method for event, time, and failure state recording mechanism in a power supply
US8370663B2 (en) 2008-02-11 2013-02-05 Nvidia Corporation Power management with dynamic frequency adjustments
US8775843B2 (en) 2008-02-11 2014-07-08 Nvidia Corporation Power management with dynamic frequency adjustments
US20090249088A1 (en) * 2008-03-28 2009-10-01 Samsung Electronics Co., Ltd. Semiconductor apparatus including power management integrated circuit
US8135968B2 (en) * 2008-03-28 2012-03-13 Samsung Electronics Co., Ltd. Semiconductor apparatus including power management integrated circuit
US8028182B2 (en) 2008-06-04 2011-09-27 Dell Products L.P. Dynamic CPU voltage regulator phase shedding
US20090307509A1 (en) * 2008-06-04 2009-12-10 Dell Products L.P. Dynamic cpu voltage regulator phase shedding
US8924750B2 (en) 2008-06-04 2014-12-30 Dell Products L.P. Dynamic CPU voltage regulator phase shedding
US9436256B2 (en) 2008-06-04 2016-09-06 Dell Products L.P. Dynamic CPU voltage regulator phase shedding
US8085020B1 (en) 2008-06-13 2011-12-27 Western Digital Technologies, Inc. Switching voltage regulator employing dynamic voltage scaling with hysteretic comparator
CN102165389A (en) * 2008-07-29 2011-08-24 Ati技术无限责任公司 Regulation of power consumption for application-specific integrated circuits
US20100030500A1 (en) * 2008-07-29 2010-02-04 Gamal Refai-Ahmed Regulation of Power Consumption for Application-Specific Integrated Circuits
US20100083021A1 (en) * 2008-09-29 2010-04-01 Jose Allarey Voltage stabilization for clock signal frequency locking
US8122270B2 (en) * 2008-09-29 2012-02-21 Intel Corporation Voltage stabilization for clock signal frequency locking
TWI405070B (en) * 2008-12-24 2013-08-11 Tatung Co Method for adjusting frequency and electronic apparatus and computer program product and computer accessible storage media to store program using the method
US8205107B2 (en) * 2009-01-29 2012-06-19 Dell Products, Lp System and method for using an on-DIMM remote sense for creating performance and power optimization
US20100191991A1 (en) * 2009-01-29 2010-07-29 Dell Products, Lp System and Method for Using an On-DIMM Remote Sense for Performance and Power Optimization
US8826048B2 (en) 2009-09-01 2014-09-02 Nvidia Corporation Regulating power within a shared budget
US8700925B2 (en) 2009-09-01 2014-04-15 Nvidia Corporation Regulating power using a fuzzy logic control system
US20110055597A1 (en) * 2009-09-01 2011-03-03 Nvidia Corporation Regulating power using a fuzzy logic control system
US20110055596A1 (en) * 2009-09-01 2011-03-03 Nvidia Corporation Regulating power within a shared budget
US20110068859A1 (en) * 2009-09-18 2011-03-24 Sony Corporation Semiconductor device
US20140063982A1 (en) * 2009-12-15 2014-03-06 Christopher P. Mozak Method and apparatus for dynamically adjusting voltage reference to optimize an i/o system
US9330734B2 (en) * 2009-12-15 2016-05-03 Intel Corporation Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
US20140119137A1 (en) * 2009-12-15 2014-05-01 Christopher P. Mozak Method and apparatus for dynamically adjusting voltage reference to optimize an i/o system
US9373365B2 (en) * 2009-12-15 2016-06-21 Intel Corporation Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
US9256265B2 (en) 2009-12-30 2016-02-09 Nvidia Corporation Method and system for artificially and dynamically limiting the framerate of a graphics processing unit
US9830889B2 (en) 2009-12-31 2017-11-28 Nvidia Corporation Methods and system for artifically and dynamically limiting the display resolution of an application
US8839006B2 (en) 2010-05-28 2014-09-16 Nvidia Corporation Power consumption reduction systems and methods
US8937404B1 (en) 2010-08-23 2015-01-20 Western Digital Technologies, Inc. Data storage device comprising dual mode independent/parallel voltage regulators
US20120117357A1 (en) * 2010-11-08 2012-05-10 Electronics And Telecommunications Research Institute Energy tile processor
US8994346B2 (en) 2012-02-09 2015-03-31 Dell Products Lp Systems and methods for dynamic management of switching frequency for voltage regulation
US9021276B2 (en) * 2012-05-07 2015-04-28 Ati Technologies Ulc Voltage adjustment based on load line and power estimates
US20130297950A1 (en) * 2012-05-07 2013-11-07 Advanced Micro Devices, Inc., Voltage adjustment based on load line and power estimates
US8988140B2 (en) 2013-06-28 2015-03-24 International Business Machines Corporation Real-time adaptive voltage control of logic blocks
US9471072B1 (en) 2013-11-14 2016-10-18 Western Digital Technologies, Inc Self-adaptive voltage scaling

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