CN105977182A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN105977182A
CN105977182A CN201510556151.XA CN201510556151A CN105977182A CN 105977182 A CN105977182 A CN 105977182A CN 201510556151 A CN201510556151 A CN 201510556151A CN 105977182 A CN105977182 A CN 105977182A
Authority
CN
China
Prior art keywords
substrate
semiconductor device
labelling
region
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510556151.XA
Other languages
English (en)
Inventor
铃木拓马
藤泽博文
白川努
佐野贤也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN105977182A publication Critical patent/CN105977182A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67282Marking devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54406Marks applied to semiconductor devices or parts comprising alphanumeric information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54433Marks applied to semiconductor devices or parts containing identification or tracking information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602Diamond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Laser Beam Processing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本发明的实施方式提供一种能够减少器件不良的半导体装置及其制造方法。实施方式的半导体装置包括:常压下为非液相的材料的单晶衬底;以及识别标记,设置于所述衬底,且具有非晶质的所述材料的区域、或偏离了化学计量的所述材料的区域。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2015-48889号(申请日:2015年3月11日)为基础申请案的优先权。本申请案通过参照该基础申请案而包括基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
为了事后确认半导体芯片的制造信息等,有时对半导体芯片附加识别标记(追踪能力ID)。例如,利用激光将识别标记压印到半导体芯片的元件区域以外的空间。然而,有利用激光形成识别标记时产生的碎片(debris)或灰尘在元件区域上飞散,而成为半导体芯片的器件不良的原因的担心。
发明内容
本发明所欲解决的课题在于能够减少器件不良的半导体装置。
实施方式的半导体装置包括:常压下为非液相的材料的单晶的衬底;以及识别标记,设置于所述衬底,且具有非晶质的所述材料的区域或偏离了化学计量(stoichiometry)的所述材料的区域。
附图说明
图1(a)~(c)是第一实施方式的半导体装置的模式图。
图2是第一实施方式的变形例的识别标记的剖面图。
图3(a)及(b)是第二实施方式的半导体装置的模式图。
图4(a)及(b)是表示实施例及比较例的观察结果的图。
图5是实施例及比较例的识别标记的照片。
具体实施方式
以下,一面参照附图一面对本发明的实施方式进行说明。另外,以下的说明中,对相同构件等附上相同符号,并对已说明的构件等适当省略其说明。
(第一实施方式)
本实施方式的半导体装置包括:常压下为非液相的材料的单晶的衬底;及识别标记,设置于衬底上,且具有非晶质的所述材料的区域或偏离了化学计量的所述材料的区域。
图1是本实施方式的半导体装置的模式图。图1(a)是本实施方式的半导体装置的立体图。图1(b)是本实施方式的识别标记的俯视图。图1(c)是本实施方式的识别标记的剖面图。图1(c)是图1(b)的AA'剖面图。本实施方式的半导体装置是使用了SiC衬底的萧特基位障二极管(SBD,Schotky barrier diode)。
SBD100具备半导体衬底(衬底)10、阳极电极12、阴极电极(未图示)、及识别标记14。SBD100是经单片化的半导体芯片。
半导体衬底10是常压下为非液相的材料的单晶的衬底。半导体衬底10的材料例如是SiC(碳化硅)。关于常压下为非液相的材料,除SiC之外,也可列举GaN(氮化镓)、金刚石、蓝宝石等。
半导体衬底10具有表面、背面及侧面。在半导体衬底10的表面设置着阳极电极12。在半导体衬底10的背面设置着阴极电极。在阳极电极12与阴极电极之间的半导体衬底10形成有元件区域。
识别标记14设置于半导体衬底10的表面的元件区域以外的区域。识别标记14如图1(b)、图1(c)所示具备区域14a。利用区域14a例如形成字串。另外,也可利用区域14a形成一维或二维的条码。
区域14a例如为非晶质的SiC。区域14a例如为单晶的SiC非晶质化而成的区域。
而且,区域14a例如为偏离化学计量的SiC。区域14a例如为SiC的组成经调制的区域。例如,为SiC的硅/碳组成比(Si/C组成比)小于1的区域。
区域14a中,因为是非晶质或偏离化学计量,所以会产生漫反射。因此,获得识别标记14的光学视认性。
识别标记14的表面的最大高度(Rz)为100nm以下。识别标记14的表面的最大高度(Rz)理想的是50nm以下
另外,最大高度(Rz)为粗糙度曲线的顶部最大高度与底部最大深度之和。换句话说,为表面的凹凸的最大的高低差。本说明书中,由纳米(nm)表示最大高度(Rz)。
本实施方式的SBD100的制造方法对常压下为非液相的材料的单晶的衬底照射能量大于所述材料的带隙的激光,将衬底非晶质化或将衬底的组成进行调制,由此形成识别标记。
首先,利用公知的制造方法制造SBD100的元件区域。然后,在半导体衬底10的表面形成识别标记14。
识别标记14是对半导体衬底10的表面照射能量大于半导体衬底10的材料的带隙的激光而形成。通过照射激光,将半导体衬底10非晶质化或将半导体衬底10的组成进行调制,而形成区域14a。
就激光而言,理想的是脉冲激光。就激光而言,理想的是飞秒激光。
通过照射能量大于半导体衬底10的带隙的激光,可将半导体衬底10的分子间键结直接切断、非晶质化或进行组成的调制。激光的能量可由激光的波长确定。
在半导体衬底10为SiC的情况下,例如使用YAG激光的四次谐波(FHG)作为激光。YAG激光的FHG的波长为266nm,能量为4.66eV。SiC的带隙为3.26eV,因此激光的能量大于SiC的带隙能量。
接下来,对本实施方式的作用及效果进行说明。
作为使用激光在衬底的表面形成识别标记的方法,有利用消融等深挖衬底的表面而形成凹凸的方法。该方法被称作硬标记(hard marking)。硬标记中,形成凹凸时,因悬浮物引起的碎片或灰尘在元件区域上飞散。因此,有产生配线的短路等器件不良的担心。
为了防止碎片或灰尘的发生,例如,在衬底为硅的情况下,有对激光的照射条件进行控制,仅使衬底的表面熔融而形成凹凸的方法。该方法被称作软标记(soft marking)。软标记因不会产生碎片或灰尘,所以适合作为在半导体芯片形成识别标记的方法。
然而,在如衬底为SiC般在常压下为非液相的材料的情况下,无法使衬底的表面熔融。因此,无法执行软标记。
本实施方式中,通过对激光的照射条件进行控制,将半导体衬底10非晶质化或将半导体衬底10的组成进行调制,由此形成区域14a。因此,区域14a的半导体衬底10不会因激光的照射而悬浮,从而抑制碎片或灰尘的发生。因此,抑制伴随识别标记14的形成的器件不良的发生。
而且,本实施方式的识别标记14因区域14a为非晶质或偏离化学计量,而可利用X射线进行识别。因此,例如,即便在由模具树脂覆盖SBD100后,也可使用X射线检查装置,非破坏性地读取识别标记14的信息。
图2是本实施方式的变形例的识别标记的剖面图。区域14a的半导体衬底10的表面侧为保持化学计量的单晶,就该点而言与实施方式不同。本变形例的区域14a例如可通过将激光的焦点位置设定得比半导体衬底10的表面深而形成。
SiC衬底、GaN衬底、金刚石衬底、蓝宝石衬底为透明衬底,因此即便区域14a形成于半导体衬底10内部也可视认。根据本变形例,进一步抑制自半导体衬底10的表面的碎片或灰尘的发生。因此,可进一步抑制伴随识别标记14的形成的器件不良的发生。
以上,根据本实施方式,可实现能够减少由识别标记的形成引起的器件不良的半导体装置及其制造方法。而且,可实现具备即便在由模具树脂覆盖后也可非破坏性地读取信息的识别标记的半导体装置及其制造方法。
(第二实施方式)
本实施方式的半导体装置除在衬底的侧面设置着识别标记以外,与第一实施方式相同。因此,关于与第一实施方式重复的内容,省略记述。
图3是本实施方式的半导体装置的模式图。图3(a)是本实施方式的半导体装置的立体图。图3(b)是本实施方式的识别标记的俯视图。本实施方式的半导体装置是使用了SiC衬底的萧特基位障二极管(SBD)。
SBD200具备半导体衬底(衬底)10、阳极电极12、阴极电极(未图示)、及识别标记14。SBD200是经单片化的半导体芯片。
半导体衬底10具有表面、背面及侧面。在半导体衬底10的表面设置着阳极电极12。在半导体衬底10的背面设置着阴极电极。在阳极电极12与阴极电极之间的半导体衬底10形成有元件区域。
识别标记14设置于半导体衬底10的侧面。通过将识别标记14设置于半导体衬底10的侧面,可削减半导体衬底10的表面的识别标记形成用的区域。因此,可提高半导体衬底10的表面的元件区域的占有率。由此,SBD200的微细化成为可能。
根据本实施方式,除实现第一实施方式的效果之外,也可实现能够微细化的半导体装置。
[实施例]
以下,对实施例进行记述。
(实施例)
对SiC衬底的表面照射激光,将SiC衬底非晶质化或将SiC衬底的组成进行调制而形成识别标记。作为激光,使用YAG激光的四次谐波(FHG)的脉冲激光。YAG激光的FHG的波长为266nm。
(比较例)
对SiC衬底的表面照射激光,利用消融在SiC衬底表面设置凹凸而形成识别标记。将每一脉冲的能量设定得高于实施例。每一脉冲的能量以外的条件与实施例相同。
图4是表示实施例及比较例的识别标记的利用3D测量激光显微镜观察的结果的图。图4(a)是实施例的结果,图4(b)是比较例的结果。图4(a)、图4(b)各自表示识别标记的照片、识别标记的光量分布、识别标记的表面高度分布。
实施例的条件中,识别标记的表面的最大高度(Rz)为100nm以下。比较例的识别标记的表面的最大高度(Rz)为1μm以上。
图5是实施例及比较例的识别标记的可视光的照片。实施例的条件下获得充分的光学视认性。
第一及第二实施方式中,以SBD为例进行了说明,但PIN二极管、MISFET(MetalIusulator Semiconductor Field Effect Transistor,金属绝缘半导体场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)等其他器件中也可适用本发明。
已对本发明的几个实施方式进行了说明,但这些实施方式是作为示例而提示,并不意图限定发明的范围。这些新颖的实施方式可由其他各种形态实施,在不脱离发明的主旨的范围内,可进行各种省略、置换、变更。例如,也可将一实施方式的构成要素与其他实施方式的构成要素进行置换。这些实施方式或其变形包含在发明的范围或主旨内,并且包含于权利要求所记载的发明及其均等的范围内。
[符号的说明]
10 半导体衬底(衬底)
14 识别标记
14a 区域
100 SBD(半导体装置)
200 SBD(半导体装置)

Claims (8)

1.一种半导体装置,其特征在于包括:
常压下为非液相的材料的单晶衬底;以及
识别标记,设置于所述衬底,具有非晶质的所述材料的区域、或偏离了化学计量的所述材料的区域。
2.根据权利要求1所述的半导体装置,其特征在于:所述材料为SiC。
3.根据权利要求1或2所述的半导体装置,其特征在于:所述识别标记的表面的最大高度为100nm以下。
4.根据权利要求1或2所述的半导体装置,其特征在于:所述衬底还包括元件区域,所述衬底具有表面、背面及侧面,所述识别标记设置于所述表面的所述元件区域以外的区域。
5.根据权利要求1或2所述的半导体装置,其特征在于:所述衬底具有表面、背面及侧面,在所述侧面设置着所述识别标记。
6.一种半导体装置的制造方法,其特征在于:对常压下为非液相的材料的单晶的衬底照射能量大于所述材料的带隙的激光,将所述衬底非晶质化或将所述衬底的组成进行调制,由此形成识别标记。
7.根据权利要求6所述的半导体装置的制造方法,其特征在于:所述材料为SiC。
8.根据权利要求6或7所述的半导体装置的制造方法,其特征在于:所述识别标记的表面的最大高度为100nm以下。
CN201510556151.XA 2015-03-11 2015-09-02 半导体装置及其制造方法 Pending CN105977182A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015048889A JP2016171149A (ja) 2015-03-11 2015-03-11 半導体装置およびその製造方法
JP2015-048889 2015-03-11

Publications (1)

Publication Number Publication Date
CN105977182A true CN105977182A (zh) 2016-09-28

Family

ID=56888148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510556151.XA Pending CN105977182A (zh) 2015-03-11 2015-09-02 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US9799608B2 (zh)
JP (1) JP2016171149A (zh)
CN (1) CN105977182A (zh)
TW (1) TWI604592B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109725452A (zh) * 2017-10-31 2019-05-07 乐金显示有限公司 显示装置
CN114121898A (zh) * 2022-01-28 2022-03-01 甬矽电子(宁波)股份有限公司 晶圆级芯片封装结构、封装方法和电子设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6946153B2 (ja) * 2017-11-16 2021-10-06 株式会社ディスコ ウエーハの生成方法およびウエーハ生成装置
US11562928B2 (en) * 2019-01-25 2023-01-24 Omnivision Technologies, Inc. Laser marked code pattern for representing tracing number of chip
KR20210079614A (ko) * 2019-12-20 2021-06-30 엘지디스플레이 주식회사 유기발광 표시장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010020750A1 (en) * 2000-03-07 2001-09-13 Teiichirou Chiba Semiconductor wafer and method of specifying crystallographic axis orientation thereof
CN1384544A (zh) * 2001-03-21 2002-12-11 株式会社东芝 具有id标记的半导体晶片,及从中生产半导体器件的方法和设备
JP2006043717A (ja) * 2004-08-02 2006-02-16 Sumitomo Heavy Ind Ltd マーキング方法、単結晶炭化ケイ素製部材の製造方法、及び単結晶炭化ケイ素製部材

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114129A (ja) 1998-10-09 2000-04-21 Toshiba Corp 半導体装置及びその製造方法
TW454238B (en) 1999-11-25 2001-09-11 Komatsu Mfg Co Ltd Form of microscopic dot mark using laser beam and marking method thereof
US6812477B2 (en) 2002-12-04 2004-11-02 Texas Instruments Incorporated Integrated circuit identification
JP2006203063A (ja) * 2005-01-21 2006-08-03 Toshiba Corp 半導体基板及び半導体基板の製造方法
TWI349973B (en) 2007-10-31 2011-10-01 Chipmos Technologies Inc Method of fabricating alignment mark for cdim package structure
JP5078725B2 (ja) 2008-04-22 2012-11-21 ラピスセミコンダクタ株式会社 半導体装置
JP5522914B2 (ja) 2008-09-11 2014-06-18 株式会社半導体エネルギー研究所 Soi基板の作製方法
DE102008059756A1 (de) 2008-12-01 2010-06-10 Tesa Se Verfahren zum Markieren oder Beschriften eines Werkstücks
JP2010283070A (ja) 2009-06-03 2010-12-16 Fujikura Ltd 半導体装置の製造方法
JP2012028664A (ja) 2010-07-27 2012-02-09 Renesas Electronics Corp 半導体装置の製造方法
WO2012042668A1 (ja) * 2010-10-01 2012-04-05 株式会社メイコー 部品内蔵基板及び部品内蔵基板の製造方法
JP2013093493A (ja) * 2011-10-27 2013-05-16 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JP6155866B2 (ja) * 2012-07-10 2017-07-05 日立金属株式会社 高融点材料単結晶基板への識別マークの形成方法、及び高融点材料単結晶基板
KR102506703B1 (ko) * 2014-12-16 2023-03-03 데카 테크놀로지 유에스에이 인코포레이티드 반도체 패키지를 마킹하는 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010020750A1 (en) * 2000-03-07 2001-09-13 Teiichirou Chiba Semiconductor wafer and method of specifying crystallographic axis orientation thereof
CN1384544A (zh) * 2001-03-21 2002-12-11 株式会社东芝 具有id标记的半导体晶片,及从中生产半导体器件的方法和设备
JP2006043717A (ja) * 2004-08-02 2006-02-16 Sumitomo Heavy Ind Ltd マーキング方法、単結晶炭化ケイ素製部材の製造方法、及び単結晶炭化ケイ素製部材

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109725452A (zh) * 2017-10-31 2019-05-07 乐金显示有限公司 显示装置
US11217537B2 (en) 2017-10-31 2022-01-04 Lg Display Co., Ltd. Display device including identification number pattern
CN114121898A (zh) * 2022-01-28 2022-03-01 甬矽电子(宁波)股份有限公司 晶圆级芯片封装结构、封装方法和电子设备

Also Published As

Publication number Publication date
US20160268212A1 (en) 2016-09-15
JP2016171149A (ja) 2016-09-23
TWI604592B (zh) 2017-11-01
US9799608B2 (en) 2017-10-24
TW201633490A (zh) 2016-09-16

Similar Documents

Publication Publication Date Title
CN105977182A (zh) 半导体装置及其制造方法
DE102017128441B4 (de) Lichtemittierende Vorrichtung
CN105340088B (zh) 半导体发光装置
US20200091225A1 (en) Micro led display panel and manufacturing method thereof
CN102714152A (zh) 功能元件及其制造方法
TW200605151A (en) Lift-off process for gan films formed on sic substrates and devices fabricated using the method
TW200717862A (en) Method of removing the growth substrate of a semiconductor light-emitting device
TW200947747A (en) Manufacturing method of semiconductor device
DE102014016854A1 (de) Lichtemittierende Vorrichtung und Verfahren zur Herstellung derselben
DE102012102420B4 (de) Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
CN104916556B (zh) 芯片排列方法
JP6593237B2 (ja) 発光素子の製造方法、及び発光装置の製造方法
DE102013202902B4 (de) Verfahren zum Herstellen eines optoelektronischen Bauelements
IT202000020566A1 (it) Procedimento per fabbricare dispositivi a semiconduttore e dispositivo corrispondente
CN104205316B (zh) 半导体装置的制造方法以及制造装置
US20120094405A1 (en) Method for manufacturing led package
JP6471641B2 (ja) 発光装置の製造方法
US11362242B2 (en) Light-emitting device
TW201445766A (zh) 半導體基板之製造方法
CN206163512U (zh) 一种紫外外延片结构
TWI667742B (zh) Semiconductor device and method of manufacturing same
US9864071B2 (en) Bonding method with peripheral trench
CN104064518B (zh) 刻划方法及刻划装置
CN205194732U (zh) 一种识别芯片
CN105140231B (zh) 薄膜晶体管阵列基板及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160928

WD01 Invention patent application deemed withdrawn after publication