CN105874716B - 延迟锁定环中的自动相位同步 - Google Patents

延迟锁定环中的自动相位同步 Download PDF

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Publication number
CN105874716B
CN105874716B CN201580003481.4A CN201580003481A CN105874716B CN 105874716 B CN105874716 B CN 105874716B CN 201580003481 A CN201580003481 A CN 201580003481A CN 105874716 B CN105874716 B CN 105874716B
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CN
China
Prior art keywords
delay line
delay
main
line signal
signal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN201580003481.4A
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English (en)
Chinese (zh)
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CN105874716A (zh
Inventor
B.奥德达拉
D.潘乔利
V.拉斯塔吉
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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Publication of CN105874716A publication Critical patent/CN105874716A/zh
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
CN201580003481.4A 2014-01-30 2015-01-28 延迟锁定环中的自动相位同步 Expired - Fee Related CN105874716B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
IN427/CHE/2014 2014-01-30
US14/461,921 US9148157B2 (en) 2014-01-30 2014-08-18 Auto-phase synchronization in delay locked loops
US14/461,921 2014-08-18
PCT/US2015/013273 WO2015116670A1 (en) 2014-01-30 2015-01-28 Auto-phase synchronization in delay locked loops
IN427CH2014 IN2014CH00427A (enExample) 2014-01-30 2015-01-28

Publications (2)

Publication Number Publication Date
CN105874716A CN105874716A (zh) 2016-08-17
CN105874716B true CN105874716B (zh) 2019-04-09

Family

ID=53680069

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580003481.4A Expired - Fee Related CN105874716B (zh) 2014-01-30 2015-01-28 延迟锁定环中的自动相位同步

Country Status (5)

Country Link
US (1) US9148157B2 (enExample)
KR (1) KR101947580B1 (enExample)
CN (1) CN105874716B (enExample)
IN (1) IN2014CH00427A (enExample)
WO (1) WO2015116670A1 (enExample)

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JP2015076711A (ja) * 2013-10-08 2015-04-20 マイクロン テクノロジー， インク． 半導体装置
US10148316B2 (en) * 2016-04-26 2018-12-04 Intel Corporation Technologies for PCB and cable loss characterization and fixture de-embedding
CN107528583B (zh) * 2016-06-21 2022-04-19 马维尔亚洲私人有限公司 使用采样时间至数字转换器的倍频延迟锁定环路
US11114112B2 (en) * 2017-09-07 2021-09-07 Google Llc Low power, high bandwidth, low latency data bus
US10204668B1 (en) 2017-10-09 2019-02-12 Sandisk Technologies Llc On die delay range calibration
WO2020047672A1 (en) 2018-09-07 2020-03-12 Analogx Inc. Circuit and method to set delay between two periodic signals with unknown phase relationship
CN111865300B (zh) * 2020-07-08 2022-05-17 福州大学 应用于双环路延迟锁相环的可编程数字控制延迟线
CN114696822B (zh) * 2020-12-29 2024-06-07 宸芯科技股份有限公司 相位调谐装置
US11362667B1 (en) * 2021-09-24 2022-06-14 Cypress Semiconductor Corporation Reducing delay-lock loop delay fluctuation
US12316334B2 (en) * 2022-11-02 2025-05-27 Texas Instruments Incorporated Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection
CN116089937B (zh) * 2023-04-10 2023-06-20 灿芯半导体(苏州)有限公司 一种可抵御多种故障注入的全数字传感器

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US20010022524A1 (en) * 2000-03-16 2001-09-20 Kim Kyu-Hyoun Delay-locked loop circuit having master-slave structure
US20040093388A1 (en) * 2002-11-13 2004-05-13 Chandler James E. Test validation of an integrated device
CN1608342A (zh) * 2001-11-02 2005-04-20 摩托罗拉公司 级联的延迟锁定环路
JP2005142859A (ja) * 2003-11-06 2005-06-02 Nec Micro Systems Ltd Ｍａｓｔｅｒ／Ｓｌａｖｅ方式ディジタルＤＬＬおよびその制御方法
CN101547007A (zh) * 2008-03-28 2009-09-30 索尼株式会社 延迟锁相环电路和显示装置
US20120249200A1 (en) * 2011-04-01 2012-10-04 Yu Wing K Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments

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US6741522B1 (en) * 2001-11-27 2004-05-25 Lsi Logic Corporation Methods and structure for using a higher frequency clock to shorten a master delay line
US6958634B2 (en) * 2003-12-24 2005-10-25 Intel Corporation Programmable direct interpolating delay locked loop
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JP5023605B2 (ja) 2006-08-09 2012-09-12 富士通セミコンダクター株式会社 ディレイ調整回路およびその制御方法
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US20010022524A1 (en) * 2000-03-16 2001-09-20 Kim Kyu-Hyoun Delay-locked loop circuit having master-slave structure
CN1608342A (zh) * 2001-11-02 2005-04-20 摩托罗拉公司 级联的延迟锁定环路
US20040093388A1 (en) * 2002-11-13 2004-05-13 Chandler James E. Test validation of an integrated device
JP2005142859A (ja) * 2003-11-06 2005-06-02 Nec Micro Systems Ltd Ｍａｓｔｅｒ／Ｓｌａｖｅ方式ディジタルＤＬＬおよびその制御方法
CN101547007A (zh) * 2008-03-28 2009-09-30 索尼株式会社 延迟锁相环电路和显示装置
US20120249200A1 (en) * 2011-04-01 2012-10-04 Yu Wing K Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments

Also Published As

Publication number Publication date
KR20160114052A (ko) 2016-10-04
US9148157B2 (en) 2015-09-29
IN2014CH00427A (enExample) 2015-08-07
CN105874716A (zh) 2016-08-17
US20150214965A1 (en) 2015-07-30
WO2015116670A1 (en) 2015-08-06
KR101947580B1 (ko) 2019-02-14

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