IN2014CH00427A - - Google Patents

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Publication number
IN2014CH00427A
IN2014CH00427A IN427CH2014A IN2014CH00427A IN 2014CH00427 A IN2014CH00427 A IN 2014CH00427A IN 427CH2014 A IN427CH2014 A IN 427CH2014A IN 2014CH00427 A IN2014CH00427 A IN 2014CH00427A
Authority
IN
India
Prior art keywords
slave
master
phase difference
delay
delay line
Prior art date
Application number
Other languages
English (en)
Inventor
Bhavin Odedara
Deepak Pancholi
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US14/461,921 priority Critical patent/US9148157B2/en
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Priority to CN201580003481.4A priority patent/CN105874716B/zh
Priority to KR1020167017448A priority patent/KR101947580B1/ko
Priority to PCT/US2015/013273 priority patent/WO2015116670A1/en
Priority to IN427CH2014 priority patent/IN2014CH00427A/en
Publication of IN2014CH00427A publication Critical patent/IN2014CH00427A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
IN427CH2014 2014-01-30 2015-01-28 IN2014CH00427A (enExample)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US14/461,921 US9148157B2 (en) 2014-01-30 2014-08-18 Auto-phase synchronization in delay locked loops
CN201580003481.4A CN105874716B (zh) 2014-01-30 2015-01-28 延迟锁定环中的自动相位同步
KR1020167017448A KR101947580B1 (ko) 2014-01-30 2015-01-28 지연 동기 루프들에서의 자동 위상 동기화
PCT/US2015/013273 WO2015116670A1 (en) 2014-01-30 2015-01-28 Auto-phase synchronization in delay locked loops
IN427CH2014 IN2014CH00427A (enExample) 2014-01-30 2015-01-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN427CH2014 IN2014CH00427A (enExample) 2014-01-30 2015-01-28

Publications (1)

Publication Number Publication Date
IN2014CH00427A true IN2014CH00427A (enExample) 2015-08-07

Family

ID=53680069

Family Applications (1)

Application Number Title Priority Date Filing Date
IN427CH2014 IN2014CH00427A (enExample) 2014-01-30 2015-01-28

Country Status (5)

Country Link
US (1) US9148157B2 (enExample)
KR (1) KR101947580B1 (enExample)
CN (1) CN105874716B (enExample)
IN (1) IN2014CH00427A (enExample)
WO (1) WO2015116670A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015076711A (ja) * 2013-10-08 2015-04-20 マイクロン テクノロジー， インク． 半導体装置
US10148316B2 (en) * 2016-04-26 2018-12-04 Intel Corporation Technologies for PCB and cable loss characterization and fixture de-embedding
CN107528583B (zh) * 2016-06-21 2022-04-19 马维尔亚洲私人有限公司 使用采样时间至数字转换器的倍频延迟锁定环路
US11114112B2 (en) * 2017-09-07 2021-09-07 Google Llc Low power, high bandwidth, low latency data bus
US10204668B1 (en) 2017-10-09 2019-02-12 Sandisk Technologies Llc On die delay range calibration
WO2020047672A1 (en) * 2018-09-07 2020-03-12 Analogx Inc. Circuit and method to set delay between two periodic signals with unknown phase relationship
CN111865300B (zh) * 2020-07-08 2022-05-17 福州大学 应用于双环路延迟锁相环的可编程数字控制延迟线
CN114696822B (zh) * 2020-12-29 2024-06-07 宸芯科技股份有限公司 相位调谐装置
US11362667B1 (en) * 2021-09-24 2022-06-14 Cypress Semiconductor Corporation Reducing delay-lock loop delay fluctuation
US12316334B2 (en) * 2022-11-02 2025-05-27 Texas Instruments Incorporated Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection
CN116089937B (zh) * 2023-04-10 2023-06-20 灿芯半导体(苏州)有限公司 一种可抵御多种故障注入的全数字传感器

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KR100640568B1 (ko) 2000-03-16 2006-10-31 삼성전자주식회사 마스터-슬레이브 구조를 갖는 지연동기루프 회로
US6496048B1 (en) * 2000-07-20 2002-12-17 Silicon Graphics, Inc. System and method for accurate adjustment of discrete integrated circuit delay lines
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
US6741522B1 (en) * 2001-11-27 2004-05-25 Lsi Logic Corporation Methods and structure for using a higher frequency clock to shorten a master delay line
US20040093388A1 (en) * 2002-11-13 2004-05-13 Chandler James E. Test validation of an integrated device
JP3949643B2 (ja) * 2003-11-06 2007-07-25 Ｎｅｃエレクトロニクス株式会社 Ｍａｓｔｅｒ／Ｓｌａｖｅ方式ディジタルＤＬＬおよびその制御方法
US6958634B2 (en) * 2003-12-24 2005-10-25 Intel Corporation Programmable direct interpolating delay locked loop
JP4416580B2 (ja) 2004-06-28 2010-02-17 株式会社リコー 遅延制御装置
US7157948B2 (en) * 2004-09-10 2007-01-02 Lsi Logic Corporation Method and apparatus for calibrating a delay line
US7061224B2 (en) * 2004-09-24 2006-06-13 Intel Corporation Test circuit for delay lock loops
US7634039B2 (en) * 2005-02-04 2009-12-15 True Circuits, Inc. Delay-locked loop with dynamically biased charge pump
US7123103B1 (en) * 2005-03-31 2006-10-17 Conexant Systems, Inc. Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop
US7161402B1 (en) * 2005-05-13 2007-01-09 Sun Microsystems, Inc. Programmable delay locked loop
US20070096787A1 (en) * 2005-11-03 2007-05-03 United Memories, Inc. Method for improving the timing resolution of DLL controlled delay lines
JP5023605B2 (ja) 2006-08-09 2012-09-12 富士通セミコンダクター株式会社 ディレイ調整回路およびその制御方法
US7388795B1 (en) * 2006-12-28 2008-06-17 Intel Corporation Modular memory controller clocking architecture
US7795935B2 (en) 2007-09-29 2010-09-14 Intel Corporation Bias signal delivery
US7911873B1 (en) * 2007-12-31 2011-03-22 Synopsys, Inc. Digital delay locked loop implementation for precise control of timing signals
JP4569656B2 (ja) * 2008-03-28 2010-10-27 ソニー株式会社 遅延同期ループ回路および表示装置
US7701246B1 (en) * 2008-07-17 2010-04-20 Actel Corporation Programmable delay line compensated for process, voltage, and temperature
US8564345B2 (en) * 2011-04-01 2013-10-22 Intel Corporation Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments
US8779816B2 (en) * 2012-06-20 2014-07-15 Conexant Systems, Inc. Low area all digital delay-locked loop insensitive to reference clock duty cycle and jitter
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US9754656B2 (en) * 2013-06-28 2017-09-05 Intel Corporation Master/slave control voltage buffering
US8890591B1 (en) * 2013-12-24 2014-11-18 Liming Xiu Circuit and method of using time-average-frequency direct period syntheszier for improving crystal-less frequency generator frequency stability

Also Published As

Publication number Publication date
CN105874716B (zh) 2019-04-09
US20150214965A1 (en) 2015-07-30
KR20160114052A (ko) 2016-10-04
CN105874716A (zh) 2016-08-17
US9148157B2 (en) 2015-09-29
WO2015116670A1 (en) 2015-08-06
KR101947580B1 (ko) 2019-02-14

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