MX369350B - Bucle digital bloqueado por fase con una fase desacoplada y compensacion de frecuencia. - Google Patents

Bucle digital bloqueado por fase con una fase desacoplada y compensacion de frecuencia.

Info

Publication number
MX369350B
MX369350B MX2017007101A MX2017007101A MX369350B MX 369350 B MX369350 B MX 369350B MX 2017007101 A MX2017007101 A MX 2017007101A MX 2017007101 A MX2017007101 A MX 2017007101A MX 369350 B MX369350 B MX 369350B
Authority
MX
Mexico
Prior art keywords
phase
locked loop
frequency compensation
digital phase
component
Prior art date
Application number
MX2017007101A
Other languages
English (en)
Other versions
MX2017007101A (es
Inventor
Landheer Ronald
Original Assignee
Cooper Technologies Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cooper Technologies Co filed Critical Cooper Technologies Co
Publication of MX2017007101A publication Critical patent/MX2017007101A/es
Publication of MX369350B publication Critical patent/MX369350B/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Un dispositivo de circuito integrado que implementa un bucle digital bloqueado por fase incluye un componente de periodo de medida, un componente de promedio, un componente de generador y un componente de compensación. En la implementación de bucle bloqueado por fase digital, la compensación de fase y la compensación de frecuencia están separadas una de la otra.
MX2017007101A 2016-06-14 2017-06-05 Bucle digital bloqueado por fase con una fase desacoplada y compensacion de frecuencia. MX369350B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/181,857 US9654117B1 (en) 2016-06-14 2016-06-14 Digital phase-locked loop having de-coupled phase and frequency compensation

Publications (2)

Publication Number Publication Date
MX2017007101A MX2017007101A (es) 2018-08-28
MX369350B true MX369350B (es) 2019-11-06

Family

ID=58670460

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2017007101A MX369350B (es) 2016-06-14 2017-06-05 Bucle digital bloqueado por fase con una fase desacoplada y compensacion de frecuencia.

Country Status (2)

Country Link
US (1) US9654117B1 (es)
MX (1) MX369350B (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110100389B (zh) * 2016-12-19 2021-03-02 瑞典爱立信有限公司 用于无线设备收发器的参考晶体振荡器切换的系统和方法
KR20230039135A (ko) * 2021-09-13 2023-03-21 삼성전자주식회사 패턴 생성기 및 이를 포함하는 내장 자체 시험 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666330A (en) 1994-07-21 1997-09-09 Telecom Solutions, Inc. Disciplined time scale generator for primary reference clocks
US7248124B2 (en) 2004-03-22 2007-07-24 Mobius Microsystems, Inc. Frequency calibration for a monolithic clock generator and timing/frequency reference
US7567640B2 (en) * 2006-05-02 2009-07-28 Faraday Technology Corp. Phase offset tracking method for tracking a phase offset and device thereof
US8321489B2 (en) * 2006-09-15 2012-11-27 National Semiconductor Corporation Software reconfigurable digital phase lock loop architecture
JP2009109338A (ja) 2007-10-30 2009-05-21 Seiko Epson Corp 時刻情報管理システム、電子機器、時刻情報管理方法及びプログラム
US9749169B2 (en) * 2009-01-10 2017-08-29 John W. Bogdan Data recovery with inverse transformation
US9722768B2 (en) * 2013-11-15 2017-08-01 National Institute Of Advanced Industrial Science And Technology Received signal processing device, communication system, and received signal processing method
US9397673B2 (en) * 2014-04-23 2016-07-19 Telefonaktiebolaget L M Ericsson (Publ) Oscillator crosstalk compensation
WO2016153653A1 (en) * 2015-03-23 2016-09-29 Microsemi SoC Corporation Hybrid phase locked loop having wide locking range
US9667237B2 (en) * 2015-03-31 2017-05-30 Microsemi Semiconductor Ulc Hardware delay compensation in digital phase locked loop

Also Published As

Publication number Publication date
US9654117B1 (en) 2017-05-16
MX2017007101A (es) 2018-08-28

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