CN105870117A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105870117A
CN105870117A CN201610053787.7A CN201610053787A CN105870117A CN 105870117 A CN105870117 A CN 105870117A CN 201610053787 A CN201610053787 A CN 201610053787A CN 105870117 A CN105870117 A CN 105870117A
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wiring
semiconductor device
external connection
connection terminals
transistor
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CN105870117B (zh
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桥谷雅幸
长谷川尚
高品隆之
增子裕之
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Seiko Instruments Inc
Ablic Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract

本发明提供一种半导体装置,该半导体装置在第1外部连接端子与被连接于VSS的第2外部连接端子之间具有作为ESD保护元件的截止晶体管和输出元件,其中,密封环布线利用连接布线而与从第2外部连接端子至截止晶体管的源极的第1内部布线并列地连接,该部分的寄生电阻比连接截止晶体管的源极与输出元件的源极的第2内部布线的寄生电阻小。

Description

半导体装置
技术领域
本发明涉及半导体装置,为了保护半导体集成电路(以下,称作IC)免受由于静电放电(Electro-Static Discharge;以下,称作ESD)产生的静电脉冲的破坏,该半导体装置具有形成在外部连接端子与内部电路区域、或外部连接端子与输出元件之间的ESD保护元件。
背景技术
以往,在以IC为代表的半导体装置中具备ESD保护元件,关于该ESD保护元件,已知所谓的截止晶体管,关于该截止晶体管,将N型MOS晶体管的栅极电位恒定为接地(以下,称作VSS),在稳定状态下处于截止状态。
作为ESD对策,为了防止内部电路元件或以驱动器(drive)为代表的输出元件的ESD破坏,关键在于将尽量多的静电脉冲取入截止晶体管并向VSS放出。因此,为了使由于ESD的静电脉冲而发生的、向应当进行保护而免受ESD影响的内部电路元件和输出元件流动的电流流至VSS,关键在于从IC的VSS方面降低截止晶体管的寄生电阻。
可是,例如在IC尺寸变大的情况下,从VSS到截止晶体管的距离变远,由此,存在下述情况:截止晶体管的源极的寄生电阻的影响突显化,截止晶体管无法发挥充分的能力,而使本来应取入的静电脉冲传导至内部电路元件或输出元件,造成因ESD引起的IC破坏。
作为对该不良情况的改善方案的示例,如下述专利文献中那样,还提出了一种器件结构,该器件结构的特征在于,通过使从外部连接端子到ESD保护元件的寄生电阻、以及从ESD保护元件到内部电路元件的寄生电阻具有寄生电阻的大小关系,从而将尽量多的静电脉冲取入到ESD保护元件中。
以往,特别着眼于高驱动能力和高附加价值而开发了以电压检测器或电压调节器为代表的电源管理IC。在对高驱动能力的研究中,例如通过将输出元件配置在VSS附近,从而降低了输出元件的寄生电阻。在对高附加价值的研究中,例如通过利用以往的CMOS工艺构成内部电路,从而附加了原始的功能。
可是,在所述的高驱动能力化中,输出元件的寄生电阻降低得比截止晶体管低,其结果是,担心无法利用截止晶体管充分取入静电脉冲而使得静电脉冲传导至输出元件,导致IC破坏。
另外,在后述的高附加价值中,由于IC尺寸变大,因而外部连接端子远离IC的VSS,由此截止晶体管的源极的寄生电阻突显化,其结果是,担心无法利用截止晶体管充分取入静电脉冲而使得静电脉冲传导至内部电路元件,导致IC破坏。
专利文献1:日本特开2009-49331号公报
发明内容
因此,在本发明中,课题在于提供一种半导体装置,其具有降低了源极的寄生电阻的截止晶体管。
本发明为了解决上述问题而采用以下手段。即,在具有截止晶体管的以IC为代表的半导体装置中,其特征在于,为了降低截止晶体管的源极的寄生电阻,而将与截止晶体管的源极连接的电位为VSS的内部布线与配置在IC外周的密封环布线并列地连接。
发明效果
根据本发明,在具有截止晶体管的半导体装置中,通过使截止晶体管的源极的寄生电阻降低,能够使截止晶体管快速地工作,能够抑制由于ESD产生的静电脉冲传导至输出元件或内部电路元件,能够改善半导体装置对于ESD的耐受性。
附图说明
图1是表示本发明的实施例的半导体装置的外部连接端子、ESD保护元件以及输出元件的示意性的电路图。
图2是对本发明的特征进行说明的示意性的布置图。
图3是能够实施本发明的半导体装置的示例。
标号说明
1:第1外部连接端子;
2:第2外部连接端子;
3:截止晶体管的源极寄生电阻;
4:输出元件的源极寄生电阻;
5:截止晶体管;
6:输出元件;
7:密封环布线;
8:内部布线;
9:连接布线;
10:通孔;
20:半导体装置。
具体实施方式
使用附图对用于实施本发明的方式进行说明。
图1是表示本发明的实施例的半导体装置的外部连接端子、ESD保护元件以及输出元件的示意性的电路图。第1外部连接端子1例如是用于输出的端子。第2外部连接端子2是较低侧的电源电压,通常与接地电位VSS连接。连接在第1外部连接端子1与第2外部连接端子2之间的元件之一是作为ESD保护元件的截止晶体管5。此外,输出元件6与截止晶体管5并列地连接。即,输出元件6的输出与第1外部连接端子1连接。
截止晶体管5的源极的寄生电阻是从截止晶体管5的源极至第2外部连接端子2的第1内部布线中寄生含有的电阻,用图中的标号3来表示(以下,称作截止晶体管的源极寄生电阻3),输出元件6的源极的寄生电阻是从输出元件6的源极至截止晶体管5的源极的第2内部布线中寄生含有的电阻,用图中的标号4来表示。在以下内容中,作为输出元件的源极寄生电阻4。
本发明的特征在于,使截止晶体管的源极寄生电阻3比输出元件的源极寄生电阻4低,使用图2对用于进一步说明此特征的实施例进行说明。
图2是示出IC布置的一部分的图,示出了布线的形状。描画出了设置于IC的外周的密封环布线7和内部布线8。从第2外部连接端子2到截止晶体管5设置内部布线8,而且,利用连接布线9将内部布线8与密封环布线7电连接,使内部布线8与密封环布线7并列,由此能够降低截止晶体管的源极寄生电阻3。
该情况下的密封环布线7与第2外部连接端子连接,该第2外部连接端子被连接于比第1外部连接端子低的电位,电位例如是接地电位VSS。
另外,密封环布线7的布线方法一般是被设置在上述的IC的外周。如上所述地与第2外部连接端子连接,例如作为接地电位VSS。能够配置成以不在中途中断的方式环绕整个IC的外周。另外,即便是存在1处中断而不连续的部分,但也能够大致环绕地配置。这是因为,优选密封环布线7整体成为相同电位。
图3是能够实施本发明的半导体装置的示例。如图3所示,一般,密封环布线7、第2外部连接端子2以及截止晶体管5多是沿着芯片形状的IC即半导体装置20的外周进行配置,因此,将连接第2外部连接端子2和截止晶体管5的内部布线8与密封环布线7并列地进行连接并不困难。
另一方面,使从输出元件6的源极至截止晶体管5的源极的布线仅为一层布线,而且使宽度变窄,由此能够相对增大寄生电阻。此外,将输出元件6沿着从第2外部连接端子2延伸的内部布线8配置得比截止晶体管5远,由此,容易相对增大寄生电阻。
此外,在采用多层布线的情况下,图2中的内部布线8也可以形成为最下层布线和最上层布线的层叠结构。该情况下,也可以进一步在最下层布线与最上层布线之间包含多个中间层的布线,可以经由通孔10(也称作过孔)电连接。在层叠结构中,最上层布线的宽度与最下层布线的宽度可以相同,也可以不同。由此,能够使截止晶体管的源极寄生电阻3比输出元件的源极寄生电阻4低。
此外,在所述的由多个布线构成的层叠结构中,具有用于将多个布线电连接的通孔10,通孔10可以连续地配置,也可以断续地、分散地配置。
另外,内部布线8利用连接布线9与密封环布线7电连接,关于连接布线9,无论是最下层布线、最上层布线、或是其他中间层的布线,都能够进行电连接。此外,在密封环布线7与内部布线8的连接中,可以如图2那样断续地并列配置多个连接布线9,也可以连续地呈面状配置一个连接布线9。
另外,到此为止,作为比截止晶体管5更位于IC的内部的元件,以输出元件6为例进行了说明,但很明显,输出元件6即使是一般的内部电路,也能够同样地实施本发明。

Claims (9)

1.一种半导体装置,其特征在于,
所述半导体装置由下述部分构成:
第1外部连接端子;
第2外部连接端子,所述第2外部连接端子被连接于比所述第1外部连接端子低的电位;
作为ESD保护元件的截止晶体管和输出元件,所述截止晶体管和输出元件并列地配置在所述第1外部连接端子与所述第2外部连接端子之间;以及
密封环布线,所述密封环布线与所述第2外部连接端子连接,
通过利用连接布线将连接所述第2外部连接端子和所述截止晶体管的源极的第1内部布线与所述密封环布线并列地连接,使得所述第1内部布线的寄生电阻即截止晶体管的源极寄生电阻比连接所述截止晶体管的源极和所述输出元件的源极的第2内部布线的寄生电阻即输出元件的源极寄生电阻小。
2.根据权利要求1所述的半导体装置,其特征在于,
所述第1内部布线是包含最下层布线和最上层布线的层叠结构。
3.根据权利要求2所述的半导体装置,其特征在于,
所述第1内部布线是在最下层布线和最上层布线之间包含中间布线层的层叠结构。
4.根据权利要求2或3所述的半导体装置,其特征在于,
所述层叠结构中包含的布线经由通孔电连接。
5.根据权利要求2所述的半导体装置,其特征在于,
所述连接布线由所述最下层布线或所述最上层布线构成。
6.根据权利要求3所述的半导体装置,其特征在于,
所述连接布线由所述最下层布线、所述最上层布线、或所述中间布线层构成。
7.根据权利要求6所述的半导体装置,其特征在于,
连接所述密封环布线与所述内部布线的所述连接布线断续地并列配置有多个、或者连续地呈面状配置有一个。
8.根据权利要求1所述的半导体装置,其特征在于,
所述密封环布线被设置在IC外周,并且连续地环绕。
9.根据权利要求1所述的半导体装置,其特征在于,
所述密封环布线被设置在IC外周,并且除了中断而不连续的1处之外环绕。
CN201610053787.7A 2015-02-05 2016-01-27 半导体装置 Active CN105870117B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2015021374 2015-02-05
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