CN105830203A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN105830203A CN105830203A CN201480069435.XA CN201480069435A CN105830203A CN 105830203 A CN105830203 A CN 105830203A CN 201480069435 A CN201480069435 A CN 201480069435A CN 105830203 A CN105830203 A CN 105830203A
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Abstract
本发明的半导体装置(1)具备:半导体层(2);电极层(3),其被配置于半导体层(2)上;裂缝起点层(10),其被配置于半导体层(2)的上侧;锡焊层(4),其与电极层(3)以及裂缝起点层(10)接触。锡焊层(4)与裂缝起点层(10)的接合力小于锡焊层(4)与电极层(3)的接合力。
Description
技术领域
本说明书所公开的技术涉及一种具备锡焊层的半导体装置。
背景技术
在一般的半导体装置中,有时会因在使用中反复实施温度的上升与下降的温度循环而向半导体装置的内部施加有应力,从而产生裂缝(裂纹)。在专利文献1(日本国特开2011-023631号公报)中,公开了一种用于提高相对于半导体装置中所产生的裂缝的耐性的技术。专利文献1所公开的结构具备半导体元件、和与半导体元件对置配置的电极层。此外,在该结构中,在半导体元件的与电极层对置一侧的面上具备中间接合层以及锡焊接合层。此外,在半导体元件上、以及至少中间接合层与锡焊接合层之间的外周面区域内,被覆形成有半导体元件保护树脂。
发明内容
发明所要解决的课题
在专利文献1的技术中,通过形成半导体元件保护树脂,从而提高了半导体装置的耐裂缝性。然而,在专利文献1的技术中,也具有在因温度循环而向半导体装置的内部施加有应力时产生裂缝的可能性。此外,在产生了裂缝时,该裂缝有可能会向电极层扩展。因此,本说明书的目的在于,提供一种裂缝难以进入电极层的半导体装置。
用于解决课题的方法
本说明书所公开的半导体装置具备:半导体层;电极层,其被配置于所述半导体层上;裂缝起点层,其被配置于所述半导体层的上侧;锡焊层,其与所述电极层以及所述裂缝起点层接触。所述锡焊层与所述裂缝起点层的接合力小于所述锡焊层与所述电极层的接合力。
根据这种结构,在因温度循环而向半导体装置的内部施加有应力时,裂缝起点层将成为裂缝的起点,从而使裂缝先于电极层而进入锡焊层。由于当不存在裂缝起点层时,将没有产生裂缝的契机,因此裂缝有可能不进入锡焊层而进入电极层,但是根据上述结构,裂缝以裂缝起点层为契机而进入锡焊层。由此,能够使裂缝难以进入电极层。
在上述半导体装置中,也可以采用如下方式,即,所述裂缝起点层被配置于所述电极层上,所述裂缝起点层的厚度小于所述裂缝起点层的宽度。
此外,可以采用如下方式,即,所述电极层通过如下材料而被形成,所述材料与所述裂缝起点层相比而易于与所述锡焊层形成合金。
此外,也可以采用如下方式,即,所述裂缝起点层通过铝、硅铝合金(aluminumsilicon)、碳、或者聚酰亚胺树脂中的任意一种而被形成。
附图说明
图1为实施方式所涉及的半导体装置的俯视图。
图2为将半导体装置的主要部分放大表示的剖视图(图1的Ⅱ-Ⅱ剖视图)。
图3为将另一实施方式所涉及的半导体装置的主要部分放大表示的剖视图。
图4为将又一实施方式所涉及的半导体装置的主要部分放大表示的剖视图。
图5为又一实施方式所涉及的半导体装置的俯视图。
图6为又一实施方式所涉及的半导体装置的俯视图。
图7为又一实施方式所涉及的半导体装置的俯视图。
图8为又一实施方式所涉及的半导体装置的俯视图。
图9为又一实施方式所涉及的半导体装置的俯视图。
具体实施方式
以下,参照附图对实施方式进行说明。如图1及图2所示,实施方式所涉及的半导体装置1具备:半导体层2;电极层3,其被配置于半导体层2上;裂缝起点层10,其被配置于半导体层2的上侧;锡焊层4,其与电极层3以及裂缝起点层10接触。各层在纵向(z方向)上层叠。另外,虽然裂缝起点层10因被锡焊层4覆盖而在图1的俯视图中原本无法观察到,但为了进行说明而在图1中以实线来表示裂缝起点层10。
半导体层2为,通过向例如硅(Si)或碳化硅(SiC)等半导体基板中注入杂质从而形成了n型或p型的各个区域的层。作为该半导体层2,能够使用例如二极管、晶体管、或者可控硅等。更具体而言,能够使用MOSFET(MetalOxideSemiconductorFieldEffectTransistor:金属氧化物场效应晶体管)或IGBT(InsulatedGateBipolarTransistor:绝缘栅双极性晶体管)等。
电极层3具备被配置在半导体层2的表面上的第一层31、和被配置在第一层31的表面上的第二层32。第一层31与半导体层2接触,第二层32与锡焊层4接触。锡焊层4与电极层3(第二层32)的接合力大于锡焊层4与裂缝起点层10的接合力。关于电极层3(第二层32),其为了增大与锡焊层4的接合力,而采用了与裂缝起点层10相比更容易与锡焊层4形成合金的结构。具体而言,作为与锡焊层4接合的电极层3的表面侧的第二层32的材料,而使用与裂缝起点层10的材料相比更容易与锡焊层4的材料形成合金的材料。更具体而言,作为第二层32的材料,而能够使用例如镍(Ni)或铜(Cu)。
在电极层3的第一层31的端部与第二层32的端部之间配置有保护层6。作为保护层6的材料,而能够使用例如聚酰亚胺树脂(PI)等。
锡焊层4被配置在电极层3的表面上。锡焊层4相对于电极层3而接合被接合部件5。锡焊层4被填充于电极层3与被接合部件5之间。虽然被接合部件5未被特别限定,但该被接合部件5为例如铜(Cu)等金属制造的引线框架。被接合部件5经由锡焊层4而与电极层3通电。作为锡焊层4的材料,能够使用用于实施软钎焊的公知的材料,例如能够使用作为主要成分而含有锡(Sn)、银(Ag)、铜(Cu)的合金。锡焊层4的热膨胀系数与被接合部件5的热膨胀系数不同。此外,锡焊层4具备位于半导体层2与被接合部件5之间的第一区域41、和位于与第一区域41相比靠外侧的第二区域42。第一区域41被配置于被接合部件5的下方。第二区域42从被接合部件5向横向(x方向)鼓出,并且被配置于保护层6的上方。在第二区域42的内部被配置有裂缝起点层10。
裂缝起点层10被配置于电极层3之上,且被配置于电极层3与锡焊层4的边界部分处。裂缝起点层10被配置于电极层3的第二层32之上。裂缝起点层10被配置于与锡焊层4的端部接触的位置处。裂缝起点层10的整体被锡焊层4所覆盖,从而被埋藏在锡焊层4的内部。在俯视观察锡焊层4时,锡焊层4包围了裂缝起点层10,并在裂缝起点层10的周围与电极层3接合。裂缝起点层10沿着电极层3的表面延伸。此外,裂缝起点层10具备第一部分101和第二部分102,所述第一部分101在沿着半导体层2的表面的方向(横向:x方向)上延伸,所述第二部分102相对于第一部分101而倾斜,并从第一部分101朝向半导体层2侧延伸。第一部分101位于外侧(锡焊层4的端部侧),第二部分102位于与第一部分101相比靠内侧处。锡焊层4与裂缝起点层10的接触面在第一部分101与第二部分102的边界部分处发生弯曲。此外,在俯视观察时,沿着锡焊层4的端部配置有多个裂缝起点层10。在各个裂缝起点层10的周围填充有锡焊层4。此外,裂缝起点层10以在俯视观察时包围被接合部件5的方式被配置于被接合部件5的周围。
锡焊层4与裂缝起点层10的接合力小于锡焊层4与电极层3的接合力。关于裂缝起点层10,其为了减小与锡焊层4的接合力,而采用了难以与锡焊层4形成合金的结构。具体而言,作为裂缝起点层10的材料,而使用难以与锡焊层4的材料形成合金的材料(作为裂缝起点层10的材料,而使用与锡焊层4的材料的湿润性较差的材料)。更具体而言,作为裂缝起点层10的材料,能够使用例如铝(Al)、硅铝合金(AlSi)、碳(C)、聚酰亚胺树脂(PI)等。由于锡焊层4与裂缝起点层10的接合力小于锡焊层4与电极层3的接合力,因此以裂缝起点层10为起点,而使裂缝容易进入锡焊层4。从使裂缝在横向(x方向)上进入锡焊层4的观点来看,优选为,裂缝起点层10的厚度t小于裂缝起点层10的宽度w。裂缝起点层10的厚度t为纵向(z方向)上的裂缝起点层10的端部间的距离,宽度w为横向(x方向)上的裂缝起点层10的端部间的距离。
根据具备上述结构的半导体装置1,通过向半导体层2施加电压而流动有电流。当有电流在半导体层2中流动时,将产生热量,从而使半导体装置1的温度上升。此外,当停止电压的施加时,半导体装置1的温度将降低。此时,由于温度的上升与降低的循环,而向半导体装置1的内部施加有应力。根据上述的半导体装置1,在向内部施加有应力时,裂缝起点层10成为裂缝的起点,并使裂缝进入锡焊层4。即,由于当不存在裂缝起点层10时将没有产生裂缝的契机,因此裂缝有可能不进入锡焊层4而进入电极层3。当裂缝进入电极层3时,将无法使用半导体装置。然而,根据上述的半导体装置1,由于锡焊层4与裂缝起点层10的接合力小于锡焊层4与电极层3的接合力,因此将以裂缝起点层10为契机,而使裂缝先于电极层3而进入锡焊层4。由此,能够使裂缝难以进入电极层3。此外,当裂缝进入锡焊层4时,由于锡焊层4中的电阻将变大而使温度上升与通常相比变高,因此能够通过对该温度上升进行检测并发出警告从而避免半导体装置1的劣化。
此外,由于裂缝起点层10的厚度t小于裂缝起点层10的宽度w,因此能够将以裂缝起点层10为起点而产生的裂缝向宽度方向(x方向)引导。由此,能够对裂缝沿着纵向(z方向)延伸的情况进行抑制,从而能够使裂缝难以从锡焊层4进入电极层3或半导体层2。此外,由于裂缝起点层10与锡焊层4的端部接触,因此能够使裂缝进入锡焊层4的端部,从而能够防止在锡焊层4的中央部产生裂缝的情况。
虽然上文对一个实施方式进行了说明,但具体的方式并不限定于上述实施方式。例如,虽然在实施方式中,在电极层3的第二层32之上形成有裂缝起点层10,但并不限定于该结构,也可以在第二层32之下形成裂缝起点层10。在其他的实施方式中,如图3所示,裂缝起点层10被配置于第一层31之上,第二层32被配置于裂缝起点层10之上。在第二层32上,于形成有裂缝起点层10的位置处形成有开口部35,裂缝起点层10从开口部35露出。锡焊层4覆盖了开口部35,并与露出的裂缝起点层10接触。该结构的裂缝起点层10也具有作为图1所示的半导体装置1中的保护层6的功能。另外,在图3中,对与图2同样结构标注相同的符号并省略说明。
此外,虽然在上述实施方式中,电极层3的第二层32的端部被配置于保护层6之上,但并不限定于该结构,如图4所示,也可以不将第二层32的端部配置于保护层6之上。另外,在图4中,对与图2相同的结构标注相同的符号并省略说明。
此外,俯视观察时的裂缝起点层10的配置位置并未被特别限定。例如,如图5所示,可以使各个裂缝起点层10以沿着锡焊层4的端部呈直线状延伸的方式被配置。各个裂缝起点层10以分别与被接合部件5的各个边整体对置的方式被配置。此外,如图6所示,也可以以与被接合部件5的一条边对置的方式而配置有多个裂缝起点层10。多个裂缝起点层10呈直线状延伸,并以在长度方向上互相隔开间隔的方式而配置。此外,如图7所示,多个裂缝起点层10也可以以并排为两列的方式而配置。一列裂缝起点层10被配置在于z方向上与被接合部件5重叠的位置处,另一列裂缝起点层10被配置在于z方向上与被接合部件5不重叠的位置处。此外,如图8所示,也可以以与被接合部件5的两边(短边)对置的方式而配置有多个裂缝起点层10。在与被接合部件5的另外两边(长边)对置的位置处,不配置裂缝起点层10。此外,如图9所示,也可以采用如下方式,即,使沿着被接合部件5的各个边排列为两列的多个裂缝起点层10被配置于互相偏离的位置处。例如,通过使沿着被接合部件5的y方向上的一条边而排列为两列的多个裂缝起点层10在y方向上互相偏离,从而以在x方向上不重叠的方式而配置。即使根据图5~图9所示的各个结构,也使裂缝以起点层10为契机而进入到锡焊层4中。另外,在图5~图9中,对与图1相同的结构标注相同的符号并省略说明。
虽然以上对本发明的具体例进行了详细说明,但这些内容只不过是例示,并非对权利要求进行限定。在权利要求所记载的技术中,包括对以上所例示的具体例进行各种变形、变更的内容。本说明书或附图中所说明的技术要素为,通过单独或各种组合而发挥技术上的有用性的要素,并不限定于申请时权利要求所记载的组合。此外,本说明书或附图中所例示的技术能够同时实现多个目的,实现其中的一个目的这本身就具有技术上的有用性。
符号说明
1、半导体装置;
2、半导体层;
3、电极层;
4、锡焊层;
5、被接合部件;
6、保护层;
10、裂缝起点层;
31、第一层;
32、第二层;
35、开口部;
41、第一区域;
42、第二区域;
101、第一部分;
102、第二部分。
Claims (4)
1.一种半导体装置,具备:
半导体层;
电极层,其被配置于所述半导体层上;
裂缝起点层,其被配置于所述半导体层的上侧;
锡焊层,其与所述电极层以及所述裂缝起点层接触,
所述锡焊层与所述裂缝起点层的接合力小于所述锡焊层与所述电极层的接合力。
2.如权利要求1所述的半导体装置,其中,
所述裂缝起点层被配置于所述电极层上,
所述裂缝起点层的厚度小于所述裂缝起点层的宽度。
3.如权利要求1或2所述的半导体装置,其中,
所述电极层通过如下材料而被形成,所述材料与所述裂缝起点层相比而易于与所述锡焊层形成合金。
4.如权利要求1至3中的任意一项所述的半导体装置,其中,
所述裂缝起点层通过铝、硅铝合金、碳、或者聚酰亚胺树脂中的任意一种而被形成。
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PCT/JP2014/070519 WO2015093090A1 (ja) | 2013-12-20 | 2014-08-04 | 半導体装置 |
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US20080157359A1 (en) * | 2006-12-27 | 2008-07-03 | Sharp Kabushiki Kaisha | Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component |
JP2010212294A (ja) * | 2009-03-06 | 2010-09-24 | Toyota Motor Corp | 半導体装置 |
JP2011023631A (ja) * | 2009-07-17 | 2011-02-03 | Panasonic Corp | 接合構造体 |
CN102903690A (zh) * | 2011-07-29 | 2013-01-30 | 台湾积体电路制造股份有限公司 | 在半导体器件和封装组件中的凸块结构 |
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US20080157359A1 (en) * | 2006-12-27 | 2008-07-03 | Sharp Kabushiki Kaisha | Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component |
JP2010212294A (ja) * | 2009-03-06 | 2010-09-24 | Toyota Motor Corp | 半導体装置 |
JP2011023631A (ja) * | 2009-07-17 | 2011-02-03 | Panasonic Corp | 接合構造体 |
CN102903690A (zh) * | 2011-07-29 | 2013-01-30 | 台湾积体电路制造股份有限公司 | 在半导体器件和封装组件中的凸块结构 |
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