CN105826276B - 模块及其制造方法 - Google Patents

模块及其制造方法 Download PDF

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Publication number
CN105826276B
CN105826276B CN201610051869.8A CN201610051869A CN105826276B CN 105826276 B CN105826276 B CN 105826276B CN 201610051869 A CN201610051869 A CN 201610051869A CN 105826276 B CN105826276 B CN 105826276B
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mentioned
substrate
semiconductor module
electrode
recess portion
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CN105826276A (zh
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铃宗一郎
泷智仁
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Sanmei Electric Co Ltd
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Sanmei Electric Co Ltd
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Abstract

本发明提供能够确保刚性并增大实装面积率的模块。本模块具有：具有多个电极的第一基板；粘接于上述第一基板的具有多个电极的第一元件；层叠在上述第一基板上的具备凹部的第二基板；以及粘接于上述凹部的具有多个电极的第二元件，在上述第一元件的一端侧，将上述第一元件的电极与上述第一基板的电极电连接，在与上述一端侧对向的另一端侧，将上述第一元件的电极与上述第二元件的电极经由设置在上述凹部的贯通孔进行电连接。

Description

模块及其制造方法
技术领域
本发明涉及模块及其制造方法。
背景技术
以往公知有在基板上实装半导体元件等的模块。在这样的模块中，例如在由基板的底板和侧壁形成的斗状的凹部上层叠两个半导体元件并在凹部上设置盖板而形成空心构造。
这里，如果将在基板上实装的半导体元件等的面积相对于基板面积的比例定义为实装面积率，则为了不改变半导体元件的尺寸而在上述构造中增大实装面积率，需要使基板的侧壁变薄来减小基板面积。但是，减薄侧壁可能会降低作为模块的刚性而不理想。另外，原本在上述构造中，在对半导体元件进行引线键合时，存在毛细管状键合头与侧壁干涉的问题，因此减小基板面积是有限度的。
另一方面，有时是在平板状的基板上以在层叠的半导体元件周围环绕的方式安装使凹状构造上下翻转的形状的盖罩而实现空心构造。此时需要有安装盖罩的余量，因此很难减小基板面积来增大实装面积率。
现有技术文献
专利文献
专利文献1：日本特开2005－101192号公报
发明内容
发明所要解决的课题
本发明针对上述课题，提供一种能够确保刚性并增大实装面积率的模块。
用于解决课题的方法
本模块(1)的要点在于，具有：具有多个电极(13)的第一基板(10)；粘接于上述第一基板(10)的具有多个电极(21、22)的第一元件(20)；层叠在上述第一基板(10)上的具备凹部的第二基板(50)；粘接于上述凹部的具有多个电极(61)的第二元件(60)，在上述第一元件(20)的一端侧将上述第一元件(20)的电极(21)与上述第一基板(10)的电极(13)电连接，在与上述一端侧对向的另一端侧将上述第一元件(20)的电极(22)与上述第二元件(60)的电极(61)经由设置于上述凹部的贯通孔(53)进行电连接。
另外，上述括弧内的参照符号是为了容易理解而附加的，仅为一种例示而不限于图示形态。
发明的效果
根据公开的技术，能够提供一种模块，其能够确保刚性并增大实装面积率。
附图说明
图1是例示第一实施方式的半导体模块的图。
图2是例示第一实施方式的半导体模块的制造工序的图(其1)。
图3是例示第一实施方式的半导体模块的制造工序的图(其2)。
图4是例示第一实施方式的半导体模块的制造工序的图(其3)。
图5是例示第一实施方式的半导体模块的制造工序的图(其4)。
图6是例示第一实施方式的半导体模块的制造工序的图(其5)。
图7是例示第一实施方式的半导体模块的制造工序的图(其6)。
图8是例示第一实施方式的半导体模块的制造工序的图(其7)。
图9是例示第一实施方式的变形例1的半导体模块的剖视图。
图10是例示第一实施方式的变形例1的半导体模块的制造工序的图。
图11是对第一实施方式的变形例1的半导体模块的效果进行说明的图。
图12是例示第一实施方式的变形例2的半导体模块的剖视图。
图13是例示第一实施方式的变形例1的半导体模块的制造工序的图(其1)。
图14是例示第一实施方式的变形例1的半导体模块的制造工序的图(其2)。
图15是例示第一实施方式的变形例3的半导体模块的剖视图。
图16是例示第一实施方式的变形例4的半导体模块的剖视图。
图中：
1、2、3、4、5—半导体模块；10、50、100—基板；11、51、101—底板；12、52、102—侧壁；13、21、22、61、62、111—电极；20、60、110—半导体元件；30、70、120—金属线；35—基板支撑部件；40—填充树脂；53、54、81、103—贯通孔；55—保护层隔板；56—保护层隔垫；80—盖罩基板；90—粘接树脂；130—电阻；140—电容
具体实施方式
以下参照附图对本发明的实施方式进行说明。在各图中对同一结构部分标记同一符号而有时省略重复说明。
另外，在以下各实施方式中，作为本发明的模块的一个例子使用半导体模块进行说明，但是本发明的模块的也可以没有半导体元件。
〈第一实施方式〉
[第一实施方式的半导体模块的构造]
首先，对第一实施方式的半导体模块的构造进行说明。图1是例示第一实施方式的半导体模块的图。另外，图1(b)是俯视图、图1(a)是沿图1(b)的A－A线的剖视图。但是，在图1(b)中省略了填充树脂40及盖罩基板80的图示。
如图1所示，半导体模块1大致具有基板10、半导体元件20、金属线30、填充树脂40、基板50、半导体元件60、金属线70、盖罩基板80。
另外，在本实施方式中，为了方便而将半导体模块1的盖罩基板80侧设定为上侧或一方侧，将基板10侧设定为下侧或另一方侧。另外，将各部位的盖罩基板80侧的面设定为上表面或一侧的表面，将基板10侧的面设定为下表面或另一侧的表面。但是，半导体模块1能够在上下颠倒的状态下使用，或者能够以任意的角度进行配置。另外，俯视是指从基板10的上表面的法线方向观察对象物，平面形状是指从基板10的上表面的法线方向观察对象物的形状。
半导体模块1是将实装有半导体元件60的基板50层叠(贴合)在实装有半导体元件20的基板10上而成的两层构造(封装体叠层构造：package on package)。并且，半导体元件20与半导体元件60经由金属线70电连接。另外，在下层的基板10上填充有填充树脂40，上层的基板50上形成空心构造。以下对半导体模块1的各结构要素进行说明。
基板10是例如在平面形状大致呈矩形的底板11上形成有侧壁12的构造。但是，侧壁12形成在底板11外缘的三个边上，而在一个边上未形成。在基板10的底板11的上表面的一端侧(在图1中为右端侧)设有多个电极13。另外，在基板10的底板11上设置有与各电极13连接而成为外部端子的多个贯通电极(未图示)，并构成为能够进行半导体模块1与外部之间的电信号的输入输出。
作为基板10能够使用所谓玻璃环氧基板、陶瓷基板、硅基板等。基板10的底板11各边的长度例如可以是1.5mm～5mm左右。基板10的底板11及侧壁12的厚度例如可以是50μm～100μm左右。基板10的高度例如可以是数个100μm左右。
半导体元件20在基板10的底板11的上表面以正面(face-up)状态实装。在半导体元件20上表面的一端侧设有多个电极21。另外，在半导体元件20上表面的与一端侧对向的另一端侧(在图1中为左端侧)设有多个电极22。
半导体元件20的各电极21经由金属线30与基板10的各电极13电连接。作为金属线30例如可以采用金线、铜线等(所谓的键合线)。
填充树脂40与基板10的底板11的上表面及侧壁12的内侧面相接而包覆半导体元件20及金属线30。填充树脂40未填充到比基板50的底板51靠上侧(基板50的凹部内)的位置(该部分为空间)。作为填充树脂40例如能够采用以环氧类树脂为主成分的所谓的底部填充(underfill)树脂。填充树脂40也可以含有填料(filler)。
基板50例如是在平面形状大致呈矩形状的底板51上形成侧壁52的构造。在基板50上与基板10不同的是在底板51外缘的全部4边上形成有侧壁52。换言之，由基板50的底板51和侧壁52形成了斗状的凹部。另外，在基板50的底板51上形成有贯通孔53。
作为基板50可以采用所谓的玻璃环氧基板、陶瓷基板、硅基板等。基板50的底板51各边的长度例如可以是1.5mm～5mm左右。基板50的底板51及侧壁52的厚度例如可以是50μm～100μm左右。基板50的高度例如可以是数个100μm左右。另外，在本实施方式中在基板50上没有形成配线、电极等。
半导体元件60在基板50的底板51的上表面(凹部的底面)上以正面状态实装。在半导体元件60的上表面设有多个电极61。半导体元件60的各电极61介由通过贯通孔53的金属线70与半导体元件20的各电极22电连接。作为金属线70例如可以采用金线、铜线等(所谓的键合线)。
盖罩基板80固定在基板50的凹部的上部(侧壁52的上表面)。盖罩基板80保护半导体元件60等，例如在半导体元件60是具备隔膜的压力传感器、半导体元件20是半导体元件60的信号处理用IC的情况下，设置贯通孔81，将作为测定对象的气体导入半导体元件60。但是，在考虑半导体元件60的功能时，而不需要设置贯通孔81的情况下，则也可以将基板50的上侧完全封闭。作为盖罩基板80可以采用所谓的玻璃环氧基板、陶瓷基板、硅基板等。盖罩基板80的厚度例如可以是50μm～100μm左右。
另外，在上述说明中，基板10的侧壁12仅形成在底板11外缘的三个边上，但是也可以采用基板10的侧壁12仅形成在底板11外缘的一个边或两个边上的构造。在任一情况下都是在不存在侧壁12的一侧配置电极13。
[第一实施方式的半导体模块的制造方法]
接下来，对第一实施方式的半导体模块的制造方法进行说明。图2～图8是例示第一实施方式的半导体模块的制造工序的图。
首先，在图2所示的工序中准备基板50。虽然基板50最终会被切断而成为图1的具备底板51、侧壁52及贯通孔53的形状，但是在此阶段中则是宽幅地形成凹部外侧(在图2中为右端侧)的侧壁52并设有贯通孔54。基板50例如通过对所谓的玻璃环氧基板等实施锪孔加工、蚀刻加工、切削加工等进行制作。但是，在图2中仅图示了最终成为一个半导体模块1的部分，然而实际中是制作将图2的形状的基板50纵横排列而成的集成基板。另外，图2(a)是俯视图，图2(b)是沿图2(a)的B－B线的剖视图。
接下来，在图3所示的工序中，在基板50的底板51的上表面(凹部的底面)将上表面设有多个电极61的半导体元件60以正面状态粘接。作为粘接剂例如能够采用硅类粘接剂等。
接下来，在图4所示的工序中准备基板10。虽然基板10最终会被切断而成为图1的具备底板11及侧壁12的形状，但是在此阶段中则是一端侧(在图2中为右端侧)较长地伸展，在该部分上也形成侧壁12而作为整体形成了斗状的凹部。基板10例如可以通过对所谓的玻璃环氧基板等实施锪孔加工、蚀刻加工、切削加工等进行制作。其后，形成多个电极13、成为外部端子的多个贯通电极(未图示)等。但是，在图4中仅图示了最终成为一个半导体模块1的部分，然而实际中是制作将图4的形状的基板10纵横排列而成的集成基板。另外，图4(a)是俯视图，图4(b)是沿图4(a)的C－C线的剖视图。
接下来，在图5所示的工序中，在基板10的底板11的上表面(凹部的底面)以正面状态粘接半导体元件20，该半导体元件20在上表面的一端侧设置多个电极21，且在上表面的另一端侧设置多个电极22。作为粘接剂例如能够采用环氧类的粘接剂等。
接下来，在图6(a)所示的工序中，将基板10的各电极13与半导体元件20的各电极21用金属线30连接(所谓的引线键合)。在金属线30的连接中也可以采用反向键合(reverse-bonding)的工艺。由此，能够抑制从半导体元件20的上表面突出的金属线30的高度。另外，反向键合的工艺是将形成在金属线30前端的金属球先与低层侧的电极13连接，此后将金属线30环卷至高层的电极21附近的高度，然后将金属线30连接于高层侧的电极21。
接下来，在图6(b)所示的工序中，在半导体元件20的上表面从涂布装置510涂布基板支撑部件35。基板支撑部件35是在下一工序中用于支撑基板10上的基板50的部件。作为基板支撑部件35例如能够采用环氧类的树脂等。另外，既可以先执行图2及图3所示的工序和图4～图6所示的工序中的任一个，也可以同时执行。
接下来，在图7(a)所示的工序中，将粘接有半导体元件60的基板50(在图3所示的工序中制作的构造体)介由基板支撑部件35层叠在基板10上并进行粘接。其后通过加热等使基板支撑部件35固化，从而基板支撑部件35能够支撑基板10上的基板50。另外，虽然基板10和基板50最终是利用填充树脂40固定，但是在填充树脂40填充前的工序中，为了避免基板50与基板10相对移动，而利用基板支撑部件35对基板10上的基板50进行支撑。
接下来，在图7(b)所示的工序中，经由贯通孔53用金属线70对半导体元件60的各电极61和半导体元件20的各电极22进行连接(所谓的引线键合)。此时，基板10与基板50是用基板支撑部件35进行支撑，因此能够稳定地进行引线键合。另外，与金属线30的情况同样地，在金属线70的连接中也可以采用反转键合工艺。
接下来，在图8(a)所示的工序中，从树脂填充装置520经由基板50的贯通孔54向基板10与基板50之间的空间注入填充树脂40而覆盖半导体元件20。此时进行控制以避免填充树脂40流入比基板50的底板51靠上侧的位置。其后通过加热等使填充树脂40固化。作为填充树脂40例如能够采用以环氧类树脂为主成分的所谓的底部填充树脂。
接下来，在图8(b)所示的工序中，在图8(a)所示的构造体的基板50的凹部的上部(侧壁52的上表面)粘接盖罩基板80。但是在图8(b)中，仅图示了最终成为一个半导体模块1的部分，然而实际中是粘接将图8(b)的形状的盖罩基板80纵横排列而成的集成基板。
在粘接盖罩基板80后，为了除去贯通孔54而使用划片刀530等在切断位置CL进行切断，从而使各模块单片化而完成多个图1所示的半导体模块1。另外，图8(b)为了方便而以与图8(a)相同的方向进行了图示，但是在实际进行切断时则是上下翻转地从上侧使用划片刀530等进行切断。
这样，在半导体模块1的制造工序中，成为第一层的基板10的电极13仅形成在基板10的一端侧，在电极13与基板10的一端侧的侧壁12之间确保了充分的间隔。因此，在对基板10的电极13和半导体元件20的电极21进行引线键合时，避免了毛细管状键合头与侧壁12干涉。
另外，基板10的一端侧的侧壁12最终会被切断，半导体模块1在成为第一层的基板10的一端侧配置电极13，是在基板10的一端侧不存在侧壁12的构造。另外，最终避免在侧壁12所存在的一侧形成电极13，因此能够不考虑引线键合的工序而使侧壁12的内壁面与半导体元件20的外壁面接近。
由此，能够使半导体元件20的面积相对于基板10的面积的比例即实装面积率比现有构造大。另外，在现有构造中难以使实装面积率大于50％，但是在半导体模块1中则能使实装面积率为50％以上。
另外，在成为第一层的基板10上进行填充树脂40的填充，因此即使减薄侧壁12或将其取消也能够确保刚性。
另外，第二层的半导体元件60以在俯视时与第一层的半导体元件20部分或全部重叠的状态实装在基板10的平面形状内，并经由通过贯通孔53的金属线70连接。即，在上下基板的实装面积率无限接近的情况下，也能够避免在俯视时从基板10突出地进行实装及连接。其结果是能够使半导体模块1小型化。
另外，能够对实装第二层的半导体元件60的位置任意地进行调整，因此能够不依存于第一层的半导体元件20的引线键合区域地决定第二层的半导体元件60的尺寸。
〈第一实施方式的变形例1〉
在第一实施方式的变形例1中示出基板10没有侧壁的例子。另外，在第一实施方式的变形例1中有时对与已说明的实施方式相同的结构部省略说明。
图9是对第一实施方式的变形例1的半导体模块进行例示的剖视图，示出了与图1(a)对应的剖面。
如图9所示，半导体模块2与半导体模块1(参照图1)的区别在于基板10没有侧壁而仅由底板构成。即，基板10是平板而没有与基板50相接的部分。在基板10的上表面与基板50的底板51的下表面之间进行填充树脂40的填充来支撑基板50。
在制作半导体模块2时，首先执行与第一实施方式的图2～图7(a)同样的工序，制作图10(a)所示的构造体。但是，在图10(a)的时点，基板10由底板11和侧壁12构成。另外，在基板50中，除形成有贯通孔54的部分以外的三个边的侧壁52形成为比半导体模块1的情况厚，并采用在搭载于基板10上时各侧壁52的内壁面比基板10的侧壁12的内壁面向内侧突出的形状。
接下来，执行与第一实施方式的图7(b)及图8(a)同样的工序，在图10(b)所示的工序中，与图8(b)所示的工序同样地在切断位置CL进行切断。此时，将切断位置CL设定为比基板50的侧壁52的内壁面靠内侧。由此，基板10的侧壁12全部被切断，完成多个具备仅由底板11构成的基板10的半导体模块2(参照图9)。另外，图10(b)为了方便而以与图10(a)相同的方向进行了图示，然而实际进行切断时则是上下翻转地从上侧利用划片刀530等进行切断。
在半导体模块2中与半导体模块1相比能够进一步增大实装面积率。换言之，在将尺寸相同的半导体元件实装于基板10的情况下，在半导体模块2中与半导体模块1相比能够减小基板10的面积。即，能够使半导体模块2的封装整体小型化。或者，若基板10的尺寸与半导体模块1相同，则能够将比半导体模块1大的半导体元件实装于基板10。
这里，参照图11来说明能够在基板10上实装何种尺寸程度的半导体元件20。
在图11中设基板10的面积为A×A。在半导体模块2的情况下，基板10上没有侧壁，无需用于安装盖罩等的安装余量。因此，能够使半导体元件20的纵方向的长度为A－0.2～0.3左右，使横方向的长度为A－0.4～0.5左右，面积则成为(A－0.2～0.3)×(A－0.4～0.5)左右。另外，横方向的长度较短是为了确保配置电极13的区域。
A例如可以是1.5mm～5mm左右。假设A＝2mm时，则基板10的面积为A×A＝4mm2，半导体元件20的面积为基板10的面积的64～72％左右。即，实装面积率为64～72％左右。
在现有的半导体模块中，实装面积率小于50％，因此可知半导体模块2中的实装面积率得到大幅提高。即，在半导体模块2的构造中能够将在现有构造中无法进行实装的尺寸的半导体元件在尺寸相同的基板上进行实装。
〈第一实施方式的变形例2〉
在第一实施方式的变形例2中示出了在保护层上配置半导体元件60的例子。另外，在第一实施方式的变形例2中有时对与已说明的实施方式相同的结构部省略说明。
图12是对第一实施方式的变形例2的半导体模块进行例示的剖视图，示出了与图1(a)对应的剖面。
如图12所示，半导体模块3与半导体模块1(参照图1)的区别在于：在基板50的底板51的上表面形成保护层隔板(partition)55及保护层隔垫(spacer)56，在其上用粘接树脂90粘接有半导体元件60。
在制作半导体模块3时，首先制作第一实施方式的图2所示的基板50。然后，例如通过采用焊料保护层的印刷法等，在基板50的底板51的上表面形成图13(a)所示的保护层隔板55及保护层隔垫56。设置保护层隔板55是为了防止粘接树脂90的扩展。另外，保护层隔垫56是用于搭载半导体元件60的基座。
例如，将保护层隔板55形成为十字状，在以十字状划分的各区域上逐一地配置保护层隔垫56。但是，保护层隔板55的形状、在所划分的各区域上配置的保护层隔垫56的数量不限于图13(a)的例示。保护层隔板55及保护层隔垫56的高度例如可以是10～40μm左右。
接下来，在图13(b)所示的工序中，在各保护层隔垫56上及其周围涂布粘接树脂90。粘接半导体元件60的粘接树脂90优选为具有比粘接半导体元件20的粘接树脂(环氧类树脂等)低的弹性(低杨氏模量)。作为粘接树脂90例如可以采用低杨氏模量的粘接树脂即硅类树脂。另外，作为粘接树脂90可以采用低杨氏模量的粘接树脂即环氧聚氨酯类树脂等。
另外，硅类树脂的杨氏模量是1.0×10－2～10－3GPa左右，环氧聚氨酯类树脂的杨氏模量是50.0×10－2～10－3GPa左右。这些是相对于在半导体元件20的粘接等中使用的环氧类树脂的杨氏模量5.0～10.0GPa左右而大幅减小的值。
接下来，在图14所示的工序中，在基板50上实装半导体元件60。具体而言，在基板50的底板51的上表面介由保护层隔垫56搭载半导体元件60，并通过加热等使粘接树脂90固化。另外，图14(a)是俯视图、图14(b)是沿图14(a)的D－D线的剖视图。
其后，执行与第一实施方式的图4～图8(b)同样的工序，从而完成多个半导体模块3(参照图12)。途中经过在半导体元件60的电极61上对金属线70进行引线键合的工序，在半导体元件60的下侧布设保护层隔垫56。因此，即便使用低杨氏模量的粘接树脂90，也能够稳定地进行引线键合(能够提高引线接合性)。
另外，如果不设保护层隔垫56而介由低杨氏模量的粘接树脂90将半导体元件60直接固定于基板50，则会导致在以金属线70结线时的引线接合性恶化。该情况下，需要取代低杨氏模量的粘接树脂90而使用环氧类树脂等的弹性比较高的粘接树脂，但是在半导体元件60为压力传感器时则无法吸收外部应力，因而半导体元件60的特性会发生变化。
在本实施方式中，在设置保护层隔垫56的基础上使用了低杨氏模量的粘接树脂90。因此，能够防止引线接合性恶化，并且即使半导体元件60为压力传感器，也能够由低杨氏模量的粘接树脂90吸收半导体元件60的应力，因此能够抑制半导体元件60的特性变化。
这样，与在第一层的半导体元件上直接层叠第二层的半导体元件的现有构造不同，在半导体模块3中在第二层的半导体元件60的正下方是基板50。因此，能够利用保护层隔板55实现低杨氏模量的粘接树脂90的分割涂布并利用保护层隔垫56提高引线接合性。但是，也可以不设保护层隔板55而仅设置保护层隔垫56。
〈第一实施方式的变形例3〉
在第一实施方式的变形例3中示出了三层构造的半导体模块的例子。另外，在第一实施方式的变形例3中有时对与已说明的实施方式相同的结构部省略说明。
图15是例示第一实施方式的变形例3的半导体模块的剖视图，示出了与图1(a)对应的剖面。
如图15所示，半导体模块4是三层构造，区别于半导体模块1(图1参照)的两层构造。具体而言，在基板50与盖罩基板80之间插入有基板100。
基板100是与基板50同样的构造，在底板101外缘的全部四个边上形成有侧壁102。换言之，由基板100的底板101和侧壁102形成了斗状的凹部。另外，在基板100的底板101上形成有贯通孔103。基板100的材料、厚度等例如能够与基板50相同。
在基板100的底板101的上表面(凹部的底面)以正面状态实装有半导体元件110。在半导体元件110的上表面设有多个电极111。半导体元件110的各电极111介由通过贯通孔103的金属线120与半导体元件60的各电极62电连接。作为金属线120例如可以采用金线、铜线等(所谓的键合线)。在基板100的侧壁102的上表面固定有盖罩基板80。
这样，通过层叠与基板50同样构造的基板，不必扩大平面形状(不必改变实装面积)便能够实现三层构造的半导体模块。也可以进一步层叠与基板50同样构造的基板而形成四层以上构造的半导体模块。
〈第一实施方式的变形例4〉
在第一实施方式的变形例4中，示出了实装有无源零件的半导体模块的例子。另外，在第一实施方式的变形例4中有时对与已说明的实施方式相同的结构部省略说明。
图16是例示第一实施方式的变形例4的半导体模块的剖视图，示出了与图1(a)对应的剖面。
如图16所示，半导体模块5与半导体模块1(参照图1)的主要区别在于，取代半导体元件20而实装有电阻130及电容140。电阻130及电容140的电极(未图示)以各自的一端侧与基板10的电极(未图示)进行了倒装芯片连接。另外，电阻130及电容140的电极(未图示)经由基板10的配线(未图示)并以各自的另一端侧与电极13连接，电极13用金属线70与半导体元件60的电极61电连接。
在本实施方式中示出了半导体元件60不是压力传感器的例子。由于半导体元件60不是压力传感器，因此未在盖罩基板80上形成贯通孔81。另外，填充树脂40填充于基板10与基板50之间，并且也填充到比基板50的底板51靠上侧(基板50的凹部内)而不存在空心空间。
这样，在基板10、基板50上不仅可以实装半导体元件，也可以实装电阻、电容等无源零件。能够使半导体元件和无源零件混合存在于基板10上或基板50上。
另外，能够根据半导体元件等的功能适当地选择进行填充树脂的填充的区域。此时，也可以填充多种填充树脂。例如，也可以在无源零件周围填充环氧类树脂，在半导体元件周围填充低弹性的硅类树脂等。该情况下，对于搭载应力耐性差(会因应力而发生特性变化)的半导体元件的情况特别有效。
以上对优选实施方式及变形例进行了详细说明，但是不限于上述实施方式及变形例，而能够在不脱离专利申请范围的前提下，对上述实施方式及变形例实施各种变形及置换。
例如，可以在基板10上搭载多个半导体元件等，也可以在基板50上搭载多个半导体元件等。

Claims (12)

1.一种半导体模块，其特征在于，具有：
具有多个电极的第一基板；
粘接于上述第一基板的具有多个电极的第一元件；
层叠在上述第一基板上的具备凹部的第二基板；以及
粘接于上述凹部的具有多个电极的第二元件，
在上述第一元件的一端侧，将上述第一元件的电极与上述第一基板的电极电连接，
在与上述一端侧对向的另一端侧，将上述第一元件的电极与上述第二元件的电极经由设置在上述凹部的贯通孔直接进行电连接。
2.根据权利要求1所述的半导体模块，其特征在于，在上述凹部的上部具有盖罩基板。
3.根据权利要求1或2所述的半导体模块，其特征在于，上述第一元件被树脂覆盖。
4.根据权利要求1或2所述的半导体模块，其特征在于，在上述第一元件上搭载有对上述第二基板进行支撑的基板支撑部件。
5.根据权利要求1或2所述的半导体模块，其特征在于，上述第二元件通过粘接树脂粘接于上述凹部，该粘接树脂涂布在设于上述凹部的第一保护层上。
6.根据权利要求5所述的半导体模块，其特征在于，上述粘接树脂涂布在由第二保护层划分的区域上。
7.根据权利要求5所述的半导体模块，其特征在于，粘接上述第二元件的上述粘接树脂与粘接上述第一元件的粘接树脂相比呈低弹性。
8.根据权利要求6所述的半导体模块，其特征在于，粘接上述第二元件的上述粘接树脂与粘接上述第一元件的粘接树脂相比呈低弹性。
9.根据权利要求1或2所述的半导体模块，其特征在于，上述第二元件被树脂覆盖。
10.根据权利要求1或2所述的半导体模块，其特征在于，在上述第一基板上搭载有包含上述第一元件的至少一个元件，在上述第二基板上搭载有包含上述第二元件的至少一个元件。
11.一种半导体模块的制造方法，其特征在于，具有：
准备具有多个电极的第一基板的工序；
在上述第一基板上粘接具有多个电极的第一元件的工序；
在上述第一元件的一端侧将上述第一元件的电极与上述第一基板的电极电连接的工序；
准备第二基板的工序，该第二基板具备具有第一贯通孔的凹部以及设置在上述凹部的外侧的第二贯通孔；
在上述凹部粘接具有多个电极的第二元件的工序；
在上述第一基板上层叠上述第二基板的工序；
在与上述一端侧对向的另一端侧将上述第一元件的电极与上述第二元件的电极经由上述第一贯通孔进行电连接的工序；
从上述第二贯通孔注入树脂而由上述树脂覆盖上述第一元件的工序；
在上述凹部的上部粘接盖罩基板的工序；以及
以除去上述第二贯通孔的方式将上述盖罩基板、上述第二基板、上述第一基板以及上述树脂切断的工序。
12.根据权利要求11所述的半导体模块的制造方法，其特征在于，上述第一基板、上述第二基板、上述盖罩基板由用于构成多个模块的集成基板构成，
在粘接上述盖罩基板的工序之后具有使各个模块单片化的工序。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101427365A (zh) * 2006-09-06 2009-05-06 日立金属株式会社 半导体传感器件及其制造方法
CN103579207A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法

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JP2010093303A (ja) * 2010-01-25 2010-04-22 Epson Toyocom Corp 電子デバイスの製造方法
JP2012073233A (ja) * 2010-08-31 2012-04-12 Mitsumi Electric Co Ltd センサ装置及び半導体センサ素子の実装方法
JP5699838B2 (ja) * 2011-07-14 2015-04-15 豊田合成株式会社 発光装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101427365A (zh) * 2006-09-06 2009-05-06 日立金属株式会社 半导体传感器件及其制造方法
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