CN105814690B - 用于半导体器件的边缘终止和对应的制造方法 - Google Patents

用于半导体器件的边缘终止和对应的制造方法 Download PDF

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CN105814690B
CN105814690B CN201480068737.5A CN201480068737A CN105814690B CN 105814690 B CN105814690 B CN 105814690B CN 201480068737 A CN201480068737 A CN 201480068737A CN 105814690 B CN105814690 B CN 105814690B
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termination
trench
region
substrate
field plate
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M.安托尼奧
F.尤德里
I.尼斯托
M.拉希莫
C.科瓦斯塞
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Hitachi Energy Co ltd
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Abstract

描述垂直DMOSFET或IGBT的终止区（4），其中表面p环（10）与氧化物/多晶硅填充的沟槽（40）、掩埋p环（41）和可选的表面场板（11）组合，以便在终止区（4）中获得电势场线（7）的改进分布。表面环终止（10，11）和深环终止（41）的组合提供终止区（4）面积的明显减少。

Description

用于半导体器件的边缘终止和对应的制造方法
技术领域
本发明涉及半导体器件的终止设置（termination arrangement），并且特别但不排除涉及例如二极管、晶体管或绝缘栅双极晶体管（IGBT）等需要耐受几百或几千伏反向电压的高压（HV）半导体器件的终止设置。
背景技术
高压半导体器件典型地包括终止区，其使器件与环绕衬底和/或与器件的封装电隔离。终止区必须确保器件的有源区免受高压影响，并且器件的器件击穿电压尽可能高。
对于例如DMOSFET或IGBT等高压器件，轻掺杂漂移区可采用确保场或电势线的最佳分布这样的方式终止，这对于实现器件的全额定电压是重要的。为了变得有效，这样的终止区应优选地具有比器件的内部（有源）区更高的电压耐受能力。
电终止可以通过介电材料和/或通过反向偏置的pn结实现。在介电隔离下，可使用例如二氧化硅等介电绝缘体材料，在该情况下电终止可通过在环绕器件有源区的终止区中形成氧化物填充沟槽而实现。这样的终止沟槽在使电势或场线横向通过衬底本体分布时可以是有效的，但可使得表面处电荷和电势分布相对未受控。
备选地，可使用结隔离终止，其中反向偏置的p-n结有助于实现通过终止区的需要的场或电势线分布。例如可使用与漂移区相反掺杂的表面保护环来使电势跨接近衬底表面的终止区分布。然而，这样的终止设置在接近表面的衬底本体中防止电势线拥挤方面不太有效。此外，这样的现有技术的终止设置典型地牵涉附加制造步骤和/或掩模，或制造工艺可对终止元件的几何形状和/或配置施加限制。
US 2008/042172 A1指现有技术的MOS晶体管，其包括有源单元区中的槽栅和终止区中的终止槽栅，它们被一个毗邻的p掺杂层所环绕。
在US 2009/090968 A1中描述现有技术的MOS器件，其在终止区中具有被场板电极覆盖的p保护环。
发明内容
本发明的目标是克服现有技术的终止设置的劣势中的至少一些。为此，本发明预示如在权利要求1中阐述的制造方法和如在权利要求6中阐述的半导体器件。本发明的另外的变化形式在从属权利要求2至5和7至11中阐述。
通过使终止沟槽和掩埋保护环的制造与表面保护环的制造结合，实现较高终止效率（即，减少的终止区和/或增加的击穿电压）同时使需要的额外制造加工量最小化，这是可能的。终止沟槽和/或表面保护环上场板的添加可进一步提高终止效率。
通过具有终止沟槽和深埋保护环（其邻接终止沟槽）的设置，电场在终止区中保持在到达这样的掩埋终止沟槽这一高的深度使得电场的电势线从有源区向外横向引导，这使击穿电压增加。由于表面保护环在朝衬底边缘的终止沟槽侧上邻接终止沟槽，电场从有源区进一步向外展开，但在接着的向外延伸的终止沟槽之前仍被高效终止，即电场更好地被控制终止，但仍在短的横向距离内。
在朝着有源单元区的侧上具有邻接每个终止沟槽的漂移层并且具有仅在朝着衬底边缘侧上设置的表面保护环使得电场被引导以在终止沟槽以外（即终止沟槽向外（即，在朝这着衬底边缘的侧上））的区域中终止。朝着有源单元区的终止沟槽侧上表面保护环的存在将阻挠远离有源单元区引导电势线的效应。
在示范性实施例中，使终止沟槽与表面保护环连接的场板的存在促进在离有源单元区的短但受控横向距离内终止电场的效应并且保护衬底的表面。
从而发明性半导体器件能够具有在小的距离内具有高效场终止的器件使得该器件可以更可靠地操作并且可以比现有技术的器件设计得更紧凑，即终止区（即，终止区的横向延伸）可以减少。
附图说明
现在将参考附图更详细描述本发明，其中：
图1在示意横截面图中示出如现有技术中已知的使用p环和场板终止的n沟道DMOS器件的示例。
图2在示意横截面图中示出如现有技术中已知的使用p环和场板终止的槽栅n沟道器件的示例。
图3在示意横截面图中示出如现有技术中已知的使用沟槽和掩埋p环终止的n沟道DMOS器件的示例。
图4在示意横截面图中示出如现有技术中已知的使用沟槽和掩埋p环终止的槽栅n沟道器件的示例。
图5在示意横截面图中示出根据本发明使用沟槽、掩埋保护环和表面保护环终止的n沟道DMOS器件的示例。
图6在示意横截面图中示出根据本发明使用沟槽、掩埋保护环和表面保护环终止的槽栅n沟道器件的示例。
图7在示意横截面图中示出根据本发明使用沟槽、掩埋保护环和表面保护环终止的n沟道DMOS器件的示例。
图8在示意平面图中示出根据本发明终止的通用器件的示例。
应注意图作为理解本发明基础的某些原理的辅助手段提供，并且不应视为暗指在寻求的保护范围中的任何限制。在相同参考符号在不只一个图中使用的情况下，这些意在指相同或对应的特征。然而，不同参考符号的使用不应视为指示符号所指的特征之间的差异。
具体实施方式
图1示出如本现有技术中已知的n沟道耗尽MOSFET或IGBT的横截面图的示例。有源单元区3包括功率MOSFET或IGBT单元的阵列，每个具有p掺杂本体区20（即，第二传导类型），其环绕在两个n掺杂区21（即第一传导类型）与p掺杂本体（阱）区20之间形成的两个p-n结。提供两个栅极连接23（在该示例情况下，每个与相邻单元共享）用于控制从p-n结到漂移区6内以及通过器件衬底6（采用n漂移层的形式）到漏极/阴极层5（在n沟道DMOSFET情况下是n掺杂，或在n沟道IGBT情况下是p掺杂）的电流流动。经由发射极/阳极触点24向每个器件单元供电。
图1还示出可如何使用跨边缘终止区4分布的保护环10和场板11来终止MOSFET或IGBT。可通过包含在衬底材料表面中形成的p掺杂保护环10而防止电势线7在有源区3的边缘周围集中。保护环10中的每个在轻p掺杂保护环10与轻n掺杂漂移区6之间形成弱掺杂p-n结并且在反向偏置情况下通过使耗尽层从衬底6边缘进一步向外展开、进一步经过处于递降电势的保护环10直到有源区3中存在的高电荷密度跨终止区4渐缩为零而起到使衬底表面处的电场拥挤减少的作用。场板11起到在表面附近使电势更均匀分布的作用，由此避免电势线集中（“拥挤”）。
图2示出n沟道槽栅MOSFET或IGBT的横截面图。如在图1中示出的器件中的一样，器件的有源单元区3通过衬底6的终止区4延伸。终止区4使用表面p环（保护环）10，其在终止区4的表面处或附近部分替代漂移层材料6。场板11也添加到p环10中的每个的边缘。如与图1的示例器件一样，保护环10和场板11起到使电势线7偏转并且在终止区4的表面区防止电势线集中的作用。
图3和4分别示出与图1和2中描绘的那些相似的器件，但用终止沟槽40而不是图1和2的表面p环10终止。终止沟槽40中的每个可用例如二氧化硅等介电材料或例如多晶硅等传导材料填充。p掺杂区41可在每个终止沟槽40的末端或顶端处或附近形成，以在终止沟槽40末端周围提供电势线的增强偏转。已知深p掺杂区41（也称为深或掩埋保护环41）是参考图1和2描述的表面保护环10的有效备选。
注意参考图1至4描述的器件是耗尽型器件，其中专用p-n结在关断状态耗尽以便耐受关断态电压。也就是说，耗尽区使p掺杂区和n掺杂区彼此电隔离。
图5示出发明性MOSFET的第一实施例。轻n掺杂区6部分可称为“漂移区”、“轻掺杂区”或“反向电压支撑区”。对于通过以低n掺杂浓度衬底开始而制作的功率器件，最终功率器件中的漂移层6将是通过制造步骤未修改的掺杂浓度层。示范性地，漂移层6具有恒定低的掺杂浓度。其中，漂移层6的大致恒定掺杂浓度意指掺杂浓度在整个漂移层6中是大致均匀的，然而不排除由于例如外延生长过程中的波动而可能存在漂移层内掺杂浓度中的波动是约分数五分之一。由于应用需要选择最终漂移层厚度和掺杂浓度。漂移层6的示范性掺杂浓度在5*1012 cm-3与5*1014 cm-3之间。
然而，本发明的实现不限于这样的器件；其他可能包括例如它在超结（SJ）或需要终止的其他类型的器件中的使用。在SJ器件中，漂移区可典型地被交替高掺杂p和n层替代，其在相互电荷补偿下可以完全在关断态耗尽并且支持跨器件的高电压。
相似地，尽管图示出一个特定掺杂方案（例如n沟道MOSFETS），它当然将可能使用不同（例如反向）的掺杂方案。
图5和6图示利用本发明的原理的终止设置的示例。在图5和6中描绘的器件的有源区3分别对应于图1和2或3和4的有源区。衬底6包括（n-）掺杂漂移层。在有源单元区中，器件包括衬底相对侧上的第一和第二主侧上的主电触点。衬底6包括有源单元区3，其被终止区4横向环绕（即，在与主侧平行的平面中），该终止区4延伸到衬底边缘（衬底的横向表面侧）。
在终止区4中，相比之下，图5和6中示出的器件结合终止沟槽40与掩埋保护环41的原理，和表面保护环10的变化形式，其中保护环具有与漂移层不同的传导类型，在该示例中保护环是p掺杂。在图5和6中示出的示例器件两者中，终止区4包括终止沟槽40和掩埋保护环41，其通过将电势线从有源区3向外横向引导来提供主终止效应。每个终止沟槽40还具有外相邻表面保护环10（邻接终止沟槽40的外侧）来引导电势线7（其否则将在终止沟槽周围弯曲，如在图3和4中指示的）并且可在每个终止沟槽40的外侧附近形成电势线7的局部拥挤，以使它们进一步向外并且远离终止沟槽40展开。从而，终止沟槽40下p掺杂掩埋保护环41的存在使电场的部分更深地释放到器件硅内，因此击穿电压增加。终止沟槽40可用例如氧化物或多晶硅填充。通过使表面p环10与终止沟槽40的外侧对准，保护邻近每个终止沟槽40的终止区4的表面以免受高电场影响。表面可通过在每个表面p环（10）边缘处形成场板（例如，介电氧化物的）而进一步受到保护。
终止沟槽40（具有它们的掩埋p环41）和表面p环10（第二传导类型的环）可采用自对准方式制造。可提供n掺杂衬底6。例如，表面p环10可首先在衬底6中形成（例如通过植入和扩散），并且然后可蚀刻或另外形成终止沟槽40使得终止沟槽中的一个的外边缘（从有源单元区3向外的边缘，即朝着衬底边缘）与它的邻接表面p环的向内的部分（朝有源单元区3）相交。终止沟槽40可采用常规方式通过去除衬底材料形成。一旦打开终止沟槽40，则可在终止沟槽40下通过在邻近每个终止沟槽40底部的区41中植入（掺杂）衬底本体而形成掩埋p环41。有利地，需要的工艺步骤和/或掩模的数量可通过在终止区4和p阱本体20或本体32中使用相同掩模和相同掺杂工艺形成表面p环10而减少。从而，对于图5中图示的示例器件，可有利地配置制造工艺使得相同掩模和工艺不仅用于终止区4中的表面p环10，而且用于有源区中的器件单元本体（p阱）区20。对于图6中示出的示例器件，可有利地配置制造工艺使得相同掩模和/或工艺不仅用于终止区4中的终止沟槽40，而且用于有源区3中的器件单元的器件单元槽栅30。另外，在对于图6中示出的示例器件的制造工艺中，单个掩模和/或工艺可有利地用于在终止区4中形成表面p环10以及在有源区3中形成p本体层32。
还可形成表面场板11，其部分或完全覆盖每个终止沟槽40和它的邻接表面保护环10，并且在将终止沟槽40分离的漂移区6（n掺杂区，即第二传导类型，该传导类型与第一传导类型不同）的表面上向外延伸超出表面保护环10。终止区4上的电场分布可通过适当选择终止沟槽40、表面p环10和掩埋p环41的尺寸和间距来控制。
图7示出终止沟槽40、掩模p环41、表面p环10和场板11的一些尺寸的示例。尽管在图7中仅图示两个终止沟槽40，应理解该数量实际上可大得多-例如跨终止区4分布多达15或20个或以上。
通过示例，有源区3的边缘与第一终止沟槽40之间的距离16可例如在5μm至10μm之间（例如7μm）。台面宽度15（即相邻终止沟槽40之间的分离距离）可例如是7-20μm，并且可在远离有源区3的方向上增加。沟槽深度9可在4与7μm之间（例如5.2μm），沟槽宽度17可例如在制造工艺所允许的最小值与4μm之间（例如1.2μm）。掩埋p环41的峰值掺杂浓度可在1016 cm-3与1018 cm-3之间（例如1017 cm-3），并且2μm掺杂深度处的掺杂浓度可在1015 cm-3与1016 cm-3之间（例如5×1015 cm-3）。深p环（掩埋保护环）41的高度8可在2与5μm之间（例如3-4μm）。表面p环（保护环）10的横向范围可在1与5μm之间，并且优选地在1与2μm之间，例如1.5μm，而表面p环（保护环）10的垂直范围（深度）优选地与有源区3中的器件单元的p阱（本体区）20的深度大致相同。相似地，表面p环（保护环）10的掺杂浓度优选地与有源区3中的器件单元的p阱20的大致相同。对于具有这些优选尺寸的器件，场板宽度12可例如在3与8μm之间，或更优选地在4与6μm之间（例如4.5μm）。保护环/沟槽/场板终止可使用例如植入、扩散、蚀刻和再填等标准器件加工技术制成。表面10和深保护环41、场板11和氧化物/多晶硅填充沟槽40的尺寸和距离可以改变来适应需要的反向击穿电压。
表面和深环终止、介电/沟槽终止和场板的组合在需要高压器件（可需要其耐受5kV、6kV或以上的反向电压）的有效结终止的终止区中提供明显的面积减少。在较低电压（例如1.3kV），发现这里描述的终止在终止区的最小径向范围内提供30%或以上的减少。
图8示出终止区（其包括终止沟槽40和场板11）的简化示例的示意平面图。表面保护环10（被场板11掩盖）和掩埋保护环41（在终止沟槽40下）不可见。在上文描述的终止设置的现实实现中，终止结构（终止沟槽40、掩埋保护环41、表面保护环10和场板11）的数量将比图8中示出的两个大得多。

Claims (15)

1.一种制造半导体功率器件的方法，其中所述半导体功率器件包括具有有源单元区（3）的半导体衬底（6），所述有源单元区（3）包括第一传导类型的漂移层和直至衬底边缘的边缘终止区（4），并且其中所述方法包括：
在所述边缘终止区（4）的表面中形成与第一传导类型不同的第二传导类型的多个表面保护环（10）的第一步骤，所述多个表面保护环（10）彼此分离，
去除衬底材料（6）以便形成从所述边缘终止区（4）的表面向下延伸的多个终止沟槽（40）的第二步骤，使得每个表面保护环（10）仅在朝着所述衬底边缘的侧上邻接相邻终止沟槽（40）并且所述漂移层在朝着所述有源单元区（3）的侧上邻接所述终止沟槽（40）使得所述漂移层将所述终止沟槽（40）分离，
在邻近每个终止沟槽（40）底部的衬底材料中形成第二传导类型的掩埋保护环（41）的第三步骤，以及
用介电材料填充每个终止沟槽（40）的第四步骤。
2.如权利要求1所述的方法，其中第五步骤：对于每个终止沟槽（40），在终止沟槽（40）的一部分和它的邻接表面保护环（10）上形成场板（11）。
3.如权利要求1所述的方法，其中形成场板（11），所述场板（11）在朝着所述衬底边缘的侧上在所述漂移层表面上延伸超出所述表面保护环。
4.如权利要求1所述的方法，其中所述第一步骤在所述第二步骤之前执行使得对于所述多个终止沟槽（40）中的每个，在所述第二步骤中去除的衬底材料包括所述表面保护环（10）中的一个的一部分。
5.如权利要求1所述的方法，其中所述有源单元区（3）包括多个槽栅器件单元（30，31，33），并且其中所述第二步骤包括在与所述终止沟槽（40）相同的制造工艺或多个工艺期间形成所述槽栅器件单元（30，31，33）的沟槽（30）。
6.如权利要求1所述的方法，其中所述有源单元区（3）包括多个有源器件单元（20，21，23，24），每个包括本体区（20），并且其中所述第一步骤包括在与所述表面保护环（10）相同的制造工艺或多个工艺期间形成所述有源器件单元（20，21，23，24）的本体区（20）。
7.如权利要求5或权利要求6所述的方法，其中第五步骤：对于每个终止沟槽（40），在终止沟槽（40）的一部分和它的邻接表面保护环（10）上形成场板（11）并且，
其中每个有源器件单元（20，21，23，24）包括栅极连接（23）和电力连接（24）中的至少一个，并且其中所述第五步骤包括在与所述场板（11）相同的制造工艺或多个工艺期间形成所述栅极连接（23）和所述电力连接（24）中的至少一个。
8.如权利要求5或权利要求6所述的方法，其中第五步骤：对于每个终止沟槽（40），在终止沟槽（40）的一部分、它的邻接表面保护环（10）上形成场板（11）并且所述场板（11）在朝着所述衬底边缘的侧上在所述漂移层表面上延伸超出所述表面保护环，并且
其中每个有源器件单元（20，21，23，24）包括栅极连接（23）和电力连接（24）中的至少一个，并且其中所述第五步骤包括在与所述场板（11）相同的制造工艺或多个工艺期间形成所述栅极连接（23）和所述电力连接（24）中的至少一个。
9.一种半导体功率器件，其包括半导体衬底（6），所述半导体衬底（6）具有有源单元区（3），其包括第一传导类型的漂移层和直至衬底边缘的边缘终止区（4），其中所述边缘终止区（4）包括：
设置在所述衬底（6）的表面中、与所述第一传导类型不同的第二传导类型的多个表面保护环（10），其彼此分离，
从所述衬底（6）的表面向下延伸并且用介电材料填充的多个终止沟槽（40），使得每个表面保护环（10）仅在朝着所述衬底边缘的侧上邻接相邻终止沟槽（40）并且所述漂移层在朝着所述有源单元区（3）的侧上邻接所述终止沟槽（40）使得所述漂移层将所述终止沟槽（40）分离，以及
多个掩埋保护环（41），每个掩埋保护环（41）设置在所述衬底（6）中邻近所述终止沟槽（40）中的一个的底部。
10.如权利要求9所述的半导体功率器件，其中至少一个场板（11）设置在终止沟槽（40）的一部分和它的邻接表面保护环（10）上。
11.如权利要求10所述的半导体功率器件，其中所述至少一个场板（11）在朝着所述衬底边缘的侧上在所述漂移层表面上延伸超出所述表面保护环。
12.如权利要求9至11中任一项所述的半导体功率器件，其中所述有源单元区（3）包括多个槽栅器件单元（30，31，33），并且其中所述终止沟槽（40）用与所述槽栅器件（30，31，33）的槽栅沟槽（30）相同的材料填充。
13.如权利要求9所述的半导体功率器件，其中所述有源单元区（3）包括多个有源器件单元（20，21，23，24），每个包括第二传导类型的本体区（20），并且其中所述表面保护环（10）具有与所述有源器件单元（20，21，23，24）的本体区（20）相同的掺杂浓度。
14.如权利要求13所述的半导体功率器件，其中至少一个场板（11）设置在终止沟槽（40）的一部分和它的邻接表面保护环（10）上并且其中
每个有源器件单元（20，21，23，24）包括栅极连接（23）和电力连接（24）中的至少一个，并且其中所述终止沟槽（40）和表面保护环场板（11）包括与所述有源器件单元（20，21，23，24）的栅极连接（23）和功率连接（24）中的至少一个相同的材料。
15.如权利要求14所述的半导体功率器件，其中所述至少一个场板（11）在朝着所述衬底边缘的侧上在所述漂移层表面上延伸超出所述表面保护环。
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DE102015212464B4 (de) * 2015-07-03 2019-05-23 Infineon Technologies Ag Leistungshalbleiterrandstruktur und Verfahren zu deren Herstellung
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101969068A (zh) * 2010-08-06 2011-02-09 浙江大学 一种高压功率半导体器件的边缘终端结构
CN103165604A (zh) * 2011-12-19 2013-06-19 英飞凌科技奥地利有限公司 具有节省空间的边缘结构的半导体部件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10014660C2 (de) * 2000-03-24 2002-08-29 Infineon Technologies Ag Halbleiteranordnung mit einer durch einen Hohlraum von einer Driftstrecke getrennten Trenchelektrode
JP2007109712A (ja) * 2005-10-11 2007-04-26 Shindengen Electric Mfg Co Ltd トランジスタ、ダイオード
JP4735235B2 (ja) * 2005-12-19 2011-07-27 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
JP5188037B2 (ja) * 2006-06-20 2013-04-24 株式会社東芝 半導体装置
DE102006036347B4 (de) * 2006-08-03 2012-01-12 Infineon Technologies Austria Ag Halbleiterbauelement mit einer platzsparenden Randstruktur
JP2009088345A (ja) * 2007-10-01 2009-04-23 Toshiba Corp 半導体装置
CN102473721B (zh) * 2009-07-31 2015-05-06 富士电机株式会社 半导体装置
US8785279B2 (en) * 2012-07-30 2014-07-22 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (FBM)
US8680613B2 (en) * 2012-07-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Termination design for high voltage device
CN103715232B (zh) * 2012-09-28 2017-10-10 中国科学院微电子研究所 用于半导体功率器件的沟槽式终端及其制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101969068A (zh) * 2010-08-06 2011-02-09 浙江大学 一种高压功率半导体器件的边缘终端结构
CN103165604A (zh) * 2011-12-19 2013-06-19 英飞凌科技奥地利有限公司 具有节省空间的边缘结构的半导体部件

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