CN105814679A - 细间距再分布线的保持 - Google Patents

细间距再分布线的保持 Download PDF

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Publication number
CN105814679A
CN105814679A CN201380077002.4A CN201380077002A CN105814679A CN 105814679 A CN105814679 A CN 105814679A CN 201380077002 A CN201380077002 A CN 201380077002A CN 105814679 A CN105814679 A CN 105814679A
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China
Prior art keywords
rdl
line
seed layer
additional
sidewall
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K.J.李
H.科萨里
W.M.利特尔
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Intel Corp
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Intel Corp
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Abstract

实施例包括一种半导体装置，其包括：再分布层（RDL），所述再分布层（RDL）包含具有两个RDL侧壁的图案化RDL线，所述RDL包含选自包括Cu和AU的组的材料；直接接触所述两个RDL侧壁的保护侧壁；包含所述材料的种子层；以及阻挡层；其中（a）所述RDL线具有与所述两个RDL侧壁正交且在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层和阻挡层各包括与所述RDL线宽平行且比所述RDL线宽更宽的宽度。本文描述了其他实施例。

Description

细间距再分布线的保持
技术领域
实施例包括半导体加工，以及更确切地来说，包括半导体加工期间保持再分布层尺寸。
背景技术
与晶片关联的硅通孔（TSV）可能未与晶片的触点（例如，焊盘）对齐。在此类情况中，可以将如金属层的导电再分布层（RDL）图案化在晶片的背侧或晶片的装置侧上。图案化可以包括光刻技术，其中例如在晶片背侧表面上沉积铜材料。然后使用掩膜来定义RDL并蚀刻图形，以使RDL具有从TSV到与晶片或另一个晶片的接触点（例如，C4凸点、接触盘）电接触的期望位置的侧向延伸的指形体/突起。RDL可以经例如焊接连接到晶片的触点。
附图说明
从所附权利要求，一个或多个示例实施例的下文详细描述和附图将显见到本发明的特征和优点，其中：
图1包括具有图案化RDL线的半导体装置。
图2包括包含图1的图案化RDL线的物理简化版本的半导体装置。
图3包括本发明实施例中包含图案化RDL的半导体装置。
图4包括本发明实施例中在RDL侧壁保护层沉积之后的包含图案化RDL的半导体装置。
图5包括本发明实施例中在RDL侧壁保护层蚀刻之后的包含图案化RDL的半导体装置。
图6包括本发明实施例中在种子层蚀刻之后的包含图案化RDL的半导体装置。
图7包括本发明实施例中在阻挡层蚀刻之后的包含图案化RDL的半导体装置。
图8包括本发明实施例中的半导体装置加工方法。
图9包括配合本发明实施例使用的系统。
具体实施方式
现在参考附图，其中相似结构可以配有相似后缀的引用编号。为了更明确地示出多种实施例的结构，本文包含的附图是半导体/电路结构的示意性表示。因此，虽然引入图示的实施例的要求权利的结构，但是制造的集成电路结构的实际外观，例如显微照片中的实际外观可能看上去有所不同。而且，这些附图可能仅示出有助于理解图示的实施例的结构。本领域中公知的附加结构可能未包含以便保持附图的简明。例如，并非半导体装置的每一层都一定被示出。对“一实施例”、“多种实施例”等的引述指示，如此描述的实施例可能包括特定特征、结构或特点，但是不是每个实施例都必需地包括这些特定特征、结构或特点。一些实施例可以具有针对其他实施例描述的特征的其中一些、全部或完全不具有针对其他实施例描述的特征。“第一”、“第二”、“第三”等描述共有对象并且指示正在引述相似对象的不同实例。此类形容词不暗示如此描述的对象必须在时间上、空间上、评级上或任何其他方式上为给定顺序的。“连接”可以指示元件彼此直接物理或电接触，以及“耦合”可以指示元件彼此协同工作或交互，但是它们可能处于直接物理或电接触或可能未处于直接物理接触或电接触。再有，虽然不同附图中可能使用相似或相同编号来表示相同或相似的部件，但是这样不意味着包括相似或相同编号的所有附图构成单个或相同的实施例。
一实施例包括在非常细间距厚金属RDL线的一个或多个边缘上制造一个或多个保护侧壁。侧壁膜中包含的保护侧壁保护非常细间距厚金属线侧免于“半加成”工序流中进行的种子层蚀刻工序步骤期间的化学侵蚀。这样免除或大大地减少种子层蚀刻期间化学侵蚀所导致线宽损耗。这极大地有益于非常细间距的再分布线加工，其中当再分布线在宽度上小于4.0um时，种子层蚀刻期间的约0.5um的线宽损耗构成总线宽的大比例。因此，一实施例包括在非常细间距金属线的侧壁上制造保护膜，这阻止了种子层蚀刻工序期间的线宽损耗。
图1包括具有图案化RDL线的半导体装置。图案化铜（Cu）RDL层形成RDL线105。RDL线105在RDLCu种子层106、RDL阻挡层107、钝化层（例如，氮化物）108、镶嵌互连堆栈109中的最后金属层以及衬底110上形成。阻挡层可以排列装置的部分以便阻止成品装置工作期间来自金属线的离子迁移。例如，在金属线将是铜的情况下，阻挡层可以包含钽（Ta）。
图1的装置是通过“半加成”工序形成的。在“半加成”工序中，非图案化RDL具有薄种子层（例如，Cu）。然后敷设反掩膜，其暴露RDL种子层中将最终成为RDL线的部分。然后将附加的Cu添加到种子层在未被掩罩区域中以形成RDL线。剥离掩膜，以及蚀刻会移除现在暴露裸露的原种子Cu，从而将个体RDL线/迹线隔离。
为了确保多种材料之间的充分粘合，最初可以沉积种子层。种子层一般包含用于形成金属线的相同金属。作为备选，可以使用金属合金来形成种子层。种子层一般非常薄。例如，种子层可以在厚度上介于约10埃与约3000埃之间。通过比较，要形成的完整金属线可以填充光刻胶槽（未示出且已被图1中所示工序点移除），并且可以在高度上介于约0.5微米与约20微米之间以及可以在宽度上介于约0.25微米与约7微米之间。可以通过例如原子层沉积（ALD）或物理蒸镀沉积（PVD）来沉积种子层。以此方式，形成薄且均匀的种子层，附着于定义光刻胶槽的硅或其他材料。此外，种子层可以包含与RDL线的材料相似的材料。例如，种子层和金属线可以都包含铜。因此，形成金属线其他部分的材料与沉积于其上的种子层充分地相容且与之附着。种子层由此用作衬底或阻挡层的材料与金属线之间的附着界面。
图2包括图1的图案化RDL线路的物理简化版本。确切地来说，利用铜种子层106蚀刻，接着阻挡层107蚀刻来加工图1的装置。在铜种子层蚀刻步骤期间，厚金属RDL线的高度和宽度缩减，正如图示RDL线之一的原尺寸的点划线轮廓111所见。
图3包括本发明实施例中包含图案化RDL的半导体装置。与图1的情况一样，图3包括具有图案化RDL线的半导体装置。图案化铜（Cu）RDL层形成RDL线305。RDL线305在RDLCu种子层306、RDL阻挡层307、钝化层（例如，氮化物）308、镶嵌互连堆栈309中的最后金属层以及衬底310上形成。图3的装置是通过“半加成”工序形成的。
图4包括在RDL侧壁保护层沉积（又参见图8中方法800的框801）之后的包含图案化RDL的半导体装置。例如，该方法的实施例开始于已加工到形成图案化铜厚金属再分布线但是尚未执行铜种子层蚀刻的点的晶圆。然后，如图4中所见，在整个晶圆表面上方沉积侧壁保护膜304。
在一实施例中，该膜包含氮化硅，但是如碳化硅、氧化硅、氧氮化硅和多种聚合物的其他材料也是适合的且在多种其他实施例中被包含。
图5包括本发明实施例中在RDL侧壁保护层蚀刻（又参见图8中框802）之后的包含图案化RDL的半导体装置。例如，使用各向异性等离子体蚀刻工序从水平表面移除侧壁保护膜304，同时保持RDL305的垂直表面被覆盖。以此方式，介于铜厚金属RDL线（这些铜厚金属RDL线仅其中之一枚举为线305）中间的铜种子层306变为暴露，同时厚金属RDL线的侧壁仍被覆盖。
图6包括本发明实施例中在种子层蚀刻（又参见图8中框803）之后的包含图案化RDL的半导体装置。例如，使用各向同性湿法蚀刻工序来将铜厚金属RDL线中间的铜种子层306蚀刻掉。因为RDL线覆盖有侧壁保护膜304，所以不会（或非常少地）发生RDL侧壁的蚀刻，并且因此图6的铜种子蚀刻工序期间少到没有线宽损耗。适合的铜湿法蚀刻剂包含，例如基于氯化铁的蚀刻剂和硫酸/过氧化氢混合物。
图7包括本发明实施例中在阻挡层蚀刻（又参见图8中框804）之后的包含图案化RDL的半导体装置。例如，使用湿法化学或等离子蚀刻工序来蚀刻阻挡层膜307。在一个实施例中，阻挡层307包含钛（Ti），但是在其他实施例中，其他适合的阻挡膜包含钽（Ta）、铬（Cr）等。图7示出结构，其中保护侧壁膜304位于细间距厚金属RDL线305的侧边以保护该侧壁免于铜种子层蚀刻工序期间的化学侵蚀。
RDL线305具有RDL线宽311，RDL线宽311正交于RDL侧壁304'、304"且在RDL侧壁304'、304"之间延伸。种子层306和阻挡层307各包括与RDL线宽311平行且比RDL线宽311更宽的宽度。种子层306包括垂直地与保护侧壁304'、304"的最低边缘对齐的边缘。阻挡层307包括垂直地与种子层306的边缘以及保护侧壁304'、304"的最低边缘对齐的边缘。
在图7中，包括在与RDL线305相同的RDL中的附加图案化RDL线325具有附加RDL侧壁和直接接触附加RDL侧壁的附加保护侧壁324'、324"。再者，附加种子层326包含与RDL线325相同的材料，且与种子层306同平面。再者，附加阻挡层327与阻挡层307同平面。附加RDL线具有附加RDL线宽，以及附加种子层和阻挡层各包括与附加RDL线宽平行且比附加RDL线宽更宽的宽度。例如，种子层326和阻挡层327可以延伸到保护侧壁324'、324"的外边缘。
在一实施例中，RDL线305、325的图示部分之间没有介电材料和没有其他图案化RDL线。这可以与双镶嵌工序相对照。因此，线305、325之间可能有空的空隙331。空隙331被连接（出于说明目的）RDL线305、325的轴线330横切。在一实施例中，空隙330不包含介电材料。因此，在不包含甚至与线的顶部同平面的任何电介质的情况下，RDL线305、325可以形成装置的外缘或外周。
如图7所示，种子层306、326不直接彼此接触，以及阻挡层307、327不直接彼此接触。在一实施例中，RDL线宽311小于5微米，但是在其他实施例中，它小于7、6、4、3或2微米。
本文中有时可能将RDL线称为RDL层。但是，这样仅表示由单个层形成多个RDL线。在图案化之后，RDL层可以包含多个RDL线。
如图7的实施例的实施例能够实现间距低于4um线/空间（L/S）的非常细间距厚金属线的低成本制造。这提供优于镶嵌型工序流程的优点，镶嵌型工序流程可能需要铜和阻挡层化学机械抛光/平面化（CMP）步骤，化学机械抛光/平面化（CMP）步骤远较本文描述的“半加成”工序成本高昂。
现在参考图9，其中示出根据本发明实施例的系统实施例1000的框图。示出的还有多处理器系统1000，其包括第一处理元件1070和第二处理元件1080。虽然示出有两个处理元件1070和1080，但是要理解，系统1000的实施例还可以包含仅一个此类处理元件。系统1000图示为点到点互连系统，其中第一处理元件1070和第二处理元件1080通过点到点互连1050耦合。应该理解，图示的任何或所有互连可以实现为多点分支（multi-drop）总线，而非点到点互连。如图所示，处理元件1070和1080的每个处理元件都可以是多核处理器，包括第一和第二处理器核（即处理器核1074a和1074b和处理器核1084a和1084b）。此类核1074、1074b、1084a、1084b可以配置成以与本文论述的方法类似的方式执行指令代码。
每个处理元件1070、1080可以包括至少一个共享的高速缓存。该共享的高速缓存可以存储分别被处理器的一个或多个组件、如核1074a、1074b和1084a、1084b的利用的数据（例如，指令）。例如，该共享的高速缓存可以在本地缓存在存储器1032、1034中存储的数据以便更快速地被处理器的组件访问。在一个或多个实施例中，该高速缓存可以包括一个或多个中间级高速缓存（例如2级（L2）、3级（L3）、4级（L4）或其他级的高速缓存）、末级高速缓存（LLC）和/或它们的组合。
虽然仅示出有两个处理元件1070、1080，但是要理解，本发明的范围不限于此。在其他实施例中，给定处理器中可以存在一个或多个附加处理元件。作为备选，处理元件1070、1080的其中一个或多个可以是处理器以外的元件，如加速器或场可编程门阵列。例如，附加处理元件可以包括与第一处理器1070系统相同的附加处理器、与第一处理器1070异构的或不对称的附加处理器、加速器（例如，图形加速器或数字信号处理器（DSP）单元）、场可编程门阵列或任何其他处理元件。就包括体系结构、微体系结构、热、功耗特征等的频谱效用而言，处理元件1070、1080之间可能存在多种差异。这些差异实际可以证明自身为处理元件1070、1080之间的非对称性和异构性。对于至少一个实施例，多种处理元件1070、1080可以驻留在相同的晶片封装中。
第一处理元件1070还可以包括存储器控制器逻辑（MC）1072和点到点（P-P）接口1076和1078。相似地，第二处理元件1080可以包括MC1082和P-P接口1086和1088。MC1072和1082将这些处理器耦合到相应的存储器，即存储器1032和存储器1034，存储器1032和存储器1034可以是本地连接到相应处理器的主存储器的一部分。虽然MC逻辑1072和1082图示为集成到处理元件1070、1080中，但是对于备选实施例，MC逻辑可以是处理元件1070、1080外的分设元件，而非集成于其中。
可以分别经由P-P互连1076、1086经由P-P互连1062、10104将第一处理元件1070和第二处理元件1080耦合到I/O子系统1090。如图所示，I/O子系统1090包括P-P接口1094和1098。再者，I/O子系统1090还包括将I/O子系统1090与高性能图形引擎1038耦合的接口1092。在一个实施例中，可以使用总线将图形引擎1038耦合到I/O子系统1090。作为备选，点到点互连1039可以耦合这些组件。
然后，可以经由接口1096将I/O子系统1090耦合到第一总线10110。在一个实施例中，第一总线10110可以是外设互连（PCI）总线或诸如PCIExpress总线的总线或另一种第三代I/O互连总线，虽然本发明的范围并不局限于此。
如图所示，可以将多种I/O装置1014、1024连同将第一总线10110耦合到第二总线1020的总线桥1018耦合到第一总线10110。在一个实施例中，第二总线1020可以是低针脚计数（LPC）总线。可以将多种装置耦合到第二总线1020，在一个实施例中，这些装置诸如键盘/鼠标1022、通信装置1026（通信装置1026然后可以与计算机网络连接）和可以包含代码1028的数据存储单元1030（如磁盘驱动器或其他海量存储装置）。代码1030可以包括用于执行上文描述的一个或多个方法的实施例的指令。而且，还可以将音频I/O1024耦合到第二总线1020。
系统1000的多种组件，如组件1070、1080、1032、1034、1038、1090可以包含本文描述的RDL线。
注意还可设想其他实施例。例如，对于所示的点到点体系结构，代之以系统可以实现多点分支总线或另一种此类通信拓扑。作为备选，附图的元件还可以使用比附图所示更多或更少的集成芯片来划分。
示例1包括一种半导体装置，其包括：再分布层（RDL），所述再分布层（RDL）包括具有两个RDL侧壁的图案化RDL线，所述RDL包含一种材料；直接接触所述两个RDL侧壁的保护侧壁；包含所述材料的种子层；以及阻挡层；其中（a）所述RDL线具有正交于所述两个RDL侧壁且在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层和阻挡层各包括与所述RDL线宽平行且比所述RDL线宽更宽的宽度。
在一实施例中，所述材料选自包括Cu和Au的组。虽然一些实施例包含Cu或Au用于RDL线，但是其他实施例不限于此，并且可以包含未专门提及的其他金属和/或合金。在一实施例中，所述侧壁垂直且正交于衬底所在的水平面。这些保护侧壁可以“直接地接触”所述两个RDL侧壁，而不管在形成所述保护侧壁时所述RDL侧壁存在某种程度的氧化或污染。这对于本文中涉及“直接接触”的其他区域也是成立的。再者，所述种子层可以包含与所述RDL线相同的材料，而不管是以与所述RDL线不同的方式实施的（例如，所述种子层可以是用于所述RDL线的材料的合金以及反之亦然，所述种子层可以包含与所述RDL线不同的材料比例（虽然材料相同）等）。在一个实施例中，所述RDL线包含着陆盘（landingpad）。整个RDL线可以构成着陆盘（例如，对于短RDL线而言）或所述RDL的仅一部分可以构成着陆盘（例如，对于长RDL线而言）。
在示例2中，示例1的主题可以可选地包括，其中所述种子层包括垂直地与所述保护侧壁之一的边缘对齐的边缘。
在示例3中，示例1-2中的主题可以可选地包括，其中所述阻挡层包括垂直地与所述种子层的边缘对齐的边缘。
在示例4中，示例1-3中的主题可以可选地包括，其中所述RDL耦合到硅通孔（TSV）。
在示例5中，示例1-4中的主题可以可选地包括附加图案化RDL线，所述附加图案化RDL线包含在所述RDL中，且具有两个附加RDL侧壁，直接接触所述两个附加RDL侧壁的附加保护侧壁；包含所述材料和所述种子层同平面的附加种子层；与所述阻挡层同平面的附加阻挡层；其中（a）所述附加RDL具有正交于所述两个附加RDL侧壁且在所述两个附加RDL侧壁之间延伸的附加RDL线宽，以及（b）所述附加种子层和阻挡层各包括与所述附加RDL线宽平行且比所述附加RDL线宽更宽的宽度。
在示例6中，示例1-5中的主题可以可选地包括，其中所述图案化RDL线的一部分与所述附加图案化RDL线的附加部分之间不存在介电材料和不存在其他图案化RDL线。
在示例7中，示例1-6中的主题可以可选地包括，其中种子层不直接接触所述附加种子层。
在示例8中，示例1-7中的主题可以可选地包括，其中阻挡层不直接接触所述附加阻挡层。
在示例9中，示例1-8中的主题可以可选地包括所述图案化RDL线与所述附加图案化RDL线之间的空的空隙，其中所述空的空隙被连接所述图案化RDL线与所述附加图案化RDL线的轴线横切。
在示例10中，示例1-9中的主题可以可选地包括，其中所述空的空隙不包含介电材料。
在示例11中，示例1-10中的主题可以可选地包括，其中所述RDL线宽小于5微米。
在示例12中，示例1-11中的主题可以可选地包括，其中所述阻挡层包含选自包括Ti、Ta和Cr的组的至少一种材料，以及所述保护侧壁包含选自包括氮化硅、碳化硅、氧化硅和氮氧化硅的组的至少一种材料。
在示例13中，示例1-12中的主题可以可选地包括，其中所述阻挡层不直接接触所述两个RDL侧壁。
在示例14中，示例1-13中的主题可以可选地包括，其中所述种子层直接接触所述阻挡层、所述保护侧壁以及所述图案化两个RDL线。
在示例15中，示例1-14中的主题可以可选地包括，其中所述保护侧壁不直接接触所述两个RDL侧壁的最上方部分。
因此，图5示出侧壁不直接接触所述两个RDL侧壁的最上方部分，但是，在一实施例中，在种子层蚀刻（其也蚀刻RDL线）（参见图6）期间解决了此接触的缺失。但是，在其他实施例中，所述保护侧壁顶部与所述RDL线侧壁顶部之间保持这种间隙。
示例16包括一种半导体装置，其包括：再分布（RDL）线，所述再分布（RDL）线具有RDL侧壁；直接接触所述RDL侧壁的保护侧壁；包含所述材料且直接接触所述RDL线的种子层；其中（a）所述RDL线具有在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层包括比所述RDL线宽更宽的宽度。
因此，一些实施例可以包括阻挡层，但是此类层并非在所有实施例中都是绝对必需的。
在示例17中，示例16的主题可以可选地包括，其中所述种子层包括垂直地与所述保护侧壁之一的边缘对齐的边缘。
在示例18中，示例16-17中的主题可以可选地包括附加RDL线，所述附加RDL线直接接触与所述种子层同平面的附加种子层；其中所述种子层不直接接触所述附加种子层。
在示例19中，示例16-18中的主题可以可选地包括空的空隙，所述空的空隙被连接所述RDL线与所述附加RDL线的轴线横切。
在示例20中，示例16-19中的主题可以可选地包括，其中所述RDL线宽小于5微米。
示例21包括一种半导体加工方法，其包括：形成再分布（RDL）线，所述再分布（RDL）线具有RDL侧壁；形成直接接触所述RDL侧壁的保护侧壁；形成包含所述材料且直接接触所述RDL线的种子层；其中（a）所述RDL线具有在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层包括比所述RDL线宽更宽的宽度。
在示例22中，示例21中的主题可以可选地包括，形成所述种子层的边缘，所述种子层的边缘在垂直地与所述保护侧壁之一的边缘对齐。
在示例23中，示例21-22中的主题可以可选地包括形成附加RDL线，所述附加RDL线直接接触与所述种子层同平面的附加种子层；其中所述种子层不直接接触所述附加种子层；以及形成空的空隙，所述空的空隙被连接所述RDL线与所述附加RDL线的轴线横切。
在示例24中，示例21-23中的主题可以可选地包括，其中所述RDL线宽小于5微米。
前文对本发明的实施例的描述是出于说明和描述的目的而给出的。不应是穷举的或将本发明限于所公开的具体形式。此描述中以及所附权利要求包含多个术语，如左边、右边、顶部、底部、上面、下面、上方、下方、第一、第二等，这些术语进行用于描述性目的而不视为限制。例如，指示相对垂直位置的术语是指衬底或集成电路的装置侧（或活性表面）是衬底的“顶部”表面；衬底实际可以位于任何朝向，从而衬底的“顶部”一侧可能在标准地面参考框架中低于“底部”一侧，而且仍落在术语“顶部”的含义内。正如本文中（包括在权利要求中）所使用的，术语“在…上”不指示在第二层“上”的第一层直接在第二层上且与之直接接触，除非明确地如此陈述；在第一层与第一层上的第二层之间可能存在第三层或其他结构。本文描述的装置或产品的实施例可以按多种位置和朝向来制造、使用或发货。相关领域的技术人员能够根据上文教导认识到多种修改和变化是可能的。本领域技术人员将认识到对于附图所示的多种组件的多种等效组合和替代。因此，本发明的范围理应不限于此类详细描述，而仅限于所附权利要求。
虽然本发明是结合有限数量的实施例来描述的，但是本领域技术人员将设想到基于此的多种修改和变化。所附权利要求理应涵盖所在本发明的真实精神和范围内的所有此类修改和变化。

Claims (24)

1.一种半导体装置，其包括：
再分布层（RDL），所述再分布层（RDL）包括具有两个RDL侧壁的图案化RDL线，所述RDL包含材料；
直接接触所述两个RDL侧壁的保护侧壁；
包含所述材料的种子层；以及
阻挡层；
其中（a）所述RDL线具有与所述两个RDL侧壁正交且在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层和阻挡层各包括与所述RDL线宽平行且比所述RDL线宽更宽的宽度。
2.如权利要求1所述的装置，其中所述种子层包括垂直地与所述保护侧壁之一的边缘对齐的边缘。
3.如权利要求2所述的装置，其中所述阻挡层包括垂直地与所述种子层的边缘对齐的边缘。
4.如权利要求1所述的装置，其中所述RDL耦合到硅通孔（TSV）。
5.如权利要求1所述的装置，其包括：
包含在所述RDL中的附加图案化RDL线，所述附加图案化RDL线具有两个附加RDL侧壁；
直接接触所述两个附加RDL侧壁的附加保护侧壁；
包含所述材料并和所述种子层同平面的附加种子层；以及
与所述阻挡层同平面的附加阻挡层；
其中（a）所述附加RDL具有正交于所述两个附加RDL侧壁且在所述两个附加RDL侧壁之间延伸的附加RDL线宽，以及（b）所述附加种子层和阻挡层各包括与所述附加RDL线宽平行且比所述附加RDL线宽更宽的宽度。
6.如权利要求5所述的装置，其中所述图案化RDL线的一部分与所述附加图案化RDL线的附加部分之间不存在介电材料和不存在其他图案化RDL线。
7.如权利要求5所述的装置，其中所述种子层不直接接触所述附加种子层，以及所述阻挡层不直接接触所述附加阻挡层。
8.如权利要求7所述的装置，其包括：所述图案化RDL线与所述附加图案化RDL线之间的空的空隙，其中所述空的空隙被连接所述图案化RDL线与所述附加图案化RDL线的轴线横切。
9.如权利要求1所述的装置，其中所述材料选自包括Cu和Au的组。
10.如权利要求9所述的装置，其中所述空的空隙不包含介电材料。
11.如权利要求1所述的装置，其中所述RDL线宽小于5微米。
12.如权利要求11所述的装置，其中所述阻挡层包含选自包括Ti、Ta和Cr的组的至少一种材料，以及所述保护侧壁包含选自包括氮化硅、碳化硅、氧化硅和氮氧化硅的组的至少一种材料。
13.如权利要求1所述的装置，其中所述阻挡层不直接接触所述两个RDL侧壁。
14.如权利要求13所述的装置，其中所述种子层直接接触所述阻挡层、所述保护侧壁以及所述图案化RDL线。
15.如权利要求1所述的装置，其中所述保护侧壁不直接接触所述两个RDL侧壁的最上方部分。
16.一种半导体装置，其包括：
再分布层（RDL）线，所述再分布层线具有RDL侧壁；
直接接触所述RDL侧壁的保护侧壁；以及
直接接触所述RDL线的种子层；
其中（a）所述RDL线具有在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层包括比所述RDL线宽更宽的宽度。
17.如权利要求16所述的装置，其中所述种子层包括垂直地与所述保护侧壁之一的边缘对齐的边缘。
18.如权利要求16所述的装置，其包括直接接触与所述种子层同平面的附加种子层的附加RDL线；其中所述种子层不直接接触所述附加种子层。
19.如权利要求18所述的装置，其包括空的空隙，所述空的空隙被连接所述RDL线与所述附加RDL线的轴线横切。
20.如权利要求16所述的装置，其中所述RDL线宽小于5微米。
21.一种半导体加工方法，其包括：
形成再分布（RDL）线，所述再分布（RDL）线具有RDL侧壁；
形成直接接触所述RDL侧壁的保护侧壁；
形成直接接触所述RDL线的种子层；
其中（a）所述RDL线具有在所述两个RDL侧壁之间延伸的RDL线宽，以及（b）所述种子层包括比所述RDL线宽更宽的宽度。
22.如权利要求21所述的方法，包括形成所述种子层的边缘，所述边缘在垂直地与所述保护侧壁之一的边缘对齐。
23.如权利要求21所述的方法，其包括：
形成直接接触与所述种子层同平面的附加种子层的附加RDL线；其中种子层不直接接触所述附加种子层；以及
形成空的空隙，所述空的空隙被连接所述RDL线与所述附加RDL线的轴线横切。
24.如权利要求21所述的方法，其中所述RDL线宽小于5微米。
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