CN105814551B - 用于控制电路输入输出时序的方法和系统 - Google Patents

用于控制电路输入输出时序的方法和系统 Download PDF

Info

Publication number
CN105814551B
CN105814551B CN201480065422.5A CN201480065422A CN105814551B CN 105814551 B CN105814551 B CN 105814551B CN 201480065422 A CN201480065422 A CN 201480065422A CN 105814551 B CN105814551 B CN 105814551B
Authority
CN
China
Prior art keywords
delay
value
fine
coarse
propagation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480065422.5A
Other languages
English (en)
Chinese (zh)
Other versions
CN105814551A (zh
Inventor
A·蒂瓦里
I·K·达姆
P·穆尔蒂
V·B·班赛尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN105814551A publication Critical patent/CN105814551A/zh
Application granted granted Critical
Publication of CN105814551B publication Critical patent/CN105814551B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN201480065422.5A 2013-10-08 2014-09-29 用于控制电路输入输出时序的方法和系统 Active CN105814551B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/048,238 US9024670B2 (en) 2013-10-08 2013-10-08 System and method for controlling circuit input-output timing
US14/048,238 2013-10-08
PCT/US2014/057974 WO2015053968A1 (en) 2013-10-08 2014-09-29 Method and system for controlling circuit input-output timing

Publications (2)

Publication Number Publication Date
CN105814551A CN105814551A (zh) 2016-07-27
CN105814551B true CN105814551B (zh) 2019-08-30

Family

ID=52776465

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480065422.5A Active CN105814551B (zh) 2013-10-08 2014-09-29 用于控制电路输入输出时序的方法和系统

Country Status (5)

Country Link
US (1) US9024670B2 (enExample)
EP (1) EP3055781A4 (enExample)
JP (1) JP6673823B2 (enExample)
CN (1) CN105814551B (enExample)
WO (1) WO2015053968A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6784259B2 (ja) * 2015-09-02 2020-11-11 日本電気株式会社 プログラマブル論理集積回路と半導体装置およびキャラクタライズ方法
CN105429613B (zh) * 2015-10-28 2018-09-11 北京农业智能装备技术研究中心 一种同步多路脉冲产生系统及方法
CN108228919A (zh) * 2016-12-09 2018-06-29 厦门紫光展锐科技有限公司 一种集成电路接口的时序生成方法及装置
US10587253B1 (en) 2018-11-29 2020-03-10 Qualcomm Incorporated Ring oscillator-based programmable delay line
CN111221752B (zh) * 2020-01-02 2021-07-23 飞腾信息技术有限公司 一种soc中模块接口时序的优化方法
US11474964B2 (en) * 2020-10-28 2022-10-18 Moxa Inc. Configurable input/output device and operation method thereof
US11835580B2 (en) * 2020-12-01 2023-12-05 Mediatek Singapore Pte. Ltd. Circuit and method to measure simulation to silicon timing correlation
CN115906729B (zh) * 2021-08-19 2025-12-19 华润微集成电路(无锡)有限公司 针对存储器异步接口实现预定时序控制电路设计的方法
CN118282372B (zh) * 2024-06-03 2024-08-09 上海泰矽微电子有限公司 一种多开关控制电路及芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US20030106361A1 (en) * 2001-12-12 2003-06-12 Greidanus Henry Steven System and method for calibrating an adjustable delay time for a delay module
US20040155690A1 (en) * 2003-02-11 2004-08-12 Lattice Semiconductor Corporation Adaptive input logic for phase adjustments
CN100336302C (zh) * 2003-12-17 2007-09-05 精工爱普生株式会社 延迟调整电路、集成电路装置以及延迟调整方法
CN203340049U (zh) * 2011-04-01 2013-12-11 英特尔公司 具有细粒度和粗粒度延迟元件的数字控制延迟线和以细粒度增量进行调整的系统

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1124785A (ja) * 1997-07-04 1999-01-29 Hitachi Ltd 半導体集積回路装置と半導体メモリシステム
DE19845115C2 (de) * 1998-09-30 2000-08-31 Siemens Ag Integrierte Schaltung mit einer einstellbaren Verzögerungseinheit
US6445231B1 (en) 2000-06-01 2002-09-03 Micron Technology, Inc. Digital dual-loop DLL design using coarse and fine loops
US6727740B2 (en) * 2002-08-29 2004-04-27 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
US7042296B2 (en) * 2003-09-25 2006-05-09 Lsi Logic Corporation Digital programmable delay scheme to continuously calibrate and track delay over process, voltage and temperature
US7126399B1 (en) * 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
JP5377843B2 (ja) * 2007-09-13 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
KR101290764B1 (ko) * 2007-10-24 2013-07-30 삼성전자주식회사 고속동작에 적합한 입력 회로를 갖는 반도체 메모리 장치
US7639054B1 (en) * 2008-01-16 2009-12-29 Altera Corporation Techniques for generating programmable delays
JP5410075B2 (ja) * 2008-11-11 2014-02-05 ルネサスエレクトロニクス株式会社 半導体集積回路装置および遅延路の制御方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US20030106361A1 (en) * 2001-12-12 2003-06-12 Greidanus Henry Steven System and method for calibrating an adjustable delay time for a delay module
US20040155690A1 (en) * 2003-02-11 2004-08-12 Lattice Semiconductor Corporation Adaptive input logic for phase adjustments
CN100336302C (zh) * 2003-12-17 2007-09-05 精工爱普生株式会社 延迟调整电路、集成电路装置以及延迟调整方法
CN203340049U (zh) * 2011-04-01 2013-12-11 英特尔公司 具有细粒度和粗粒度延迟元件的数字控制延迟线和以细粒度增量进行调整的系统

Also Published As

Publication number Publication date
EP3055781A1 (en) 2016-08-17
US20150097608A1 (en) 2015-04-09
US9024670B2 (en) 2015-05-05
JP2016536865A (ja) 2016-11-24
WO2015053968A1 (en) 2015-04-16
EP3055781A4 (en) 2017-06-28
JP6673823B2 (ja) 2020-03-25
CN105814551A (zh) 2016-07-27

Similar Documents

Publication Publication Date Title
CN105814551B (zh) 用于控制电路输入输出时序的方法和系统
US6914492B2 (en) Digital programmable delay scheme with automatic calibration
US8779754B2 (en) Method and apparatus for minimizing skew between signals
CN107209225B (zh) 使用校准的单个时钟源同步串行器-解串器协议的高速数据传输
KR101423862B1 (ko) 동작 전압의 디바이스 특유적 구성
CN108432143A (zh) 基于时间的延迟线模/数转换器
US9251906B1 (en) Data strobe signal generation for flash memory
JPH06124137A (ja) クロックスキューを制御する方法及び装置
JP2017528838A (ja) トランスミッターのレーン間スキュー調整
US6876186B1 (en) Measurement of circuit delay
KR20200098635A (ko) 프로그래밍가능 제어 회로를 사용한 클록 신호들의 선택적 제공
JP2016536865A5 (enExample)
US7222036B1 (en) Method for providing PVT compensation
US11121707B2 (en) Programmable clock skewing for timing closure
CN108717401B (zh) 源同步系统的重新校准
CN106688182B (zh) 可编程延迟电路块
US9429625B1 (en) Analog signal test circuits and methods
US10291501B1 (en) Systems and methods for measuring latency of data buffers
US20080129357A1 (en) Adaptive Integrated Circuit Clock Skew Correction
JP6751442B2 (ja) プログラマブルロジックデバイス内のフットプリントを削減し、ファブリック多重度を向上させるシステムおよび方法
CN108074601B (zh) 具有输入电路的存储器装置以及存储器装置的操作方法
US9330217B2 (en) Holdtime correction using input/output block delay
JP7053204B2 (ja) 遅延時間測定装置、半導体装置及び遅延時間の測定方法
US7477712B2 (en) Adaptable data path for synchronous data transfer between clock domains
US11764763B1 (en) Method and apparatus for in-situ on-chip timing

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant