JP6673823B2 - 回路入出力タイミングを制御するための方法及びシステム - Google Patents

回路入出力タイミングを制御するための方法及びシステム Download PDF

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JP6673823B2
JP6673823B2 JP2016521783A JP2016521783A JP6673823B2 JP 6673823 B2 JP6673823 B2 JP 6673823B2 JP 2016521783 A JP2016521783 A JP 2016521783A JP 2016521783 A JP2016521783 A JP 2016521783A JP 6673823 B2 JP6673823 B2 JP 6673823B2
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delay
value
fine
coarse
elements
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JP2016536865A (ja
JP2016536865A5 (enExample
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ティワリ アシュトシュ
ティワリ アシュトシュ
クマール ダム イシュ
クマール ダム イシュ
マーシー プラナフ
マーシー プラナフ
ブリジラル バンサル ヴィレンドラ
ブリジラル バンサル ヴィレンドラ
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2016521783A 2013-10-08 2014-09-29 回路入出力タイミングを制御するための方法及びシステム Active JP6673823B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/048,238 2013-10-08
US14/048,238 US9024670B2 (en) 2013-10-08 2013-10-08 System and method for controlling circuit input-output timing
PCT/US2014/057974 WO2015053968A1 (en) 2013-10-08 2014-09-29 Method and system for controlling circuit input-output timing

Publications (3)

Publication Number Publication Date
JP2016536865A JP2016536865A (ja) 2016-11-24
JP2016536865A5 JP2016536865A5 (enExample) 2017-11-02
JP6673823B2 true JP6673823B2 (ja) 2020-03-25

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JP2016521783A Active JP6673823B2 (ja) 2013-10-08 2014-09-29 回路入出力タイミングを制御するための方法及びシステム

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US (1) US9024670B2 (enExample)
EP (1) EP3055781A4 (enExample)
JP (1) JP6673823B2 (enExample)
CN (1) CN105814551B (enExample)
WO (1) WO2015053968A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US10305485B2 (en) * 2015-09-02 2019-05-28 Nec Corporation Programmable logic integrated circuit, semiconductor device, and characterization method
CN105429613B (zh) * 2015-10-28 2018-09-11 北京农业智能装备技术研究中心 一种同步多路脉冲产生系统及方法
CN108228919A (zh) * 2016-12-09 2018-06-29 厦门紫光展锐科技有限公司 一种集成电路接口的时序生成方法及装置
US10587253B1 (en) 2018-11-29 2020-03-10 Qualcomm Incorporated Ring oscillator-based programmable delay line
CN111221752B (zh) * 2020-01-02 2021-07-23 飞腾信息技术有限公司 一种soc中模块接口时序的优化方法
US11474964B2 (en) * 2020-10-28 2022-10-18 Moxa Inc. Configurable input/output device and operation method thereof
US11835580B2 (en) * 2020-12-01 2023-12-05 Mediatek Singapore Pte. Ltd. Circuit and method to measure simulation to silicon timing correlation
CN118282372B (zh) * 2024-06-03 2024-08-09 上海泰矽微电子有限公司 一种多开关控制电路及芯片

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JPH1124785A (ja) * 1997-07-04 1999-01-29 Hitachi Ltd 半導体集積回路装置と半導体メモリシステム
DE19845115C2 (de) * 1998-09-30 2000-08-31 Siemens Ag Integrierte Schaltung mit einer einstellbaren Verzögerungseinheit
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US6445231B1 (en) * 2000-06-01 2002-09-03 Micron Technology, Inc. Digital dual-loop DLL design using coarse and fine loops
US7283917B2 (en) * 2001-12-12 2007-10-16 Alcatel Canada Inc. System and method for calibrating an adjustable delay time for a delay module
US6727740B2 (en) * 2002-08-29 2004-04-27 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
US7034596B2 (en) * 2003-02-11 2006-04-25 Lattice Semiconductor Corporation Adaptive input logic for phase adjustments
US7042296B2 (en) * 2003-09-25 2006-05-09 Lsi Logic Corporation Digital programmable delay scheme to continuously calibrate and track delay over process, voltage and temperature
JP2005184196A (ja) * 2003-12-17 2005-07-07 Seiko Epson Corp 遅延調整回路、集積回路装置、及び遅延調整方法
US7126399B1 (en) * 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
JP5377843B2 (ja) * 2007-09-13 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
KR101290764B1 (ko) * 2007-10-24 2013-07-30 삼성전자주식회사 고속동작에 적합한 입력 회로를 갖는 반도체 메모리 장치
US7639054B1 (en) * 2008-01-16 2009-12-29 Altera Corporation Techniques for generating programmable delays
JP5410075B2 (ja) * 2008-11-11 2014-02-05 ルネサスエレクトロニクス株式会社 半導体集積回路装置および遅延路の制御方法
US8564345B2 (en) 2011-04-01 2013-10-22 Intel Corporation Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments

Also Published As

Publication number Publication date
JP2016536865A (ja) 2016-11-24
US9024670B2 (en) 2015-05-05
CN105814551B (zh) 2019-08-30
CN105814551A (zh) 2016-07-27
EP3055781A1 (en) 2016-08-17
WO2015053968A1 (en) 2015-04-16
EP3055781A4 (en) 2017-06-28
US20150097608A1 (en) 2015-04-09

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