CN105789054B - Rfldmos制备方法及结构 - Google Patents

Rfldmos制备方法及结构 Download PDF

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CN105789054B
CN105789054B CN201610190736.9A CN201610190736A CN105789054B CN 105789054 B CN105789054 B CN 105789054B CN 201610190736 A CN201610190736 A CN 201610190736A CN 105789054 B CN105789054 B CN 105789054B
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遇寒
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

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Abstract

本发明公开了一种RFLDMOS制备方法,该方法通过三次离子注入形成漂移区,第一次离子注入覆盖整个漂移区,第二次离子注入从法拉第边缘到漏引出端,第三次离子注入从距离漏引出端0.1μm~0.3μm开始直到漏引出端。本发明还公开了用上述方法制备的RFLDMOS的结构。在该RFLDMOS结构中,自漏引出端至距离该漏引出端0.1μm~0.3μm的区域有一离子掺杂区。本发明通过在轻掺杂漏端进行三次阶梯形的离子(LDD)注入来调节漂移区电场分布,提高了器件的击穿电压和饱和电流,降低了漏端表面电场和导通电阻,提高了产品击穿电压稳定性及鲁棒性。

Description

RFLDMOS制备方法及结构
技术领域
本发明涉及集成电路制造领域,特别是涉及RFLDMOS的制备方法及结构。
背景技术
RFLDMOS(射频横向扩散金属氧化物半导体)器件是一种非常具有竞争力的功率器件,最初是用于替代基站的双极型晶体管。其具有线性度好、增益高、耐压高、输出功率大、热稳定性好、效率高、宽带匹配性能好、易于和MOS工艺集成等优点,并且价格远低于砷化镓器件。此外,该器件的射频应用覆盖了从1MHz到4GHz的广阔范围。正是由于这些优点,它被广泛用于GSM、PCS、W-CDMA基站的功率放大器,无线广播,工业,科学,医学(ISM)以及雷达等方面。
对工作电压为28~32V的器件来说,击穿电压是射频LDMOS器件可靠性的一个重要参数,它不仅决定了其输出功率,还决定了器件的耐压能力,因此必须要优化。由于工艺过程中,不可避免的会出现表面电荷,造成产品的不稳定,因此,为了保证器件运行时的可靠性,要求击穿电压必须高于65V。
发明内容
本发明要解决的技术问题之一是提供一种RFLDMOS制备方法,它可以提高器件击穿电压的稳定性。
为解决上述技术问题,本发明的RFLDMOS制备方法,通过三次离子注入形成漂移区,第一次离子注入覆盖整个漂移区,第二次离子注入从法拉第边缘到漏引出端,第三次离子注入从距离漏引出端0.1μm~0.3μm开始直到漏引出端。
第一次离子注入的剂量高于第二次离子注入的剂量,第一次离子注入的能量低于第二次离子注入的能量,第三次离子注入的剂量和第二次离子注入的剂量接近,第三次离子注入的能量低于第二次离子注入能量。三次离子注入的能量范围为100keV~250keV。
较佳的,第三次离子注入的剂量为5E11~1E12,能量为80Kev~100Kev。
本发明要解决的技术问题之二是提供用上述方法制备的RFLDMOS的结构。在该RFLDMOS结构中,自漏引出端至距离该漏引出端0.1μm~0.3μm的区域有一离子掺杂区。
本发明通过在轻掺杂漏端进行三次阶梯形的离子(LDD)注入来调节漂移区电场分布,提高了器件的击穿电压和饱和电流,降低了漏端表面电场和导通电阻,提高了产品击穿电压稳定性及鲁棒性。在静态电流偏置下,靠近栅极的电场强度不变,HCI特性不受影响。
附图说明
图1是传统RFLDMOS的结构示意图。
图2是本发明实施例的RFLDMOS结构示意图。
图3是击穿电压条件下,RFLDMOS的传统结构与本发明实施例的结构的表面电场分布图。
图4是本发明实施例的RFLDMOS在HCI条件下的表面电场分布图。
图5是本发明实施例的RFLDMOS在HCI条件下的栅极边缘横向电场。
图6是本发明实施例的RFLDMOS的BV稳定性。
图7是本发明实施例的RFLDMOS的HCI结果。
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解,现结合图示的实施方式,详述如下:
本实施例的RFLDMOS制备工艺步骤如下:
步骤1,在P型衬底生长P型外延。
步骤2,炉管生长栅氧化层及多晶硅。
步骤3,光刻胶定义出栅极,干法刻蚀,形成栅极区,进行三次N型离子注入,形成RFLDMOSN型漂移区。
其中,第一次N型离子注入(NLDD1)覆盖整个漂移区,第二次N型离子注入(NLDD2)从法拉第边缘到高掺杂的漏引出端,第三次N型离子注入(NLDD3)从距离高掺杂的漏引出端0.1μm~0.3μm开始直到漏引出端。NLDD1的剂量比NLDD2的剂量高,NLDD1的能量比NLDD2的能量低;NLDD3的剂量和NLDD2的剂量接近,NLDD3的能量低于NLDD2的能量。三次离子注入能量的范围可以从100keV到250keV。在本实施例中,NLDD3的剂量为5E11~1E12,能量为80Kev~100Kev。
步骤4,光刻胶定义出P型沟道区,通过50keV左右能量和1E12~1E13剂量离子注入形成P型沟道,通过快速热退火或者炉管做推进。
步骤5,用光刻胶定义出N型重掺杂源/漏区和P型体区,分别进行N型和P型离子注入。
步骤6,在源漏端及多晶硅上形成约左右的钛金属硅化物。
步骤7,进行后续接触孔、金属工艺等,完成LDMOS基本结构。
如图3所示,增加了第三次N型离子注入(NLDD3)后,漏端电场明显下降,从而有效地提高了产品鲁棒性和击穿电压稳定性。但是随着NLDD3剂量和能量的增加,漏端电场会增加,此时需要降低导通电阻,保持与击穿电压、鲁棒性之间的平衡。
如图4、5所示,增加了NLDD3后,只要合理设置NLDD3的剂量(5E11~1E12)和能量(80Kev~100Kev),多晶硅边缘电场将不会增加,也就不会影响HCI(hot carrierinjection,热载流子注入),但是随着NLDD3剂量和能量增加,栅极边缘电场增加,可能导致HCI变差,此时需要优化NLDD3剂量。
如图6所示,只要NLDD3能量和剂量优化合理,可以得到更加稳定的击穿电压,鲁棒性也能得到提高。
如图7所示,只要NLDD3能量和剂量优化合理,HCI可以通过。

Claims (5)

1.RFLDMOS制备方法,其特征在于,通过三次相同类型离子注入形成漂移区,第一次离子注入覆盖整个漂移区,第二次离子注入从法拉第边缘到漏引出端,第三次离子注入从距离漏引出端0.1μm~0.3μm开始直到漏引出端,且漏引出端与第三次离子注入为相同杂质类型掺杂。
2.根据权利要求1所述的方法,其特征在于,第一次离子注入的剂量高于第二次离子注入的剂量,第一次离子注入的能量低于第二次离子注入的能量,第三次离子注入的剂量和第二次离子注入的剂量接近,第三次离子注入的能量低于第二次离子注入的能量。
3.根据权利要求2所述的方法,其特征在于,三次离子注入的能量范围为100keV~250keV。
4.根据权利要求1所述的方法,其特征在于,第三次离子注入的剂量为5E11~1E12,能量为80Kev~100Kev。
5.RFLDMOS的结构,其特征在于:该RFLDMOS结构包括第一离子掺杂区、第二离子掺杂区及第三离子掺杂区,其中第一离子掺杂区覆盖整个漂移区,第二离子掺杂区从法拉第边缘到漏引出端,第三离子掺杂区自漏引出端至距离该漏引出端0.1μm~0.3μm的区域,且第一离子掺杂区、第二离子掺杂区及第三离子掺杂区为相同杂质类型掺杂,漏引出端与第三离子掺杂区为相同杂质类型掺杂。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506648B1 (en) * 1998-09-02 2003-01-14 Cree Microwave, Inc. Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure
CN104409500A (zh) * 2014-11-11 2015-03-11 上海华虹宏力半导体制造有限公司 射频ldmos及其制作方法
CN104538441A (zh) * 2014-07-03 2015-04-22 上海华虹宏力半导体制造有限公司 射频ldmos器件及其制造方法
CN104638003A (zh) * 2013-11-14 2015-05-20 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506648B1 (en) * 1998-09-02 2003-01-14 Cree Microwave, Inc. Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure
CN104638003A (zh) * 2013-11-14 2015-05-20 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法
CN104538441A (zh) * 2014-07-03 2015-04-22 上海华虹宏力半导体制造有限公司 射频ldmos器件及其制造方法
CN104409500A (zh) * 2014-11-11 2015-03-11 上海华虹宏力半导体制造有限公司 射频ldmos及其制作方法

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