CN105659384A - 晶体管阵列布线 - Google Patents

晶体管阵列布线 Download PDF

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CN105659384A
CN105659384A CN201480055851.4A CN201480055851A CN105659384A CN 105659384 A CN105659384 A CN 105659384A CN 201480055851 A CN201480055851 A CN 201480055851A CN 105659384 A CN105659384 A CN 105659384A
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S·里德尔
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Not Rec Yin Ai Greensboro Co Ltd
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    • H—ELECTRICITY
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    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract

一种包含晶体管阵列的装置，其中该装置包括：在第一层级的第一导体层，第一导体层限定了为所述晶体管阵列提供源电极或栅电极中的一个的多个第一导体；在第二层级的第二导体层，第二导体层限定了为所述晶体管阵列提供源电极或栅电极中的另一个的多个第二导体；其中该第二导体层还限定了在所述第二导体之间的一个或多个位置处的布线导体，每个布线导体通过一个或多个层间导电连接连接到相应的第一导体。

Description

晶体管阵列布线
晶体管阵列典型地包括为晶体管提供源电极的源极导体阵列、为晶体管提供漏电极的漏极导体阵列和为晶体管提供栅电极的栅极导体阵列。
一种用于连接该源极导体和栅极导体至一个或多个驱动器芯片的相应输出端子的技术涉及在该阵列的一个边缘终止该源极导体以及在该阵列的另一个边缘终止该栅极导体，以及(a)在该阵列的相应边缘提供分开的源极驱动器芯片和栅极驱动器芯片，或者在该阵列的共用边缘提供源极和栅极驱动器芯片并且提供围绕该阵列的两个边缘延伸至栅极或源极的导电轨，该栅极导体或源极导体终止于与该驱动器芯片所位于的边缘不同的该阵列的边缘。
本申请的发明人已认识到以下挑战：改进源极/栅极导体至一个或多个驱动器芯片的布线(routing)。
在此提供一种包含晶体管阵列的装置，其中该装置包括：在第一层级的第一导体层，其限定了为所述晶体管阵列提供源电极或栅电极中的一个的多个第一导体；在第二层级的第二导体层，其限定了为所述晶体管阵列提供源电极或栅电极中的另一个的多个第二导体；其中所述第二导体层还限定了在所述第二导体之间的一个或多个位置处的布线导体，每个布线导体通过一个或多个层间导电连接连接到相应的第一导体。
根据一个实施例，第一导体为该晶体管阵列提供源电极，且第二导体为该晶体管阵列提供栅电极。
根据一个实施例，每个第一导体与该晶体管阵列的相应的一个或多个列相关联，且每个第二导体与该晶体管阵列的相应的一个或多个行相关联。
根据一个实施例，第一导体为该晶体管阵列提供栅电极，而第二导体为该晶体管阵列提供源电极。
根据一个实施例，所述第二导体和所述布线导体终止于该晶体管阵列的共用侧。
根据一个实施例，该方法还包括在该晶体管的该共用侧处的驱动器芯片，所述驱动器芯片包括源极输出端子和栅极输出端子，其中源极输出端子和栅极输出端子的顺序与该晶体管阵列的该共用侧处的第二导体和布线导体的顺序相匹配。
根据一个实施例，该第一层级在该第二层级之下。
根据一个实施例，所述层间导电连接形成均匀的层间连接阵列的一部分，该均匀的层间连接阵列还包括未连接到任何第一导体的层间连接。
参考附图，仅通过非限制性的示例在下文描述本发明的一个实施例，所述附图中：
图1是TFT阵列的栅极导体和源极导体的配置示例的平面示意图；以及
图2是TFT阵列的栅极导体和源极导体的配置示例的截面示意图。
出于简明的目的，图1和图2例示了小的4×4薄膜晶体管(TFT)阵列的栅极导体和源极导体的配置示例；但相同类型的配置可应用于更大的晶体管阵列，例如包含超过一百万个晶体管的晶体管阵列。图中所例示的装置可以在本发明的范围内进行修改，其修改方式的其他示例在说明书的末尾说明。
在支撑衬底30上提供第一图案化导体层。该支撑衬底30例如可包括塑料膜和形成于该塑料膜和该第一导体层之间的平坦化层以及一个或多个其它的功能层(例如导体层和/或绝缘体层)，所述功能层在该塑料膜和该平坦化层之间，和/或在该平坦化层和该第一图案化导体层之间，和/或在该塑料膜的与该平坦化层相对的一侧。
该第一图案化导体层被图案化以限定(i)源极导体2a、2b、2c、2d的阵列，在该示例中每个源极导体为相应的晶体管列提供源电极；以及漏极导体8的阵列，每个漏极导体为相应的晶体管提供漏电极。第一图案化导体层的此图案化可以例如通过光刻技术来实现。
在限定了源极导体2和漏极导体8的图案化的第一导体层上形成半导体层32，所述半导体层32为每个晶体管提供相应的半导体沟道。该半导体层32可以例如是通过液体处理技术(诸如旋涂或柔版印刷)沉积的有机聚合物半导体。
在该半导体层32上形成电介质层34，所述电介质层34为每个晶体管提供相应的栅极电介质。该电介质层可以例如包括一个或多个有机聚合物电介质层。
随后该半导体层32和电介质层34被图案化以限定一个或多个向下延伸至各个源极导体2的通孔。此图案化可通过例如激光烧蚀来执行。此图案化处理还可包括在所有其他对应的位置处(甚至在没有下层源极导体2(接合焊盘landingpad)12之处)形成冗余的通孔，其中冗余通孔13也用导电材料填充(在形成栅极导体4和布线导体6的第二导电层的沉积期间)以生成冗余层间连接。这些冗余层间连接并不连接到任何源极导体2，但在TFT阵列用于控制作为显示装置的一部分的光学介质的示例中，提供跨整个TFT阵列区域的层间连接13、14的均匀阵列从提供跨整个TFT阵列区域都具有均匀特性的显示器的角度来看是有利的。
在图案化的电介质层34和图案化的半导体层32上沉积导电材料，并且形成在电介质层34上延伸的第二导体层，所述导电材料填充每个通过上文提及的图案化步骤生成的通孔。
接着第二导体层被图案化以限定(i)栅极导体4的阵列，每个栅极导体为相应的晶体管行提供栅电极，和(ii)布线导体6的阵列，布线导体平行于栅极导体6地延伸并且每个布线导体位于相应的一对栅极导体4之间。第二导体层的图案化还限定了在漏极导体8的中心上的位置处的栅极导体4中的通孔。如下文所述，这些通孔允许在漏极导体8和相应的顶部像素导体42之间形成层间导电连接10。在第二导体层限定向下到达源极导体2的层间导电连接的位置处形成布线导体6。每个布线导体6例如通过由第二导体层限定的一对相应的层间导电连接14连接到相应的源极导体。栅极导体4和布线导体6共同终止于晶体管阵列的同一个边缘处。
由第一图案化导体层限定的源极导体2各自被配置为限定在与布线导体6基本上平行的方向上宽度相对大的相应的接合焊盘12。这些接合焊盘12促进从布线导体6向下至源极导体2的层间导电连接14的形成。
图2是沿着源极导体2中的一个的中心线截取的装置的一部分的截面图。出于更好地解释本发明的目的，图2的截面图示出了层间导电连接14，所述层间导电连接14向下延伸至相应的源极导体的一部分，位于该源极导体2的中心线上。
在该第二图案化导体层上形成绝缘体层36，以及在绝缘体层36上形成第三导体层38。该第三导体层38被图案化以限定被通孔穿透的基本上连续的导体层，所述通孔允许在漏极导体8之间形成穿过第二和第三导体层并向上到达相应的顶部像素导体42的层间导电连接10。该第三导体层的功能是屏蔽顶部像素导体42使其免受包括栅极导体4和布线导体6的所有下层导体的电位的影响。
在第三导体层上形成另一个绝缘体层40。绝缘体层36、40可以例如是有机聚合物绝缘体层。随后绝缘体层36、40、电介质层34以及半导体层32被图案化以限定经由在第三导体层中限定的通孔并经由在栅极导体4中限定的通孔向下延伸至每个漏极导体8的通孔。这些通孔的直径小于在栅极导体4和第三导体层中限定的通孔的直径以避免在层间导电连接10和第三导体层38和/或栅极导体4之间发生的任何电短路。
在顶部绝缘体层40上沉积导体材料。该导体材料填充在绝缘体层36、40、电介质层34和半导体层32中限定的通孔并在顶部绝缘体层40上形成第四导体层42。随后该第四导体层被图案化以形成像素导体42的阵列，每个像素导体与相应的漏极导体8相关联。该像素导体42例如可以用于控制在该第四导体层上提供的光学介质(未示出)。
第一、二、三、四导体层的材料的示例包括金属和金属合金。
在该晶体管阵列的源极导体4和布线导体6所终止的边缘处，栅极/源极驱动器芯片18被接合到衬底30上。栅极导体和布线导体各自连接至该驱动器芯片的相应的输出端子20。在这个示例中，驱动器芯片18被配置使得输出端子20的顺序与该栅极导体4和布线导体6的顺序相匹配。这避免了任何栅极导体4和布线导体6彼此交叉的必要，并有助于使该驱动器芯片18的位置更靠近晶体管阵列。
该单芯片驱动集成电路(IC)18包括栅极驱动块22、源极驱动块24、逻辑块26和存储器块28。逻辑块26的功能包括：在驱动器IC18和主处理单元(MPU)间交互；将数据传输到存储器28和从存储器28传输数据；将通过栅极和源极驱动块施加的信号调配至栅极导体4和布线(源极)导体6；以及控制输出数据传输至源极驱动块24。该驱动器IC18可包括其它块。
该驱动器芯片18的作用是(i)通过将适当的电压施加到相应的栅极导体4顺序地使晶体管在截止和导通状态之间切换，以及(ii)同时将相应的数据电压施加到所有的源极导体2(经由布线导体6)以在与处于导通状态的晶体管行相关联的每个像素导体处达到期望的相应电位。
在上述示例中，在相应的一对栅极导体之间提供一个源极布线导体6。变型的示例包括：(a)为多于一个的源极导体2/位于一对栅极导体4之间的晶体管列提供源极布线导体6，或者为多于一个的位于一对源极布线导体6之间的晶体管行提供栅极导体4。一般而言，栅极导体4与布线导体6的比例可以大于或小于1。根据一个特定示例，在每个相应的一对栅极导体4之间提供相应的一组两列晶体管的源极布线导体6，以使TFT阵列的晶体管列比晶体管行更多，有助于将用于源极导体和栅极导体的驱动晶片放置在该TFT阵列的同一较短的边缘处。
在上述示例中，使用单个的组合的栅极/源极驱动器芯片，其具有与TFT阵列边缘处的栅极导体和布线导体的顺序相匹配的源极输出端子和栅极输出端子。一个变型的示例包括：使用一个或多个驱动器芯片，其中源极输出端子分别地与栅极输出端子成组。图3示意地例示了一种在该变型中实现栅极导体和布线导体交叉的技术。图3涉及相应的一组两个源极导体2/一对栅极导体4之间的晶体管列的布线导体6的示例，但相同的技术也适用于任何其它比例的源极布线导体6(晶体管列)和栅极导体4(晶体管行)。限定源极导体2(图3中未示出)的第一导体层还限定了额外导体7，所述额外导体7从该TFT阵列边缘引向外并且位于从该TFT阵列的同一个边缘引向外的之后形成的栅极导体4的部分的下方。延伸超过该TFT阵列的这一边缘的电介质层34防止了这些额外导体7和栅极导体4之间的电短路。形成层间连接14的通孔的工艺包括在每个额外导体7之上的位置处形成额外通孔；并且沉积第二导体层的工艺也填充了这些额外通孔，从而在每个布线导体6和相应的额外导体7之间形成导电连接9。图3中的附图标记11表示另外的层间导电连接，所述另外的层间导电连接将每一个额外导体7和栅极导体6连接至一个或多个驱动器芯片所位于的层级。
上文的描述涉及顶栅晶体管阵列的示例。同类的技术也同样可应用于底栅晶体管阵列，对于底栅晶体管阵列的情况，第一图案化导体层、半导体层32、电介质层34和第二图案化导体层的沉积顺序是颠倒的，并且在栅极导体4中不需要限定通孔。
上文的描述涉及环形半导体沟道设计的示例，其中每个晶体管的漏电极被该晶体管的源电极包围在源极-漏极导体层内。上述的技术也同样可应用于其它半导体沟道设计，包括非环形半导体沟道设计和其它类型的环形半导体沟道设计。例如，每个晶体管的源电极和漏电极可包括叉指型结构。
上文的描述涉及为栅极导体和源极导体提供单个驱动器芯片的示例，但上述技术还可应用于例如其中为驱动源极导体和栅极导体提供单独的驱动器芯片的装置。
上文的描述涉及在与栅极导体同层级处提供位于栅极导体4之间的源极布线导体6；但另一示例包括在与源极导体同层级处提供位于源极导体之间的栅极布线导体，以及在每一个栅极布线导体和相应的栅极导体之间提供一个或多个层间导电连接。
上文描述的技术避免了下列需求：(a)在该晶体管阵列的不同边缘处具有分开的源极驱动器芯片和栅极驱动器芯片，或者(b)沿晶体管阵列的两个边缘布线源极导体或栅极导体；并且由此有助于减小所需的在晶体管阵列之外的衬底面积。另外，对于使用其源极输出端子和栅极输出端子的顺序与TFT阵列边缘处的源极导体和栅极导体的顺序相匹配的组合源极/驱动器芯片的示例，存在以下额外优势：晶体管阵列之外的所有导体可以被限定在同一层级(即在单个导体层中)。
除了上述特别提到的变型之外，对于本领域技术人员明显的是，在本发明的范围内可以对上述实施例进行各种其他变型。
这里本申请单独公布了本文所描述的各个单独特征以及两个或更多这种特征的组合，使得不论这些特征或特征的组合是否解决本文所揭露的任何问题，都能够依据本领域技术人员的一般常识以本说明书为基础实施这些特征或特征的组合，而不限于权利要求的范围。申请人表明本申请的方面可由任何这种单独特征或特征的组合组成。

Claims (8)

1.一种包含晶体管阵列的装置，其中所述装置包括：在第一层级的第一导体层，所述第一导体层限定了为所述晶体管阵列提供源电极或栅电极中的一个的多个第一导体；在第二层级的第二导体层，所述第二导体层限定了为所述晶体管阵列提供源电极或栅电极中的另一个的多个第二导体；其中所述第二导体层还在限定了所述第二导体之间的一个或多个位置处的布线导体，每个布线导体通过一个或多个层间导电连接连接到相应的第一导体。
2.如权利要求1所述的装置，其中所述第一导体为所述晶体管阵列提供源电极，而所述第二导体为所述晶体管阵列提供栅电极。
3.如权利要求2所述的装置，其中每个第一导体与所述晶体管阵列的相应的一个或多个列相关联，而每个第二导体与所述晶体管阵列的相应的一个或多个行相关联。
4.如权利要求1所述的装置，其中所述第一导体为所述晶体管阵列提供栅电极，而所述第二导体为所述晶体管阵列提供源电极。
5.如前述权利要求中的任何一项所述的装置，其中所述第二导体和所述布线导体终止于所述晶体管阵列的共用侧。
6.如权利要求5所述的装置，还包括在所述晶体管阵列的所述共用侧的驱动器芯片，所述驱动器芯片包括源极输出端子和栅极输出端子，其中所述源极输出端子和所述栅极输出端子的顺序与在所述晶体管阵列的所述共用侧处的所述第二导体和所述布线导体的顺序相匹配。
7.如前述权利要求中的任何一项所述的装置，其中所述第一层级在所述第二层级之下。
8.如前述权利要求中的任何一项所述的装置，其中所述层间导电连接形成均匀的层间连接阵列的一部分，所述均匀的层间连接阵列还包括未连接到任何第一导体的层间连接。
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