CN105514121A - 一种tft阵列基板及其制作方法 - Google Patents

一种tft阵列基板及其制作方法 Download PDF

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CN105514121A
CN105514121A CN201610051645.7A CN201610051645A CN105514121A CN 105514121 A CN105514121 A CN 105514121A CN 201610051645 A CN201610051645 A CN 201610051645A CN 105514121 A CN105514121 A CN 105514121A
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active layer
semiconductor active
insulating barrier
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drain electrode
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CN105514121B (zh
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梁博
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种TFT阵列基板及其制作方法，通过在衬底基板上形成类石墨烯结构的二维层状半导体材料，并将该类石墨烯结构的二维层状半导体材料通过转印的方式转印到柔性基板指定的位置上以用作阵列基板的半导体有源层，因此本发明的TFT阵列基板的半导体有源层采用类石墨烯结构的二维层状半导体材料，使得阵列基板具有非常高的迁移率及机械性能，抗挠性优异，并且大大缩减了基板的厚度。

Description

一种TFT阵列基板及其制作方法
技术领域
本发明涉及平板显示技术领域，特别是涉及一种TFT阵列基板及其制作方法。
背景技术
在现有平板显示技术之中，驱动所用TFT(thinfilmtransistor，薄膜晶体管)采用非晶硅(amorphousSilicon，简称a-Si)、低温多晶硅(lowtemperaturepoly-Silicon，简称LTPS)或者非晶IGZO作为半导体有源层。a-SiTFT的电子迁移率低于1cm2/V-1s-1，限制了显示面积和逻辑控制速度。LTPS虽然电子迁移率较高，但是漏电流大，会影响触摸精度和触控操作体验。非晶IGZO(IndiumGalliumZincOxide，铟镓锌氧化物)的漏电流较小，但是对于水、氧和光很敏感，会影响使用寿命。更重要的是，当以上几种技术中的非晶和多晶半导体材料用于柔性显示基板时，经过多次弯曲与折叠，极容易出现龟裂，进而会导致显示屏幕出现斑点、黑线和亮线等。
发明内容
有鉴于此，本发明提供一种TFT阵列基板及其制作方法，阵列基板具有高的迁移率及机械性能，抗挠性优异，并且减小基板的厚度。
本发明的一方面提供一种TFT阵列基板的制作方法，包括：
提供一硬性基板；
提供一柔性基板，柔性基板设置于硬性基板上；
在柔性基板上形成第一绝缘层，其中在第一绝缘层上方预设指定位置；
提供一衬底基板；
在衬底基板上形成类石墨烯结构的二维层状半导体材料，其中类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2；
将二维层状半导体材料转印到指定位置上；
对二维层状半导体材料进行氢化处理，以形成半导体有源层。
其中，二维层状材料具体为MoS2，在衬底基板上形成类石墨烯结构的二维层状半导体材料的步骤具体包括：
在衬底基板上形成Mo图形，Mo图形的位置与指定位置相对应；
采用MoO3和S材料在600℃至800℃的温度之间进行化学气相沉积，以在Mo图形上形成二维层状的MoS2。
其中，二维层状MoS2中同一层Mo原子形成的平面与柔性基板平行。
其中，单层二维层状MoS2的厚度为0.62至0.72nm。
其中，在提供一柔性基板的步骤之后，且在柔性基板上形成第一绝缘层的步骤之前，制作方法还包括：
在柔性基板上形成第一栅极，其中第一绝缘层覆盖第一栅极并延伸到柔性基板上，且第一栅极的位置与指定位置相对应。
其中，在对二维层状半导体材料进行氢化处理，以形成半导体有源层的步骤之后，方法还包括：
通过掩膜工艺在第一绝缘层上进一步形成源电极及漏电极，其中，源电极及漏电极通过半导体有源层间隔设置，并且，源电极及漏电极分别与半导体有源层接触。
其中，在对二维层状半导体材料进行氢化处理，以形成半导体有源层的步骤之后，方法还包括：
通过掩膜工艺在第一绝缘层上进一步形成源电极及漏电极，源电极及漏电极通过半导体有源层间隔设置，并且，源电极及漏电极分别与半导体有源层接触；
在源电极、漏电极及半导体有源层上方设置第二绝缘层；
在第二绝缘层上方形成第二栅极，其中第二栅极的位置与半导体有源层位置对应。
本发明的另一方面提供一种TFT阵列基板，包括：
一硬性基板；
一柔性基板，柔性基板设置于硬性基板上；
第一绝缘层，第一绝缘层设置于柔性基板上；
半导体有源层，半导体有源层设置于第一绝缘层上方预设的指定位置上，且半导体有源层为类石墨烯结构的二维层状半导体材料，其中类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2。
其中，阵列基板还包括：
第一栅极，第一栅极设置于柔性基板与第一绝缘层之间，且第一栅极与半导体有源层位置对应；
源电极及漏电极，源电极及漏电极通过半导体有源层间隔设置于第一绝缘层上，并且源电极及漏电极分别与半导体有源层接触。
其中，阵列基板还包括：
源电极及漏电极，源电极及漏电极通过半导体有源层间隔设置于第一绝缘层上，并且源电极及漏电极分别与半导体有源层接触；
第二绝缘层，第二绝缘层覆盖设置于半导体有源层、源电极及漏电极上；
第二栅极，第二栅极设置于第二绝缘层上，且第二栅极的位置与半导体有源层位置对应。
通过上述方案，本发明的有益效果是：区别于现有技术，本发明的TFT阵列基板包括柔性基板，通过转印的方式将类石墨烯结构的二维层状半导体材料转印到柔性基板的指定位置上用作TFT阵列基板的半导体有源层，从而本发明的TFT阵列基板具有非常高的迁移率及机械性能，抗挠性优异，并且大大缩减了基板的厚度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的TFT阵列基板的结构示意图；
图2是图1中的TFT阵列基板的制作方法流程示意图；
图3是形成图1中TFT阵列基板的第一栅极的示意图；
图4是形成图1中TFT阵列基板的第一绝缘层的示意图；
图5是形成图1中TFT阵列基板的半导体有源层的示意图；
图6是本发明第二实施例的TFT阵列基板的结构示意图；
图7是图6中的TFT阵列基板的制作方法流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参看图1，图1是本发明第一实施例的TFT阵列基板的结构示意图。如图1所示，本实施例的TFT阵列基板1包括硬性基板100及设置于硬性基板100上方的柔性基板101。柔性基板101上方设置有第一栅极111，第一绝缘层113覆盖第一栅极111且延伸到柔性基板101上，半导体有源层112设置于第一绝缘层113上，且半导体有源层112与第一栅极111的位置对应，半导体有源层112为类石墨烯结构的二维层状半导体材料，其中该类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2。优选的，半导体有源层112的材料为MoS2。并且，半导体有源层112两侧还分别设置有源电极114及漏电极115，源电极114及漏电极115通过半导体有源层112间隔设置于第一绝缘层113上，并且源电极114及漏电极115分别与半导体有源层112接触。
结合图1、图3至图5参看图2，本实施例的TFT阵列基板的制作方法包括：
S11：提供一硬性基板100。
硬性基板100可以使用但不限于使用玻璃，硅晶圆片，石英片，金属片，碳化硅晶圆片。
S12：提供一柔性基板101。
柔性基板101设置于硬性基板100上方，柔性基板101可以是聚酰亚胺(PI)，聚醚酰亚胺(PEI)，聚苯硫醚(PPS)，聚芳酯(PAR)中一种或几种的组合，也可以是以上化合物经过纤维强化作为柔性基板101。
S13：在柔性基板101上形成第一栅极111。
在柔性基板101上方指定位置上形成第一栅极111，如图3所示，第一栅极111采用现有技术中的半导体器件中使用的金属、导电氧化物或者石墨烯形成。此外，还在柔性基板101上形成栅线(图未示)。
S14：在柔性基板101上形成第一绝缘层113。
在第一栅极111及柔性基板101上形成第一绝缘层113，如图4所示，第一绝缘层113覆盖第一栅极111并延伸到柔性基板101上。第一绝缘层113可以由硅(Si)氧化物，硅氮化物，硅氮氧化物，铝(Al)氧化物，铪(Hf)氧化物，或钛(Ti)氧化物或有机聚合材料形成，也可由以上中的两种及两种以上材料形成。第一绝缘层113的厚度为10nm至50nm。
并且，在第一绝缘层113上方预设指定位置，并使该指定位置与第一栅极111的位置相对应，其中该指定位置用于形成半导体有源层112，这将在以下内容中进行阐述。
S15：提供一衬底基板。
S16：在衬底基板上形成类石墨烯结构的二维层状半导体材料。
衬底基板可以为刚性的基板，也可以为柔性的基板，如耐高温金属薄片，在此不作限制。
类石墨烯结构的二维层状半导体材料为MoS2(二硫化钼)、MoSe2(硒化钼)、WS2(硫化钨)、WSe2(硒化钨)或SnS2(硫化锡)。
本实施例以MoS2为例说明，MoS2是一种类石墨烯结构的二维层状材料，其迁移率超过200cm2/V-1s-1，开关电流大于108，MoS2中层内原子通过共价键结合，机械强度比刚高30倍，有非常高的机械性能，抗挠曲性优异，且单层二维层状MoS2结构的厚度为0.62nm至0.72nm，在本实施例中，优选单层二维层状MoS2结构的厚度为0.65nm。
首先在衬底基板上形成Mo(钼)图形，Mo图形在衬底基板的位置与柔性基板101上方的第一绝缘层113的指定位置相对应。利用该Mo图形中的Mo作催化剂，使用MoO3(三氧化钼)与S(硫)材料在耐高温的衬底基板上进行化学气相沉积，其进行化学气相沉积的温度为600℃至800℃的温度之间，从而在衬底基板的Mo图形的位置上催化生长形成二维层状的MoS2。其中，二维层状的MoS2的结构受沉积时间和温度控制，如通过沉积时间控制，可以形成单层的MoS2或双层的MoS2，其中双层的MoS2的沉积时间是单层的MoS2的沉积时间的两倍。又如通过温度的控制，可以形成单晶或多晶的MoS2，在600℃或更低的温度下得到多晶结晶的MoS2，在800℃或更高的温度下得到单晶结晶的MoS2。优选的，本实施例的MoS2为单晶单层的结构。
在其他实施例中，如采用WS2材料，则在衬底基板上形成W(钨)图形利用W作催化剂化学气相沉积形成WS2。
S17：将二维层状半导体材料转印到指定位置上。
S18：对二维层状半导体材料进行氢化处理，以形成半导体有源层112。
本实施例指将MoS2转印到第一绝缘层113的预设的指定位置上，并对MoS2进行氢化处理，以在第一绝缘层113的指定位置上形成半导体有源层112，如图5所示。优选的，该半导体有源层112的材料为MoS2，其中，为了保护阵列基板的机械强度，二维层状MoS2中同一层Mo原子形成的平面与柔性基板101平行。
通过在衬底基板上形成类石墨烯结构的二维层状半导体材料，并进一步将类石墨烯结构的二维层状半导体材料转印到柔性基板101上形成半导体有源层112，这是由柔性基板101的特性决定的。由于柔性基板101的要求较多，如阻水氧，柔性，耐受ELA(准分子激光退火技术)温度，热膨胀系数与金属和绝缘层接近，表面粗糙度很低，翘曲度很小等等，因此，符合要求制作柔性基板101的材料的耐高温性能欠佳。所以需要在额外的衬底基板上先制作形类石墨烯结构的二维层状半导体材料，再进一步将该类石墨烯结构的二维层状半导体材料转印到柔性基板101上形成半导体有源层112。
这里强调一下，在衬底基板上制作类石墨烯结构的二维层状半导体材料时要求限定类石墨烯结构的二维层状半导体材料在衬底基板的位置对应柔性基板101上方的第一绝缘层113的预设指定位置，这是为了在转印的时候可以准确的将类石墨烯结构的二维层状半导体材料转印到指定位置上。其制程可通过在衬底基板上形成Mo图形时限定Mo图形在衬底基板的位置，该Mo图案在衬底基板的位置与第一绝缘层113上预设的指定位置相对应，即Mo图案在衬底基板的位置与TFT阵列基板上所需的半导体有源层112的位置相对应，从而在进行化学气相沉积时，在Mo图案的位置上形成MoS2。并且，在转印前分别在衬底基板及柔性基板101上作对应的标记，利用对应的标记作对准进行转印。其中，衬底基板上的MoS2可通过sheet–to-sheet(刚性)或者roll-to-sheet(柔性)的方式转印到柔性基板101上，并且，可以进行多次转印，如当柔性基板101的面积较大而衬底基板的面积较小时，可通过多次转印，以实现更大面积的使用MoS2。
S19：通过掩膜工艺在第一绝缘层113上进一步形成源电极114及漏电极115。
通过掩膜工艺在第一绝缘层113上形成源电极114及漏电极115，并且源电极114及漏电极115通过半导体有源层112间隔设置，并且，源电极114及漏电极115分别与半导体有源层112接触，如图1所示。
其中，源电极114和漏电极115可以选用与MoS2形成欧姆接触的金属材料的一种或几种的组合。或者在MoS2与源电极114和漏电极115之间首先形成欧姆接触层(图未示)，这样也可以使用不与MoS2形成欧姆接触的一种或几种金属，或者是导电金属氧化物。
综上，本实施例的TFT阵列基板及其制作方法所阐述的是背栅晶体管，其通过转印的方式在柔性基板101上方形成材料MoS2的半导体有源层112，因此使得柔性显示的TFT阵列基板1具有非常高的机械性能，抗挠曲性优异，且使用MoS2作为半导体有源层112，可大大减小基板的厚度，并可实现透明显示。此外，由于MoS2有禁带，无悬挂键，因此，使用MoS2作半导体电子器件可以实现稳定运行，同时使得第一栅极111的漏电流减小，并且，基于二维层状的MoS2场效应管电子迁移率超过200cm2/V-1s-1，开关电流比超过108，既可以实现大面积柔性显示，又可以在关闭时实现完全黑暗的屏幕背景。
请进一步参看图6，图6是本发明第二实施例的TFT阵列基板的结构示意图。其中，图6所示的TFT阵列基板2与图1所示第一实施例的TFT阵列基板1的区别在于，图1所示的TFT阵列基板1为背栅式的晶体管，而图6所示的TFT阵列基板2为顶栅式的晶体管，其顶栅结构有利于提高场效应单位面积集成度，同时使用更小的电压就可以对器件进行开关操作。
如图6所示，本实施例的TFT阵列基板2包括硬性基板100、设置于硬性基板100上的柔性基板101、第一绝缘层113设置于柔性基板101上，半导体有源层112设置于第一绝缘层113的预设的指定位置上，其中，该半导体有源层112为类石墨烯结构的二维层状半导体材料，类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2。源电极114和漏电极115设置于第一绝缘层113上方，且间隔设置于半导体有源层112两侧并分别与半导体有源层112接触，在半导体有源层112、源电极114和漏电极115的上方还覆盖设置有第二绝缘层116，在第二绝缘层116上方设置有第二栅极117，第二栅极117的位置与半导体有源层112的位置相对应。
请进一步参看图7，本实施例的TFT阵列基板的制作方法包括：
S21：提供一硬性基板100。
S22：提供一柔性基板101。
S23：在柔性基板101上形成第一绝缘层113。
S24：提供一衬底基板。
S25：在衬底基板上形成类石墨烯结构的二维层状半导体材料。
S26：将二维层状半导体材料转印到第一绝缘层113的指定位置上。
S27：对二维层状半导体材料进行氢化处理，以形成半导体有源层112。
S28：通过掩膜工艺在第一绝缘层113上进一步形成源电极114及漏电极115。
S29：在源电极114、漏电极115及半导体有源层112上方设置第二绝缘层116。
S30：在第二绝缘层116上方形成第二栅极117。
其中，本实施例的TFT阵列基板与上述实施例的阵列基板的制作工艺上的差别在于，为保证柔性显示阵列基板中器件稳定性和良好接触，本实施例的TFT阵列基板先在柔性基板101上形成第一绝缘层113，然后在衬底基板上形成的类石墨烯结构的二维层状半导体材料转印到第一绝缘层113的预设的指定位置上，进一步对类石墨烯结构的二维层状半导体材料进行氢化处理形成半导体有源层112，然后通过掩膜工艺在第一绝缘层113上形成源电极114及漏电极115，即在半导体有源层112两侧形成源电极114及漏电极115，源电极114及漏电极115通过半导体有源层112间隔设置，且源电极114及漏电极115分别与半导体有源层112接触。然后再在半导体有源层112、源电极114及漏电极115上方覆盖设置第二绝缘层116及第二栅极117，第二栅极117设置于第二绝缘层116上方且与半导体有源层112的位置对应。
综上所述，区域别于现有技术，本发明的TFT阵列基板通过采用类石墨烯结构的二维层状半导体材料作为半导体有源层，从而使得TFT阵列基板具有非常高的迁移率及机械性能，抗挠性优异，并且大大缩减了基板的厚度。
需要强调的是，本发明的TFT阵列基板可用于LCD(liquidcrystaldisplay)、OLED(organiclight-emittingdiode)、EPD(electrophoresisdisplay)、EWP(electrowettingdisplay)等。并且，TFT可为像素单元内的TFT，也可以为GOA电路的TFT。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种TFT阵列基板的制作方法，其特征在于，所述制作方法包括：
提供一硬性基板；
提供一柔性基板，所述柔性基板设置于所述硬性基板上；
在所述柔性基板上形成第一绝缘层，其中在所述第一绝缘层上方预设指定位置；
提供一衬底基板；
在所述衬底基板上形成类石墨烯结构的二维层状半导体材料，其中所述类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2；
将所述二维层状半导体材料转印到所述指定位置上；
对所述二维层状半导体材料进行氢化处理，以形成半导体有源层。
2.根据权利要求1所述的制作方法，其特征在于，所述二维层状材料具体为MoS2，所述在所述衬底基板上形成类石墨烯结构的二维层状半导体材料的步骤具体包括：
在所述衬底基板上形成Mo图形，所述Mo图形的位置与所述指定位置相对应；
采用MoO3和S材料在600℃至800℃的温度之间进行化学气相沉积，以在所述Mo图形上形成二维层状的MoS2。
3.根据权利要求2所述的制作方法，其特征在于，所述二维层状MoS2中同一层Mo原子形成的平面与所述柔性基板平行。
4.根据权利要求3所述的制作方法，其特征在于，单层所述二维层状MoS2的厚度为0.62nm至0.72nm。
5.根据权利要求1所述的制作方法，其特征在于，在所述提供一柔性基板的步骤之后，且在所述柔性基板上形成第一绝缘层的步骤之前，所述制作方法还包括：
在所述柔性基板上形成第一栅极，其中所述第一绝缘层覆盖所述第一栅极并延伸到所述柔性基板上，且所述第一栅极的位置与所述指定位置相对应。
6.根据权利要求5所述的制作方法，其特征在于，在所述对所述二维层状半导体材料进行氢化处理，以形成所述半导体有源层的步骤之后，所述方法还包括：
通过掩膜工艺在所述第一绝缘层上进一步形成源电极及漏电极，其中，所述源电极及漏电极通过所述半导体有源层间隔设置，并且，所述源电极及所述漏电极分别与所述半导体有源层接触。
7.根据权利要求1所述的制作方法，其特征在于，在所述对所述二维层状半导体材料进行氢化处理，以形成所述半导体有源层的步骤之后，所述方法还包括：
通过掩膜工艺在所述第一绝缘层上进一步形成源电极及漏电极，所述源电极及漏电极通过所述半导体有源层间隔设置，并且，所述源电极及所述漏电极分别与所述半导体有源层接触；
在所述源电极、所述漏电极及所述半导体有源层上方设置第二绝缘层；
在所述第二绝缘层上方形成第二栅极，其中所述第二栅极的位置与所述半导体有源层位置对应。
8.一种TFT阵列基板，其特征在于，所述阵列基板包括：
一硬性基板；
一柔性基板，所述柔性基板设置于所述硬性基板上；
第一绝缘层，所述第一绝缘层设置于所述柔性基板上；
半导体有源层，所述半导体有源层设置于所述第一绝缘层上方预设的指定位置上，且所述半导体有源层为类石墨烯结构的二维层状半导体材料，其中所述类石墨烯结构的二维层状半导体材料为MoS2、MoSe2、WS2、WSe2或SnS2。
9.根据权利要求8所述的阵列基板，其特征在于，所述阵列基板还包括：
第一栅极，所述第一栅极设置于所述柔性基板与所述第一绝缘层之间，且所述第一栅极与所述半导体有源层位置对应；
源电极及漏电极，所述源电极及漏电极通过所述半导体有源层间隔设置于所述第一绝缘层上，并且所述源电极及所述漏电极分别与所述半导体有源层接触。
10.根据权利要求8所述的阵列基板，其特征在于，所述阵列基板还包括：
源电极及漏电极，所述源电极及漏电极通过所述半导体有源层间隔设置于所述第一绝缘层上，并且所述源电极及所述漏电极分别与所述半导体有源层接触；
第二绝缘层，所述第二绝缘层覆盖设置于所述半导体有源层、所述源电极及所述漏电极上；
第二栅极，所述第二栅极设置于所述第二绝缘层上，且所述第二栅极的位置与所述半导体有源层位置对应。
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